CN101308330B - Two time graph exposure method utilizing developing filler material - Google Patents
Two time graph exposure method utilizing developing filler material Download PDFInfo
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- CN101308330B CN101308330B CN2007100407130A CN200710040713A CN101308330B CN 101308330 B CN101308330 B CN 101308330B CN 2007100407130 A CN2007100407130 A CN 2007100407130A CN 200710040713 A CN200710040713 A CN 200710040713A CN 101308330 B CN101308330 B CN 101308330B
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Abstract
The invention discloses a double-graphics exposure method which makes use of developable filling materials; after completing the first lithography and etching, and peeling off the remainder first anti-reflective layer and first photoresist, the method coats the developable filling material on the surface of a silicon wafer through a wet method so as to fill the gap between substrates to be etched; then the filling material is removed from the surface of the substrates to be etched by developing the filling material, so as to form a level interface; then the second lithography, etching and other technologies are carried through so as to eliminate the instability of the second lithography and etching technology caused by the height changes of the surface morphology step in the traditional double-graphics exposure technology to improve the performance of the double-graphics exposure technology. The method of the invention does not need to cover a hard mask layer on the substrates so as to reduce the complexity of the double-graphics exposure technology and improve the conductivity of the produced chips to some extent.
Description
Technical field
The present invention relates to a kind of manufacture method of SIC (semiconductor integrated circuit), but relate in particular to a kind of secondary image exposure method that on the integrated circuit substrate, utilizes developing material.
Background technology
Along with dwindling of chip size, traditional single optical patterning technology can not satisfy the demand of semiconductor technology evolves, in order further to excavate and to utilize the potentiality of existing equipment and even realize more tiny chip live width, secondary image exposure technology (Double Patterning) is arisen at the historic moment.
But also there is more problem in present secondary image exposure technology, shown in Fig. 1 a-1d, in the prior art, uses the positive photoresist exposure imaging to realize that the basic procedure of secondary image exposure technology is as follows:
(1) (Hard Mask, HM) 102 (for example silicon dioxide, silicon nitride, metal silicide) of the hard mask of deposit one deck on the substrate 101 to be etched;
(2) first anti-reflecting layers (Bottom Anti-Reflection Coating, BARC) 103 the coating and first photoresist (Photo Resist, PR) 104 coating;
(3) carry out the photoetching first time, at this moment the cross-section structure of silicon chip as shown in Figure 1a;
(4) carry out the etching first time, at first etch into first antireflecting coating 103 of non-photoresist protection zone, utilize first photoresist 104 as the etching masking layer subsequently, finish hard mask 102 etchings, this etching stopping is in substrate to be etched 101 surfaces;
(5) peel off first anti-reflecting layer 103 and first photoresist 104, at this moment the cross-section structure of silicon chip is shown in Fig. 1 b;
The coating of (6) second anti-reflecting layers 105, the coating of second photoresist 106;
(7) carry out the photoetching second time, at this moment the cross-section structure of silicon chip is shown in Fig. 1 c;
(8) carry out the etching second time, at first etch away second antireflecting coating 105 that covers hard mask 102 and non-photoresist protection zone, utilize the hard mask 102 and second photoresist 106 subsequently, the substrate 101 that etching exposes jointly as the etching masking layer.
(9) peel off remaining second anti-reflecting layer 105 and second photoresist 106, clean then, at this moment the cross-section structure of silicon chip is shown in Fig. 1 d;
(10) peel off remaining hard mask 102.
In this technological process, there is following shortcoming: because the etching selection ratio of hard mask layer and backing material is not high, therefore its thickness is thicker, the coating thickness that causes second antireflecting coating differs greatly in graphics intensive zone and the loose zone of figure, and then can influence follow-up photoetching, etching technics, cause being difficult to carry out accurate, repeatable explained hereafter.And, owing to need to apply one deck hard mask layer, with carry out second time during etching and second photoresist together as the etching masking layer, formation chip live width has improved the complicacy of technology thus; And the adding of described hard mask layer, also can affect to the electric conductivity of the chip finally made.
Summary of the invention
But the technical problem to be solved in the present invention provides a kind of secondary image exposure method of utilization developing filler material, can avoid producing the problem that coating thickness is regional in graphics intensive and the loose zone of figure differs greatly of antireflecting coating for the second time, thereby improve the stability of photoetching for the second time and etching technics, improve the performance of secondary image exposure technology; And can apply hard mask layer, realize the complicacy of secondary image exposure technology thereby reduced, and improved the electric conductivity of chip.
For solving the problems of the technologies described above, but the invention provides a kind of secondary image exposure method of utilization developing filler material, may further comprise the steps:
(1) goes up coating one deck first anti-reflecting layer (202) at substrate to be etched (201), apply first photoresist (203) then;
(2) carry out the photoetching first time;
(3) carry out the etching first time;
(4) peel off first photoresist (203) and remaining first anti-reflecting layer (202);
(5) packing material that can develop with wet method (204) is coated in silicon chip surface, fills the gap between the substrate to be etched (201);
(6) develop through the silicon chip after packing material (204) coating, remove the packing material (204) of substrate to be etched (201) surface, realize the smooth performance of silicon chip surface;
(7) apply second anti-reflecting layer (205), apply second photoresist (206) then;
(8) carry out the photoetching second time;
(9) carry out the etching second time;
(10) peel off second photoresist (206) and remaining second anti-reflecting layer (205) and packing material (204), clean then.
The present invention is owing to adopted technique scheme, has such beneficial effect, promptly by finishing photoetching for the first time, etching, and peeled off remaining first anti-reflecting layer, after first photoresist, adopt wet method can develop the fillibility coated materials at silicon chip surface, to fill the gap between the substrate to be etched, remove described fillibility material on the substrate surface to be etched by the mode that described packing material is developed then, thereby form smooth interface, and then carry out the photoetching second time, technologies such as etching, thereby eliminated the photoetching of introducing owing to the height change of surface topography step in the traditional secondary image exposure technical matters second time, the instability of etching technics, the performance that has improved the secondary image exposure technology.And, because the method for the invention need not cover one deck hard mask layer on substrate, therefore reduced the complicacy of secondary image exposure technology, and improved the electric conductivity of made chip to a certain extent.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 a to Fig. 1 d is the silicon chip section of structure that utilizes the existing techniques in realizing secondary image exposure;
Fig. 2 is the schematic flow sheet that but the utilization developing filler material is realized secondary image exposure according to the present invention;
Fig. 3 a to Fig. 3 f is the silicon chip section of structure that but the utilization developing filler material is realized secondary image exposure according to the present invention.
Embodiment
As shown in Figure 2, but realize the schematic flow sheet of secondary image exposure for utilization developing filler material of the present invention, its detailed process is as follows:
On substrate 201 to be etched, apply the first anti-emission coating (Bottom Anti-ReflectionCoating) 202, coating thickness is 10 nanometer to 10000 nanometers, baking temperature is that 50 ℃ to 250 ℃, stoving time are 10 seconds to 1000 seconds.Described first anti-reflecting layer can adopt following material: amorphous silicon, silicon nitride, silicon oxynitride, monox, doped silicon oxide, siloxicon, nitride, silicon nitride, titanium, titanium dioxide etc.Then, on the silicon chip that has applied first anti-reflecting layer 202, apply first photoresist (Photo Resist, PR) 203, coating thickness is 10 nanometer to 10000 nanometers, baking temperature is that 50 ℃ to 250 ℃, stoving time are 10 seconds to 1000 seconds.
Silicon chip is carried out the photoetching first time, thereby form the cross-section structure shown in Fig. 3 a.Subsequently, described silicon chip is carried out the etching first time, utilize first photoresist 203, etch away first anti-reflecting layer 202 and the substrate to be etched 201 that are positioned at non-first photoresist 203 protection zones as the etching masking layer.After the described first time, etching was finished, peel off first photoresist 203 and remaining first anti-reflecting layer 202, thereby form the silicon chip cross-section structure shown in Fig. 3 b.
The packing material 204 that can develop with wet method is coated in silicon chip surface, waits to carve gap between the substrate 201 with filling.In the present invention, described packing material 204 can be by ketone, ethers, organic solvents such as alkanes, antireflection absorbing material, can constitute with the organic acid group resin of standard Tetramethylammonium hydroxide developer solution reaction and the organic group resin that contains oxygen, fluorine element, cross-linked resin constitutes, its molecular weight is between 1000 to 50000, and refractive index is between 1.0 to 3.0, and extinction coefficient is between 0.1 to 3.0.Can fill gap between the substrate 201 to be etched effectively in order to ensure packing material 204, can carry out the coating of 1～3 packing material 204 according to actual conditions, whenever after finishing the coating of a packing material 204, all tackle to apply to show and detect, to check whether it satisfies the requirement of filling the gap between the substrate 201 to be etched, if backlog demand then can apply for the 2nd～3 time, till meeting the demands.In one embodiment, the coating dosage of each coated packing material 204 is 0.5ml to 5ml, and baking temperature is 60 ℃ to 250 ℃, and stoving time is 10 seconds to 120 seconds.The silicon chip cross-section structure of finishing after packing material applies can be referring to Fig. 3 c.
Develop through the silicon chip after packing material 204 coatings,, realize the smooth performance of silicon chip surface to remove the packing material 204 of substrate to be etched 201 surfaces.In the developing process, the temperature of used developer solution is 10 ℃ to 30 ℃, and the development soak time is 10 seconds to 120 seconds, re-uses the deionized water rinsing silicon chip surface subsequently, and to remove developer solution, flush time is 10 to 120 seconds.In order to remove the packing material 204 of substrate to be etched 201 surfaces clean, realize smooth silicon chip surface, can carry out 1～3 time according to actual conditions develops, whenever after finishing once development, all tackling the performance of developing and detecting,, then can carry out the 2nd～3 time and develop if finding that substrate 201 surfaces are also residual has a packing material, packing material until substrate 201 surfaces is all removed, and silicon chip surface is comparatively smooth.In one embodiment, each developer solution consumption that develops is 1ml to 100ml, and temperature is 10 ℃ to 30 ℃, and the development soak time is 10 seconds to 120 seconds.Can be through the silicon chip cross-section structure after developing with reference to figure 3d.
Applying second anti-reflecting layer 205 through the silicon chip surface after developing, coating thickness is 10 nanometer to 10000 nanometers, and baking temperature is that 50 ℃ to 250 ℃, stoving time are 10 seconds to 1000 seconds.Wherein, described second anti-reflecting layer 205 can adopt following material: amorphous silicon, silicon nitride, silicon oxynitride, monox, doped silicon oxide, siloxicon, nitride, silicon nitride, titanium, titanium dioxide etc.Then, apply second photoresist 206 again at the silicon chip surface that has applied second anti-reflecting layer 205, applied thickness is that 10 nanometer to 10000 nanometers, baking temperature are that 50 ℃ to 250 ℃, stoving time are 10 seconds to 1000 seconds.
Silicon chip is carried out the photoetching second time, form the cross-section structure shown in Fig. 3 e.Subsequently, described silicon chip is carried out the etching second time, utilize second photoresist 206, etch away second anti-reflecting layer 205 and the substrate to be etched 201 that are positioned at non-second photoresist 206 protection zones as the etching masking layer.After described second time, etching was finished, but peel off second photoresist 206 and remaining second anti-reflecting layer 205 and wet method developing filler material 204, and silicon chip cleaned, thereby finished whole secondary image exposure process, the cross-section structure of final formed silicon chip is shown in Fig. 3 f, and as can be seen from the figure last formed chip has less live width.
In sum, the method of the invention, but not only by utilizing developing filler material, avoid producing the problem that coating thickness is regional in graphics intensive and the loose zone of figure differs greatly of antireflecting coating for the second time, therefore improved the stability of photoetching for the second time, etching technics in the secondary image exposure technology; And, the etching masking layer when not needing to apply hard mask layer and being used as etching for the second time, the therefore complexity that realizes of the technology that reduces, and owing to there is not the participation of hard mask layer, makes and finally make the electric conductivity of chip to a certain degree being improved.
Claims (5)
1. but a secondary image exposure method that utilizes developing filler material is characterized in that, may further comprise the steps:
(1) on silicon chip, applies one deck first anti-reflecting layer (202), apply first photoresist (203) then;
(2) carry out the photoetching first time;
(3) utilize first photoresist (203) as the etching masking layer, etch away first anti-reflecting layer (202) and the silicon chip that are positioned at non-first photoresist (203) protection zone;
(4) peel off first photoresist (203) and remaining first anti-reflecting layer (202);
(5) packing material that can develop with wet method (204) is coated in silicon chip surface, fill the gap between the silicon chip, described packing material (204) is by ketone, ethers, the alkanes organic solvent, the antireflection absorbing material, can with the organic acid group resin of standard Tetramethylammonium hydroxide developer solution reaction, and contain oxygen, the organic group resin of fluorine element, cross-linked resin constitutes, its molecular weight is between 1000 to 50000, refractive index is between 1.0 to 3.0, and extinction coefficient is between 0.1 to 3.0, and the coating dosage of each coated packing material (204) is 0.5ml to 5ml, baking temperature is 60 ℃ to 250 ℃, and stoving time is 10 seconds to 120 seconds;
(6) develop through the silicon chip after packing material (204) coating, remove the packing material (204) of silicon chip surface top, realize the smooth performance of silicon chip surface;
(7) applying second anti-reflecting layer (205), apply second photoresist (206) again at the silicon chip surface that has applied second anti-reflecting layer (205) then through the silicon chip surface after developing;
(8) carry out the photoetching second time;
(9) utilize second photoresist (206) as the etching masking layer, etch away second anti-reflecting layer (205) and the silicon chip that are positioned at non-second photoresist (206) protection zone;
(10) peel off second photoresist (206) and remaining second anti-reflecting layer (205) and packing material (204), clean then.
2. but the secondary image exposure method of utilization developing filler material according to claim 1, it is characterized in that, when carrying out described step (5), should carry out the coating of 1～3 packing material (204) according to actual conditions, whenever finish the coating of a packing material (204) after, all tackle applying performance and detect, to check whether it satisfies the requirement of filling the gap between the silicon chip, if backlog demand then can apply for the 2nd～3 time, till meeting the demands.
3. but the secondary image exposure method of utilization developing filler material according to claim 2, it is characterized in that, when carrying out described step (6), should carry out 1～3 time according to actual conditions and develop, whenever finish once develop after, all tackle development and showing and detect, if find that the surface of silicon chip is also residual packing material (204) arranged, then can carry out the 2nd～3 time and develop, all remove until the packing material (204) of silicon chip surface top, silicon chip surface is smooth.
4. but the secondary image exposure method of utilization developing filler material according to claim 3 is characterized in that, each developer solution consumption that develops is 1ml to 100ml, and temperature is 10 ℃ to 30 ℃, and the development soak time is 10 seconds to 120 seconds.
5. but the secondary image exposure method of utilization developing filler material according to claim 4 is characterized in that, after packing material (204) is developed, also need use the deionized water rinsing silicon chip surface, and to remove developer solution, flush time is 10 to 120 seconds.
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| CN2007100407130A CN101308330B (en) | 2007-05-16 | 2007-05-16 | Two time graph exposure method utilizing developing filler material |
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| CN2007100407130A CN101308330B (en) | 2007-05-16 | 2007-05-16 | Two time graph exposure method utilizing developing filler material |
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| CN101308330B true CN101308330B (en) | 2010-12-15 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101630630B (en) * | 2009-08-04 | 2015-04-29 | 上海集成电路研发中心有限公司 | Method for preventing lateral erosion in wet etching |
| CN102841514A (en) * | 2011-06-23 | 2012-12-26 | 上海华虹Nec电子有限公司 | Method for implementing exposure of high-step surface graph by wet developable filling material |
| CN103337566A (en) * | 2013-06-19 | 2013-10-02 | 上海大学 | Patterned substrate manufacturing method |
| CN105842981B (en) * | 2016-05-03 | 2020-01-07 | 岭南师范学院 | Preparation method of low-cost precision chip die photoetching mask |
| CN113764260A (en) * | 2020-06-01 | 2021-12-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| CN1855418A (en) * | 2005-04-20 | 2006-11-01 | 上海集成电路研发中心有限公司 | Use of Dimashg process in production of integrated circuits |
| CN1855419A (en) * | 2005-04-20 | 2006-11-01 | 上海集成电路研发中心有限公司 | Manufacture by Dimashg process |
| CN1885521A (en) * | 2005-06-23 | 2006-12-27 | 中国科学院微电子研究所 | Preparation method of organic molecular device with cross line array structure |
| CN1914715A (en) * | 2004-01-30 | 2007-02-14 | 应用材料公司 | Techniques for the use of amorphous carbon(apf) for various etch and litho integration scheme |
| CN1925131A (en) * | 2005-09-02 | 2007-03-07 | 上海集成电路研发中心有限公司 | Process for reducing surface reflection index in semiconductor Damascus copper |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1914715A (en) * | 2004-01-30 | 2007-02-14 | 应用材料公司 | Techniques for the use of amorphous carbon(apf) for various etch and litho integration scheme |
| CN1855418A (en) * | 2005-04-20 | 2006-11-01 | 上海集成电路研发中心有限公司 | Use of Dimashg process in production of integrated circuits |
| CN1855419A (en) * | 2005-04-20 | 2006-11-01 | 上海集成电路研发中心有限公司 | Manufacture by Dimashg process |
| CN1885521A (en) * | 2005-06-23 | 2006-12-27 | 中国科学院微电子研究所 | Preparation method of organic molecular device with cross line array structure |
| CN1925131A (en) * | 2005-09-02 | 2007-03-07 | 上海集成电路研发中心有限公司 | Process for reducing surface reflection index in semiconductor Damascus copper |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131216 |
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Effective date of registration: 20131216 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |