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CN101211900A - 包含电子元件的基板 - Google Patents

包含电子元件的基板 Download PDF

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Publication number
CN101211900A
CN101211900A CNA200710160631XA CN200710160631A CN101211900A CN 101211900 A CN101211900 A CN 101211900A CN A200710160631X A CNA200710160631X A CN A200710160631XA CN 200710160631 A CN200710160631 A CN 200710160631A CN 101211900 A CN101211900 A CN 101211900A
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circuit board
electronic component
substrate
opening portion
soldered ball
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井上明宣
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Shinko Electric Industries Co Ltd
Shinko Electric Co Ltd
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Shinko Electric Co Ltd
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Abstract

本发明涉及一种包含电子元件的基板，其中电子元件安装在一对布线基板之间，布线基板通过焊球进行电气连接，在面对安装有电子元件的一个布线基板的另一个布线基板上与电子元件相对的位置处形成比电子元件的平面形状开得更大的开口部分，并且用密封树脂密封一对布线基板之间的间隙。

Description

包含电子元件的基板
本申请要求2006年12月26日提交给日本专利局的申请号为2006-348750的日本专利申请的优先权，申请号为2006-348750的日本专利申请的整个内容已经通过引用合并入本申请中。
技术领域
本发明涉及一种包含电子元件的基板，尤其涉及其中在一对布线基板之间安装电子元件的一种包含电子元件的基板。
背景技术
已经提出一种包含电子元件的基板100，其通过在下层侧上的布线基板10和上层侧上的布线基板20之间安装电子元件30、通过焊球40电气连接布线基板10和布线基板20、并且在布线基板10和布线基板20之间的间隙中填充密封树脂50而构成(如参见专利文献1)。图11是示出在专利文献1中的包含电子元件的基板的结构的横截面图(未审查公开号为2003-347722的日本专利)。
如图11所示，在专利文献1中的包含电子元件的基板100具有如下结构，即电子元件30安装在布线基板10和布线基板20之间，布线基板10、20通过焊球40电气互连，并且用密封树脂50密封所得的结构。
如图11所示，在相关技术中的包含电子元件的基板100的结构中，包含电子元件的基板100的总厚度是布线基板10和布线基板20的厚度与密封树脂50的厚度的总和。也就是布线基板10和布线基板20之间的间隙由用于对所得结构进行密封来在其中嵌入电子元件30的密封树脂50的厚度决定。因此，用于电气连接布线基板10和布线基板20的焊球40的直径尺寸会不可避免地扩大，以连接布线基板10和布线基板20。结果，存在着这样的问题，由于焊球40的排列间隔扩大，固定焊球40的端子区域增加并且因此包含电子元件的基板的平面尺寸(平面面积)增加。
此外，如图11所示，有时通过在厚度方向上堆叠多个包含电子元件的基板100、100、100、……的方式来使用包含电子元件的基板100的结构(如具有使用半导体元件作为电子元件30的POP(层叠封装)结构的半导体装置)。在这种模式中，为了减小包含电子元件的基板100的总厚度，装置的设计者不得不采用减小布线基板的厚度的方法或者减小电子元件的厚度的方法。结果，对使得结合了半导体元件的半导体装置的厚度变薄产生了限制，并且存在不能有效地减小包含电子元件的基板100的厚度这样的问题。
发明内容
本发明的示范实施例提供一种包含电子元件的基板，其可以相当多地减小平面尺寸(平面面积)和高度尺寸并且能够被紧凑地形成。
本发明提供一种包含电子元件的基板，其包含：
一对布线基板；
电子元件，其安装在一对布线基板之间；
焊球，其电气连接一对布线基板；和
密封树脂，其密封一对布线基板之间的间隙，
其中，面向安装有电子元件的一个布线基板的另一个布线基板在与电子元件相对的位置处具有一个开口部分，该开口部分比电子元件的平面形状更大。
电子元件也可以排列和安装来使得电子元件被容纳在另一个布线基板的开口部分中。
电子元件也可以安装来使得其上表面位于布线基板的厚度之内，所述电子元件的上表面与其面向布线基板的下表面相对。因此，由于下层侧上的布线基板和上层侧上的布线基板之间的距离能够被进一步地缩短，所以用来电气连接下层侧上的布线基板和上层侧上的布线基板的焊球的直径能够做得很小。因为焊球的直径能够减小，所以包含电子元件的基板的厚度和平面尺寸(平面面积)也能够减小。因为电子元件决不会从布线基板的表面突出，所以包含电子元件的基板的总厚度也能进一步减小。
也可以用密封树脂密封电子元件而露出上表面。因此，由于外露的上表面而可以改善电子元件的散热性能。
密封树脂也可以填充在开口部分中。优选地，包括上表面在内的处在开口部分中的电子元件应该由密封树脂来密封。
因此，电子元件无疑能够受到保护，并且能够提供具有高可靠性的包含电子元件的基板。
可以使用其中在由金属制成的型芯材料的外表面上涂敷焊料的包含型芯的焊球来用作焊球。型芯材料由铜形成。
当使用这样的包含型芯的焊球时，型芯材料作为下层侧上的布线基板和上层侧上的布线基板之间的限动件。因此，在下层侧上的布线基板和上层侧上的布线基板之间的间隙能够保持不变，并且包含电子元件的基板的尺寸精度能够提高。包含型芯的焊球还有效地改善了包含电子元件的基板的机械强度。
包含电子元件的基板还可以包含：
另一个电子元件或者电路元件，其安装在带有开口部分的另一个布线基板的外表面上来覆盖开口部分的开口区域的至少一部分。
因此，能够改善包含电子元件的基板(半导体装置)的封装密度。
根据本发明的包含电子元件的基板，安装在下层侧上的布线基板上的电子元件的高度(厚度)能够保持在上层侧上的布线基板的厚度之内。因此，下层侧上的布线基板和上层侧上的布线基板之间的间隙能够减小。因此，用来电气连接下层侧上的布线基板和上层侧上的布线基板的焊球的直径尺寸能够减小。换言之，焊球的排列间距可以变窄，用来电气连接下层侧上的布线基板和上层侧上的布线基板所需的焊球的数量能够在很小的空间中提供。因此，能够相当多地减小包含电子元件的基板的平面尺寸(平面面积)和高度。
从下面详细的说明、附图和权利要求中，其它特点和优势会十分明显。
附图说明
图1是示出在本发明的第一实施例中的包含电子元件的基板的横截面图。
图2是示出图1中的包含电子元件的基板中的开口部分及其邻近区域的平面图。
图3是示出第一实施例中使用的焊球的结构的剖面图。
图4是示出在制造包含电子元件的基板的步骤中的状态的示例视图。
图5是示出在制造包含电子元件的基板的步骤中的状态的示例视图。
图6是示出在制造包含电子元件的基板的步骤中的状态的示例视图。
图7是示出在制造包含电子元件的基板的步骤中的状态的示例视图。
图8是示出包含电子元件的基板的横截面图，其中在下层侧上的布线基板和上层侧上的布线基板之间的间隙、半导体元件的背面的整个表面和开口部分由密封树脂密封。
图9是示出在根据本发明的包含电子元件的基板的第二实施例中的结构的横截面图。
图10是示出在根据本发明的包含电子元件的基板的第三实施例中的结构的横截面图。
图11是示出相关技术中的包含电子元件的基板的示范视图。
具体实施方式
(第一实施例)
下面将参照附图说明本发明的包含电子元件的基板的实施例。图1是示出在本发明的第一实施例中的包含电子元件的基板的横截面图。图2是示出图1所示的包含电子元件的基板中的开口部分及其邻近区域的平面图。图3是示出第一实施例中使用的焊球的结构的剖面图。
在本发明的包含电子元件的基板100中，作为电子元件的半导体元件30安装在一对布线基板之间(布线基板10和布线基板20)，并且两个布线基板10和20通过焊球40电气连接。密封树脂50填充在布线基板10和布线基板20之间的间隙中。
布线图12由导体如铜等以公知方法分别形成在布线基板10的上表面和下表面上。布线基板10的表面由抗蚀剂13覆盖，布线图12上与连接端子连接的部分露出作为连接焊盘12A、12B。外部连接端子14连接到布线基板10的下表面上的连接焊盘12A上。连接到布线基板10的下表面上的外部连接端子14和形成在上表面上的布线图12通过通孔H电气连接。
作为电子元件的半导体元件30安装在布线基板10的上表面上。半导体元件30通过倒装芯片焊接由连接到焊条表面32上的凸块36(如焊料凸块、金凸块等)连接到布线基板10的连接焊盘12B上。底部填充树脂80注入到半导体元件30的下表面和布线基板10的上表面之间的间隙中，从而密封焊条表面32、凸块36和连接焊盘12B。
像布线基板10一样，在布线基板20的上表面和下表面上也分别按照公知方法形成由导体如铜等制成的布线图22。布线基板20的表面由抗蚀剂23覆盖，布线图22上与连接端子连接的部分露出作为连接焊盘22A。形成在布线基板20的两个表面上的布线图22通过通孔H电气互连。
图2是示出布线基板20中的开口部分及其邻近区域的平面图。如图2所示，为布线基板20提供在厚度方向上穿过布线基板20的开口部分24。提供开口部分24，使得当布线基板20堆叠在布线基板10上时，这个开口部分开口于安装在布线基板10上的半导体元件30的平面位置的相同位置处。开口部分24比半导体元件30的平面尺寸更大，这种方式使半导体元件30能够被容纳在开口部分24中。
布线基板10和布线基板20通过焊球40电气连接。在布线基板10的上表面上形成的并且连接有焊球40的连接焊盘12A和在布线基板20的下表面上形成的并且连接有焊球40的连接焊盘22A提供在相同的平面位置上。焊球40分别连接到连接焊盘12A和22A上。当布线基板20以这种方式安装到布线基板10上时，半导体元件30的背面的一部分被定位以进入布线基板20的开口部分24中。换言之，在半导体元件30的厚度的一部分置于布线基板20的厚度之内的情况中，布线基板20能够堆叠在布线基板10上。所述半导体元件的“背面”是指与形成焊条的表面相对的表面。
在本实施例中，如图3所示，通过把焊料44涂在铜芯42的外表面而形成的包含铜制型芯的焊球40被用作互连布线基板10和布线基板20的焊球40。铜芯42由金属材料铜形成并且制成实心球形。
由于使用其中包含铜芯42的焊球40，因此在布线基板10的连接焊盘12A和布线基板20的连接焊盘22A之间的间隙能够至少保持在等于铜芯42的直径尺寸的间隙的情况下，布线基板10和布线基板20电气连接。
密封树脂50填充在布线基板10和布线基板20之间的间隙中。因此，布线基板10和布线基板20之间的间隙、以及半导体元件30的背面由密封树脂50填充。
接下来，下文将参照附图4到图7说明第一实施例中的包含电子元件的基板100的制造方法。
首先，如图4所示，作为电子元件的半导体元件30安装在作为一个布线基板的布线基板10上。当凸块36与形成在布线基板10的上表面上的连接焊盘12B对准的同时，半导体元件30通过倒装芯片焊接安装在布线基板10上。在半导体元件30通过倒装芯片焊接安装在布线基板10上后，底部填充树脂80注入到半导体元件30和布线基板10的上表面之间的间隙中。
在底部填充树脂80注入后，如图5所示，其连接焊盘22A连接了焊球40的布线基板20与布线基板10对准并堆叠到布线基板10上。在布线基板20中形成的开口部分24与安装在布线基板10上的半导体元件30的平面位置对准。因此，当布线基板20堆叠到布线基板10上时，半导体元件30的背面的一部分进入到开口部分24中，如图5所示，这样半导体元件30的背面的高度位置被设置在布线基板20的厚度之内。在布线基板20以这种方式对准然后堆叠到布线基板10上后，布线基板20就通过回流焊步骤由焊球40连接到布线基板10上(图6)。
如图6所示，当焊球40经历回流焊步骤时，覆盖铜芯42外表面的焊料44熔化。这样，布线基板10的连接焊盘12A和布线基板20的连接焊盘22A能够通过焊料44和铜芯42电气互连，并且在布线基板10、20之间的间隙能够由作为限动件的铜芯42保持。
在焊球40的回流焊完成后，得到的结构由焊剂漂洗，然后密封树脂50填充在布线基板10和布线基板20之间的间隙中(图7)。
如图7所示，作为在布线基板10、20之间的间隙中填充密封树脂50的方法，例如其中一种方法是用树脂密封模子90、91来夹住布线基板10和布线基板20然后从浇口94向布线基板10和布线基板20之间的间隙中施压注入密封树脂50。被施压注入的密封树脂50受热凝固。
然后在密封树脂50受热凝固后，移开树脂密封模子90、91。然后，外部连接端子14连接到布线基板10的下表面上的连接焊盘12A上，由此包含电子元件的基板100完成。图8示出包含电子元件的基板，其中布线基板10和布线基板20之间的间隙、半导体元件的背面的整个表面以及开口部分由密封树脂密封。
在本制造方法的说明中，示出和说明了一种包含电子元件的基板100。但是在实际的制造方法中，多个包含电子元件的基板100、100、……、100通过使用大尺寸的布线基板10和大尺寸的布线基板20来同时由树脂密封，然后按照单个基板的外形对其进行切割来将其分成单独的块。
在根据本实施例的包含电子元件的基板100中，在半导体元件30的背面进入到布线基板20的开口部分24中的情况下，半导体元件30安装在布线基板10和布线基板20之间，于是半导体元件30的背面位置位于布线基板20的厚度之内。换言之，半导体元件30的高度(厚度)的一部分保持在布线基板20的厚度之内。能够通过使用这种结构来减小布线基板10和布线基板20之间的间隙。结果，焊球40的直径尺寸能够比包含电子元件的基板100减小得更多，焊球40的排列间距也能够变窄，并且焊球40的连接面积能够减小。从而能够相当大地减小包含电子元件的基板100的厚度和平面尺寸(平面面积)。
(第二实施例)
图9是示出根据本发明的包含电子元件的基板的第二实施例的结构的横截面图。本实施例示出包含电子元件的基板100，其中液态密封树脂50注入和密封在布线基板10和布线基板20之间。在图9中示出这样的情况，提供在布线基板10的上表面上的连接焊盘12A和提供在布线基板20的下表面上的连接焊盘22A通过焊球40电气互连，然后液态密封树脂50注入到布线基板10和布线基板20之间的间隙中，然后密封树脂50受热凝固。
当液态密封树脂50从侧端面部分注入到布线基板10和布线基板20之间时，液态密封树脂50通过毛细现象渗入布线基板10和布线基板20之间的间隙中，从而使密封树脂50充满布线基板10和布线基板20之间的间隙。被注入到布线基板10和布线基板20之间的间隙中的密封树脂50在开口部分24中被设置到布线基板20的下表面的高度位置，如图9所示。结果，半导体元件30的背面从密封树脂50中露出。
在本实施例中，包含电子元件的基板100的构成使得半导体元件30的背面在开口部分24中从密封树脂50中露出。因此，能够通过在半导体元件30的背面安装散热片来改善包含电子元件的基板100的散热特性。作为另一个示例，还可以在半导体元件30的背面上安装另一个半导体元件。
(第三实施例)
接下来，对本发明的第三实施例进行说明。图10是示出根据本发明的包含电子元件的基板的第三实施例的结构的横截面图。本实施例示出包含电子元件的基板(半导体装置)110，其中另一个电子元件(半导体元件)60安装在第一实施例中说明的包含电子元件的基板(半导体装置)100上。电子元件60通过外部连接端子62安装在布线基板20上以覆盖开口部分24。
布线基板10和布线基板20之间的间隙比相关技术中的更薄，并且电子元件(半导体元件)30包括其背面用密封树脂50密封。因此，电子元件(半导体元件)60的安装位置不必非得被设置成避开由倒装芯片焊接连接到布线基板10上的半导体元件的底部填充区，并且电子元件60能够在支座数量减小的情况下连接。结果，包含电子元件的基板110能够以紧凑的方式形成的更薄。
除了安装如图10所示的电子元件60，还可在布线基板20上安装电路元件如贴片电容器、贴片电阻器等。即使当电路元件等安装在布线基板20上时，电路元件等能够安装来覆盖开口部分24。
连同上述的内容，将根据实施例详细说明本发明的包含电子元件的基板(半导体装置)100。但是，本申请的本发明不只限于上述的实施例。不用说，在没有改变本发明的思想的范围内做出的各种改变和修改应该属于本申请的本发明的技术范围。
如在上述的实施例中，把半导体元件作为电子元件30的一个示例进行了说明。但是电子元件30不仅限于半导体元件，还可以采用其它电子元件。
上述的实施例中，采用了用铜芯42作为型芯材料的焊球40。但是可以使用其铜芯42由任意金属或除了铜的其它物质形成的焊球40，只要这样的导体具有足够高于焊料的熔点的软化温度。
而且，半导体元件30不仅可以通过倒装芯片焊接也可以通过丝焊安装在布线基板10上。
在上述的实施例中，说明了半导体元件30的背面(图10中的上表面)位置保持在布线基板20的厚度之内的这种模式。但是，即使在半导体元件30安装时采用了半导体元件30的背面从布线基板20的上表面中突出的模式，包含电子元件的基板100也能够比相关技术中的包含电子元件的基板薄得多，并且包含电子元件的基板100能够被小型化。

Claims (8)

1.一种包含电子元件的基板，其包含：
一对布线基板；
电子元件，其安装在所述一对布线基板之间；
焊球，其电气连接所述一对布线基板；和
密封树脂，其密封所述一对布线基板之间的间隙，
其中，面向安装有电子元件的一个布线基板的另一个布线基板在与电子元件相对的位置处具有一个开口部分，该开口部分比电子元件的平面形状更大。
2.如权利要求1所述的包含电子元件的基板，其中电子元件的排列和安装使得电子元件被容纳在所述另一个布线基板的开口部分中。
3.如权利要求2所述的包含电子元件的基板，其中电子元件的安装使得其上表面位于布线基板的厚度之内，所述电子元件的上表面与其面向布线基板的下表面相对。
4.如权利要求1到3中的任意一项所述的包含电子元件的基板，其中用密封树脂来密封电子元件而使其露出上表面。
5.如权利要求1到3中的任意一项所述的包含电子元件的基板，其中用密封树脂填充在开口部分中。
6.如权利要求1到3中的任意一项所述的包含电子元件的基板，其中焊球是在由金属制成的型芯材料的外表面上涂敷焊料而形成的包含型芯的焊球。
7.如权利要求6所述的包含电子元件的基板，其中型芯材料由铜形成。
8.如权利要求1到3中的任意一项所述的包含电子元件的基板，还包含：
另一个电子元件或者电路元件，其安装在带有开口部分的另一个布线基板的外表面上来覆盖所述开口部分的开口区域中的至少一部分。
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US9633937B2 (en) 2014-12-16 2017-04-25 Intel Corporation Electronic assembly that includes stacked electronic devices

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5279631B2 (ja) * 2009-06-23 2013-09-04 新光電気工業株式会社 電子部品内蔵配線基板と電子部品内蔵配線基板の製造方法
JP5445001B2 (ja) * 2009-09-29 2014-03-19 沖電気工業株式会社 半導体素子内蔵基板及び半導体素子内蔵基板の製造方法
TWI419283B (zh) * 2010-02-10 2013-12-11 Advanced Semiconductor Eng 封裝結構
JP5589462B2 (ja) * 2010-03-16 2014-09-17 カシオ計算機株式会社 半導体装置及び半導体装置の製造方法
US20120159118A1 (en) 2010-12-16 2012-06-21 Wong Shaw Fong Lower IC Package Structure for Coupling with an Upper IC Package to Form a Package-On-Package (PoP) Assembly and PoP Assembly Including Such a Lower IC Package Structure
CN202276549U (zh) * 2011-09-26 2012-06-13 番禺得意精密电子工业有限公司 电连接组件
US8969730B2 (en) * 2012-08-16 2015-03-03 Apple Inc. Printed circuit solder connections
JP5993248B2 (ja) * 2012-08-27 2016-09-14 新光電気工業株式会社 電子部品内蔵基板及びその製造方法
JP5935188B2 (ja) * 2012-12-28 2016-06-15 京セラ株式会社 配線基板およびその製造方法
US9484327B2 (en) * 2013-03-15 2016-11-01 Qualcomm Incorporated Package-on-package structure with reduced height
US9905491B1 (en) 2013-09-27 2018-02-27 STATS ChipPAC Pte. Ltd. Interposer substrate designs for semiconductor packages
US9859200B2 (en) * 2014-12-29 2018-01-02 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with interposer support structure mechanism and method of manufacture thereof
JP6570924B2 (ja) * 2015-08-31 2019-09-04 新光電気工業株式会社 電子部品装置及びその製造方法
US20180053753A1 (en) * 2016-08-16 2018-02-22 Freescale Semiconductor, Inc. Stackable molded packages and methods of manufacture thereof
WO2021033227A1 (ja) * 2019-08-19 2021-02-25 株式会社Ｆｕｊｉ 積層ユニットの接着方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09148496A (ja) * 1995-11-27 1997-06-06 Hitachi Ltd 半導体装置及びその製造方法
US6335565B1 (en) * 1996-12-04 2002-01-01 Hitachi, Ltd. Semiconductor device
JPH118474A (ja) * 1997-06-16 1999-01-12 Nec Corp 多層基板の製造方法
JP2001210954A (ja) * 2000-01-24 2001-08-03 Ibiden Co Ltd 多層基板
JP2002076265A (ja) * 2000-09-01 2002-03-15 Sony Corp 半導体デバイスの実装方法、半導体デバイス及び半導体装置
JP3644678B2 (ja) * 2001-01-30 2005-05-11 三菱電機株式会社 半導体装置及びその製造方法
US20020127771A1 (en) * 2001-03-12 2002-09-12 Salman Akram Multiple die package
JP2002343899A (ja) * 2001-05-17 2002-11-29 Sharp Corp 半導体パッケージ用基板、半導体パッケージ
JP2003347722A (ja) * 2002-05-23 2003-12-05 Ibiden Co Ltd 多層電子部品搭載用基板及びその製造方法
JP4287733B2 (ja) * 2003-11-04 2009-07-01 日本シイエムケイ株式会社 電子部品内蔵多層プリント配線板
US6982491B1 (en) * 2004-01-20 2006-01-03 Asat Ltd. Sensor semiconductor package and method of manufacturing the same
JP5068990B2 (ja) * 2006-12-26 2012-11-07 新光電気工業株式会社 電子部品内蔵基板

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9633937B2 (en) 2014-12-16 2017-04-25 Intel Corporation Electronic assembly that includes stacked electronic devices

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