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CN101145581B - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN101145581B
CN101145581B CN2007101537080A CN200710153708A CN101145581B CN 101145581 B CN101145581 B CN 101145581B CN 2007101537080 A CN2007101537080 A CN 2007101537080A CN 200710153708 A CN200710153708 A CN 200710153708A CN 101145581 B CN101145581 B CN 101145581B
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gate electrode
semiconductor device
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dielectric film
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CN101145581A (zh
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山本英雄
小林研也
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Renesas Electronics Corp
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    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract

本发明提供了一种具有掩埋在沟槽中的栅电极的改进的半导体器件，其使得难以在栅电极的末端处在栅电极和源电极之间产生短路。沟槽形成在半导体衬底中。栅电极和掩埋绝缘膜掩埋在沟槽中。通过掩埋绝缘膜将源电极设置在栅电极之上。在栅电极的末端处，层间绝缘膜以该层间绝缘膜跨越沟槽的末端的方式设置在掩埋绝缘膜和源电极之间。掩埋绝缘膜和层间绝缘膜两者均起着绝缘膜的作用并且防止在栅电极的末端处短路。

Description

半导体器件
本申请基于日本专利申请NO.2006-249813，通过引用将其内容结合在此。
技术领域
本发明涉及一种半导体器件。
背景技术
例如，日本特开专利申请公开No.2000-252468和日本特开专利申请公开No.2006-60184已经一种公开了具有槽栅结构的常规半导体器件。在上述半导体器件中，栅电极和覆盖栅电极的绝缘膜掩埋在沟槽中。
图9是示出日本特开专利申请公开No.2000-252468中描述的半导体器件的截面图。在半导体器件100中，N型漏区102，和P型阱区103顺序层叠在N+型半导体主体(body)101上。硅主体101和漏区102两者均操作作为MOSFET的漏极。阱区103的表面层的一部分是P+型重掺杂的体区104。半导体主体101、漏区102、阱区103以及重掺杂的体区104形成半导体衬底110。
沟槽111形成在半导体衬底110中。栅电极112和设置在其上的绝缘膜113掩埋在沟槽111中。绝缘膜114和绝缘膜115分别设置在栅电极112下和侧面上。N+型源区116形成在沟槽111和上述重掺杂的体区104之间。源区116与半导体主体101、漏区102、阱区103、绝缘膜115和栅电极112一起形成MOSFET。源区116连接到设置在半导体衬底110上的金属层117。
图10是示出在日本特开专利申请公开No.2006-60184中公开的半导体器件的截面图。图9示出垂直于沟槽纵向的截面。另一方面，图10示出与其平行的截面。在半导体器件200中，N-型外延层202形成在N型硅主体201上。P型阱区203形成在外延层202的表面的一部分中。硅主体201、外延层202和阱区203形成半导体衬底210。
也在上述半导体衬底210中形成沟槽211。栅电极212掩埋在沟槽211中。当栅电极212被容纳在沟槽211中时，栅电极212的末端基本上是在沟槽211的末端211a处。设置在栅电极212上的绝缘膜213、214和215也掩埋在沟槽211中。在栅极212的下面，还设置有绝缘膜216。
注意，在具有槽栅的半导体器件中，在沟槽末端附近的栅电极的结构可大致分为下列两种类型的结构。其中之一是如图11A所示的在沟槽311的末端311a处引出一部分栅电极312的结构。在图11A中，该部分的栅电极312在半导体衬底310中形成的元件隔离区309之上延伸，并且连接到栅极焊盘318。此外，绝缘膜313掩埋在沟槽311中。通过绝缘膜313和层间绝缘膜321电隔离栅电极312和源电极317。其中，在图11A中可去除元件隔离区309。
另一类型是如图11B中所示的在沟槽311的末端311a处不引出另一部分栅电极312的结构。然而，已经发现上述这些结构具有下列问题。也即，假设如图12A所示跨沟槽311的内部和外部，通过蚀刻以去除在沟槽311的外部的栅电极材料312a，来获得上述结构。
然而，在沟槽311的末端311a附近，对于水平上的差异，栅极材料312a比沟槽311的其他部分厚。因此，在沟槽311的末端311a附近，通过蚀刻栅极材料312a获得的栅电极312也保持得比沟槽311的其他部分厚。也即，在沟槽311的末端311a附近，在栅电极312上的绝缘膜313变得比其他部分更薄。因此，在栅电极312和源电极317之间容易产生短路。
发明内容
根据本发明，半导体器件包括：在半导体衬底中形成的沟槽；掩埋在沟槽中的栅电极；在上述栅电极之上设置的源电极；以及绝缘膜，其以该绝缘膜跨越沟槽的末端的方式设置在栅电极和源电极之间，并且该绝缘膜的一部分掩埋在沟槽中。
在上述半导体器件中，以绝缘膜跨越沟槽的末端的方式，将绝缘膜设置在栅电极和源电极之间。因此，即使当掩埋在沟槽中的一部分绝缘膜的厚度在沟槽的末端附近很薄时，也可确保在栅电极和源电极之间的相关绝缘膜的厚度足够。因此，可防止在栅电极和源电极之间产生短路。
根据本发明，可以实现具有难以在栅电极和源电极之间产生短路的结构的半导体器件。
附图说明
从下面结合附图的特定优选实施例的描述中，本发明的上述和其他目的、优势和特征将变得更明显，在附图中：
图1是示出根据本发明的半导体器件的一个实施例的平面图；
图2A是示出图1中以虚线L1包围的部分的平面图；
图2B是示出图2A中以虚线L3包围的部分的放大平面图；
图3是沿着图2A和图2B中的线III-III获得的截面图；
图4是示出图3的一部分的放大截面图；
图5是示出图1中以虚线L2包围的部分的平面图；
图6是沿着图5中的线VI-VI获得的截面图；
图7是用于解释实施例的变型的平面图；
图8A和图8B是用于解释实施例的变型的平面图；
图9是示出常规半导体器件的截面图；
图10是示出另一常规半导体器件的截面图；
图11A和图11B是用于解释本发明要解决的问题的截面图；以及
图12A和图12B是用于解释本发明要解决的问题的截面图。
具体实施方式
现在将参考说明性实施例在此描述本发明。本领域的技术人员将认识到，利用本发明的教导可完成很多替换实施例，并且本发明不限于出于解释目的而示出的说明性实施例。
在下文中，将参考附图详细解释根据本发明的半导体器件的优选实施例。其中，在解释附图时，在所有附图中用相同的附图标记示出相同的部件，并且不再重复相同的解释。
图1是示出根据本发明的半导体器件的一个实施例的平面图。半导体器件1包括：栅极焊盘10；栅极指(gate finger)20；以及源电极30。用于栅极焊盘10和源电极30的材料可包括例如铝。用于栅极指20的材料可包括例如多晶硅。并且，例如，栅极指20其上可以层叠有铝。
图2A是示出在半导体器件1中栅极焊盘10附近(图1中以虚线L1包围的部分)的平面图。如图2A所述，半导体器件1包括齐纳二极管40。齐纳二极管40连接在随后将描述的源电极30和栅极焊盘10之间。齐纳二极管40形成有N+型区域41、43、45和47以及P型区域42、44和46。用于区域41到47的材料可包括例如多晶硅。区域41的一部分作为源极触点32，而区域47的一部分作为栅极触点12。
图2B是示出图2A中以虚线L3包围的部分的放大平面图。如图2B所示，形成以类似条状布置的多个沟槽50。在本实施例中，沟槽50的末端50a彼此连接。因此，多个沟槽50和末端50a结合并形成单个沟槽。其中，每个沟槽50的末端50a定义为在纵向上相关沟槽50的末端。
图3是沿着图2A和图2B中的III-III线获得的截面图。从图3可以看出，沟槽50形成在半导体衬底60中。在本实施例中，半导体衬底60是硅衬底。栅电极52掩埋在沟槽50中。在图3中，栅电极没有在沟槽50的末端50a处引出。其理由是，栅电极52不应直接连接到作为源极触点的区域41。因此，通过栅极绝缘膜(未示出)将栅电极52容纳在沟槽50中，并且栅电极52的末端基本上是沟槽50的末端50a。这里，用于栅电极52的材料可包括多晶硅，或诸如钨之类的金属材料。
源电极30设置在栅电极52上方，且在源极触点33处连接到源区(未示出)和重掺杂的体区(未示出)，类似图9中所示。源电极30跨越沟槽50的末端50a。
绝缘膜70设置在栅电极52和源电极30之间，跨越沟槽50的末端50a。由于如上所述沟槽50的末端50a基本上是在栅电极52的末端，因此绝缘膜70不仅跨越沟槽50的末端50a，而且也跨越栅电极52的末端。
上述绝缘膜70的一部分掩埋在沟槽50中。具体的，绝缘膜70包括：位于沟槽50内的掩埋绝缘膜72(第一绝缘膜)；以及位于沟槽外的层间绝缘膜74(第二绝缘膜)。掩埋绝缘膜72对应于掩埋在沟槽50中的一部分绝缘膜70。而层间绝缘膜74对应于跨越沟槽50的末端50a的一部分。用于掩埋绝缘膜72的材料和层间绝缘膜74可包括，例如，非掺杂的硅酸盐玻璃(NSG)，或硼-磷硅酸盐玻璃(BPSG)。掩埋绝缘膜72的材料和层间绝缘膜74的材料可以相同或不同。
图4是示出图3的一部分的放大截面图。在沟槽50的末端50a处层间绝缘膜74的厚度T1优选等于或大于掩埋绝缘膜72的厚度的最大值T2。如通过利用12B所解释的，在沟槽50的末端50a附近的掩埋绝缘膜72的厚度比掩埋绝缘膜72的其他部分的厚度薄。因此，掩埋绝缘膜72的其他部分的厚度对应于上述最大值T2。例如，上述最大值T2大约为0.1到0.5微米。
回到图3，其全体形成齐纳二极管40的N+型区域41、43、45和47以及P型区域42、44和46，形成在半导体衬底60中所形成的元件隔离区62上。源电极30连接到区域41，而栅极焊盘10连接到区域47。这里，元件隔离区62具有例如硅的局部氧化(LOCOS)或浅沟槽隔离(STI)。
图5是示出半导体器件1的一部分(图1中虚线L2包围的部分)的平面图。图6是沿着图5中的VI-VI线获得的截面图。在图6中，栅电极52在沟槽50的末端50a处引出。栅电极52延伸到元件隔离区62上，并且通过栅极指20连接到栅极焊盘10。因此，栅电极52未被容纳在沟槽50中。在图5中，位于沟槽50外部的一部分栅电极52对应于栅极指20。并且，掩埋绝缘膜72也掩埋在沟槽50中。然而，不同于在图3所示的齐纳二极管40的附近形成的掩埋绝缘膜72，由于栅电极50如图11A所示地延伸在半导体衬底60上，掩埋绝缘膜72不能到达沟槽50的末端50a。通过掩埋绝缘膜72和层间绝缘膜74电隔离栅电极52和源电极30。
将解释本实施例的优点。在半导体器件1中，绝缘膜70以层间绝缘层74跨越沟槽50的末端50a的方式设置在栅电极52和源电极30之间(参考图3)。因此，即使当掩埋在沟槽50中的一部分绝缘膜70，其是掩埋绝缘膜72，在沟槽50的末端50a的附近较薄时，也可确保掩埋绝缘膜72和层间绝缘膜74两者结合的绝缘膜70的厚度足够。因此，可防止在栅电极52和源电极30之间产生短路。通过简单地改变用于形成触点的掩模图案可获得上述结构。
当在沟槽50的末端50a处的层间绝缘膜74的厚度T1(参考图4)等于或大于掩埋绝缘膜72的厚度的最大值T2时，可更有效地防止上述短路的产生。理由如下，当T1≥T2时，对于在沟槽50的末端50a处作为整体的绝缘膜70的厚度，可确保该厚度等于或大于最大值T2。
当以NSG形成掩埋绝缘膜72时，可防止在热处理时掺杂物从掩埋绝缘膜72中流出。对于其中利用NSG形成层间绝缘膜74的情况也是如此。
齐纳二极管40连接在栅电极52和源电极30之间。从而，可保护MOSFET免受浪涌电压。
栅电极52和覆盖栅电极52的绝缘膜(掩埋绝缘膜72)掩埋在沟槽50中。从而，对于图9所示的上述半导体器件，相比于其中在沟槽50上方形成绝缘膜且该绝缘膜跨越一部分源区的情况，可以使在形成于源电极30和源区之间的触点边缘与栅电极52的边缘之间的横向距离更小。
根据本发明的半导体器件并不限于上述实施例，而可能有多种修改。虽然上述实施例已经说明了类似条状布置的沟槽50，但也可类似如图7中所示的网格状布置沟槽50。同样在上述构造中，在纵向上沟槽50的特定部分(例如，沟槽50的阴影线部分)的末端对应于沟槽50的相关部分的末端50a。
此外，上述实施例已经示出了这样一个实例，其中多个沟槽50的末端50a彼此连接。因此，多个沟槽50和末端50a结合并且形成单个沟槽。尽管如此，但沟槽50的末端50a也可以不彼此连接。图8A和8B示出了这样的实例，其中分别对于类似多个条状沟槽和单个网格状沟槽布置沟槽50的情况，沟槽50的末端50a并不彼此连接。
此外，上述实施例已经解释了这样的结构，其中栅电极52并不引出，而是形成在其中设置齐纳二极管40的区域内的沟槽50的末端50a处。然而，上述结构也可形成在其余区域。即使在上述情况下，也很明显，通过设置跨越末端50a的绝缘膜70，可防止在栅和源之间产生短路。
此外，虽然上述实施例已经示出了在半导体器件1中设置栅极指20的一个实例，但是也可去除栅极指20。
很明显，本发明不限于上述实施例，且在不脱离本发明的范围和精神的条件下可进行修改和变化。

Claims (8)

1.一种半导体器件，包括：
沟槽，其形成在半导体衬底中；
栅电极，其掩埋在所述沟槽中；
源区，其形成在所述衬底中；
重掺杂体区，其形成在所述衬底中；
绝缘膜，其包括掩埋绝缘膜和层间绝缘膜，其中所述掩埋绝缘膜掩埋在所述沟槽中并且设置在所述栅电极上，所述层间绝缘膜位于所述沟槽之外，并且所述层间绝缘膜跨越所述沟槽的末端；以及，
源电极，其设置在所述栅电极之上，并且连接到所述源区、所述重掺杂体区以及所述掩埋绝缘膜，
其中，以使得所述绝缘膜跨越在所述沟槽旁边的所述半导体衬底的一部分的方式，使该绝缘膜设置在所述栅电极和所述源电极之间。
2.如权利要求1所述的半导体器件，包括形成在所述半导体衬底中的元件隔离区，
其中所述栅电极在所述沟槽的所述末端引出并延伸到所述元件隔离区上，并且位于所述沟槽之外的所述栅电极的一部分形成栅极指。
3.如权利要求1所述的半导体器件，
其中所述源电极跨越所述沟槽的所述末端。
4.如权利要求1所述的半导体器件，
其中在所述沟槽的所述末端附近的所述掩埋绝缘膜的厚度比所述掩埋绝缘膜的其它部分的厚度薄。
5.如权利要求4所述的半导体器件，
其中在所述沟槽的所述末端处的所述层间绝缘膜的厚度等于或大于所述掩埋绝缘膜的厚度的最大值。
6.如权利要求4所述的半导体器件，其中所述绝缘膜包括NSG和BPSG的至少一种。
7.如权利要求1所述的半导体器件，进一步包括连接在所述栅电极和所述源电极之间的齐纳二极管。
8.如权利要求6所述的半导体器件，其中所述绝缘膜包括NSG。
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