CN101118901B - Stack type chip packaging structure and manufacture process - Google Patents
Stack type chip packaging structure and manufacture process Download PDFInfo
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- CN101118901B CN101118901B CN2007101290251A CN200710129025A CN101118901B CN 101118901 B CN101118901 B CN 101118901B CN 2007101290251 A CN2007101290251 A CN 2007101290251A CN 200710129025 A CN200710129025 A CN 200710129025A CN 101118901 B CN101118901 B CN 101118901B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
The present invention discloses a stacked chip encapsulation structure, a chip encapsulation structure and the making process therein, which includes a first encapsulation structure unit and a secondencapsulation structure unit. Wherein, the first encapsulation structure unit has a loader, a chip, a first sealant, a wire distribution element, a conductive element; and a second sealant covers theloader surface, the chip, the first sealant, the wire distribution element and the conductive element and are exposed out of the top of the conductive element; moreover, the second encapsulation structure unit realizes electric connection with the wire distribution element through the conductive element. By using a wire distribution element connecting two encapsulation structure units, the presentinventionsaves the useable space of the loader and improves the integration degree; moreover, as the sealant covers the whole loading surface, the figure is not influenced by the size and configuration of the chip, therefore, the sealant mould of the making process of the invention can have various chip sizes and configurations.
Description
[technical field]
The invention relates to a kind of semiconductor component packaging structure (semiconductor device package) and processing procedure thereof, and particularly relevant for a kind of stack (stacked type) chip-packaging structure and processing procedure thereof.
[background technology]
In today of advanced information society, the market of multimedia application is expansion rapidly constantly, integrated circuit (integrated circuit, IC) encapsulation technology also need cooperate electronic installation digitlization, networking, zone connectionizations and use hommization trend and develop.In order to realize above-mentioned requirement, many-sided demands such as high speed processingization that must the strengthening electronic element, multifunction, integrated, miniaturization and and low priceization are so the integrated circuit encapsulation technology also and then develops to microminiaturization, densification.Except existing common spherical grid array type encapsulation (Ball Grid Array, BGA), chip scale packages (Chip-ScalePackage, CSP), Flip-Chip Using (Flip Chip package, F/C package) outside, the chip encapsulation technology of stack is more proposed recently, it is by piling up a plurality of chip packaging units, to improve whole packaging density.
Fig. 1 is the generalized section of existing a kind of stack type chip packaging structure.Please refer to shown in Figure 1, existing stack type chip packaging structure 100 comprises first encapsulation unit 110, second encapsulation unit 120 and a plurality of soldered ball (solder ball) 130, wherein soldered ball 130 is configured in the periphery of the chip 114 of first encapsulation unit 110, is used for connecting first encapsulation unit 110 and second encapsulation unit 120.Yet,, can occupy the usable area of circuit base plate 112, thereby cause the volume of stack type chip packaging structure 100 further to dwindle because soldered ball 130 is configured in chip 114 peripheries.In addition, chip 114 is received circuit base plate 112 by routing technical battery, and only forms sealing 118 on the regional area of circuit base plate 112, to cover chip 114 and lead 116.Like this, will be unfavorable for the design of dies with epoxy compound, that is to say that dies with epoxy compound must design corresponding to the size and the position of sealing 118, and can't be shared on the processing procedure of the encapsulation unit of different size design.
Fig. 2 is the generalized section of existing another kind of stack type chip packaging structure.Please refer to Fig. 2, stack type chip packaging structure 200 is similar with the stack type chip packaging structure 100 of Fig. 1, their difference be in: the sealing 212 of first encapsulation unit 210 of stack type chip packaging structure 200 is to be covered on the whole circuit base plate 216, and exposes a plurality of be configured on the circuit base plate 216 and around the soldered balls 214 of chip 218.Second encapsulation unit 220 is fixed on first encapsulation unit, 210 tops, and is electrically connected to first encapsulation unit 210 through soldered ball 230 and soldered ball 214.
The sealing 212 of Fig. 2 covers on the whole circuit base plate 216, and this design helps to improve the compatible rate of dies with epoxy compound.Yet, because soldered ball 214 and soldered ball 230 still are configured in the periphery of chip 218, occupied the usable area of circuit base plate 216 equally, limited the size of stack type chip packaging structure 200.
Fig. 3 is the generalized section of existing another stack type chip packaging structure.Please refer to Fig. 3, in stack type chip packaging structure 300, change configuration one circuit base plate 312b on first encapsulation unit 310 into, and make circuit base plate 312b be electrically connected to the circuit base plate 312a of first encapsulation unit 310 by lead 316.In addition, second encapsulation unit 320 is connected to circuit base plate 312b by a plurality of soldered balls 330, so that first encapsulation unit 310 and second encapsulation unit 320 electrically connect mutually by circuit base plate 312b.This kind design can solve the problem that the space that needs busy line substrate 312a disposes soldered ball, but owing to need to form the sealing 318 of given shape, with coated wire 316, and expose the surface of circuit base plate 312b, for soldered ball 330 configurations, therefore have the problem that sealing film tool can't be shared equally, and must design different sealing film tools corresponding to the external form of encapsulation unit.
[summary of the invention]
Main purpose of the present invention is to provide a kind of stack type chip packaging structure, in order to improve the shortcoming of aforementioned existing chip-packaging structure technology.
Another object of the present invention is to provide a kind of chip-packaging structure, can be applicable to above-mentioned stack type chip packaging structure, to solve the problem of existing chip-packaging structure technology.
Another purpose of the present invention is to provide a kind of processing procedure of chip-packaging structure, in order to make the said chip encapsulating structure.
For realizing above-mentioned or other purpose, the present invention adopts following technical scheme: a kind of chip-packaging structure comprises a carrier (carrier), a chip, one first sealing, a wire element (circuitdistribution device), a plurality of conducting element and one second sealing.Carrier has a loading end and opposing backside surface.Chip configuration and is electrically connected to carrier on loading end.First sealing is arranged on the loading end, and covers chip.Wire element is disposed in first sealing, and is electrically connected to carrier, and provides a plurality of connection pads (ball pad) in the first sealing surface.Conducting element is disposed at respectively on these connection pads.Second sealing covers loading end, and coating chip, first sealing, wire element and conducting element, and exposes the top of conducting element.
The present invention more proposes a kind of stack type chip packaging structure, mainly be with above-mentioned chip-packaging structure as an encapsulating structure unit, itself and another encapsulating structure unit is piled up mutually forms.Wherein, two encapsulating structure unit electrically connect mutually by above-mentioned conducting element and wire element.
In one embodiment of this invention, above-mentioned carrier or wire element for example are respectively a circuit base plate.
In one embodiment of this invention, the above-mentioned first encapsulating structure unit also can comprise a plurality of conductive projections, and chip is electrically connected to carrier with flip chip by these conductive projections.
In one embodiment of this invention, the above-mentioned first encapsulating structure unit also can comprise many first leads, and it is connected between chip and the carrier, and is coated by first sealing.
In one embodiment of this invention, the above-mentioned first encapsulating structure unit also can comprise many second leads, and it is connected between wire element and the carrier, and is coated by second sealing.
In one embodiment of this invention, above-mentioned conducting element for example is a plurality of first soldered balls.In addition, the connection pad on the wire element for example is to be array configurations, and accordingly, the second encapsulating structure unit can be a spherical grid array type encapsulating structure unit or other has the encapsulating structure element of array pin.
In one embodiment of this invention, the above-mentioned first encapsulating structure unit also can comprise a plurality of second soldered balls, is disposed at the back side of carrier.These second soldered balls are electrically connected to chip and wire element by carrier.
The present invention more proposes a kind of chip-packaging structure processing procedure, and it comprises the following steps.At first, provide a carrier, this carrier has a loading end and opposing backside surface.Then, dispose a chip on loading end, and make chip be electrically connected to carrier.Then, form one first sealing on loading end, make it cover chip.Afterwards, the first assembly of configuration one wiring is in first sealing, to provide a plurality of connection pads in the first sealing surface.Then, dispose a plurality of conducting elements on these connection pads.Then, electrically connect wire element to carrier.Afterwards, cover one second sealing in loading end, with by the second sealant covers chip, first sealing, wire element and these conducting elements, and second sealing exposes the top of conducting element.
In one of the present invention embodiment, for example be to come electrical connection-core sheet and carrier by flip-chip bond processing procedure or line connection process.
In one of the present invention embodiment, the step of above-mentioned configuration conducting element for example is that configuration one first soldered ball is on each connection pad.
In one of the present invention embodiment, above-mentioned chip-packaging structure processing procedure comprises that also a plurality of second soldered balls of configuration in the back side of carrier, make second soldered ball be electrically connected to chip and wire element by carrier.
In one of the present invention embodiment, above-mentioned chip-packaging structure processing procedure comprises that also configuration one second encapsulating structure unit is on the first encapsulating structure unit, make the second encapsulating structure unit be electrically connected to wire element, to form the stacked type chip-packaging structure by conducting element.
Based on above-mentioned, the present invention is disposed at chip top with wire element, to connect two encapsulating structure unit, therefore helps to save the free space on the carrier of encapsulating structure unit, thereby improves the integrated level of stack type chip packaging structure.In addition, because sealing covers the whole loading end of carrier, and its external form is not subjected to the size of chip and the influence of configuration, and therefore the employed dies with epoxy compound of chip-packaging structure processing procedure of the present invention is applicable to various chip size and configuration.
State with other purpose, feature and advantage and can become apparent on the present invention for allowing, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
[description of drawings]
Fig. 1 is the generalized section of existing a kind of stack type chip packaging structure.
Fig. 2 is the generalized section of existing another kind of stack type chip packaging structure.
Fig. 3 is the generalized section of existing another stack type chip packaging structure.
Fig. 4 is the generalized section of the chip-packaging structure of one embodiment of the invention.
Fig. 5 is the generalized section of the stack type chip packaging structure of one embodiment of the invention.
Fig. 6 A to Fig. 6 I illustrates the making flow process of above-mentioned chip-packaging structure.
[embodiment]
Fig. 4 is the generalized section of the chip-packaging structure of one embodiment of the invention.Please refer to Fig. 4, the chip-packaging structure 400 of present embodiment comprises a carrier 410, a chip 420, one first sealing 430, a wire element 440, a plurality of conducting element 450, one second sealing 460.Carrier 410 has a loading end 412 and opposing backside surface 414.Chip 420 is arranged on the loading end 412, and is electrically connected to carrier 410.First sealing 430 is arranged on the loading end 412, and covers chip 420.Wire element 440 is arranged in first sealing 430, and is electrically connected to carrier 410, and wire element 440 provides a plurality of connection pads 442 in first sealing, 430 surfaces.Conducting element 450 is arranged at respectively on the connection pad 442.Second sealing 460 covers loading end 412, and coating chip 420, first sealing 430, wire element 440 and conducting element 450, and exposes the top of conducting element 450.
In the present embodiment, wire element 440 and carrier 410 can be respectively a circuit base plate or a printed circuit board (PCB) (printed circuit board, PCB).Yet the present invention does not limit the kenel of wire element 440 and carrier 410.In other embodiments, wire element 440 also can be other encapsulating structure element that a plurality of connection pads 442 can be provided in first sealing, 430 surfaces, and carrier 410 also can be the encapsulating structure element that other is suitable for carries chips 420.In addition, in the present embodiment, conducting element 450 for example is a soldered ball.Yet in other embodiments of the invention, conducting element 450 also can be the conductor of conducting block or other type.
Hold above-mentioned, because the chip-packaging structure 400 of present embodiment utilizes the wire element 440 that is arranged on chip 420 tops to make with the extraneous conducting element 450 that electrically connects and concentrates on chip 420 tops, therefore help to save the usable area on the carrier 410, with the integrated level of raising chip-packaging structure 400, and can make carrier 410 have enough loaded areas to carry the chip 420 of large-size.In addition, because second sealing 460 of the chip-packaging structure 400 of present embodiment covers whole loading end 412, and its external form is not subjected to the size of chip 420 and the influence of configuration, therefore in order to the dies with epoxy compound that forms second sealing 460 applicable to various chip 420 sizes and configuration.That is to say that single dies with epoxy compound just can be in order to make the chip-packaging structure 400 of plurality of specifications, so just need not be and the dies with epoxy compound of customized multiple correspondence at plurality of specifications, thereby can make the manufacturing cost reduction of chip-packaging structure 400.
In the present embodiment, chip 420 is to electrically connect by many first leads 470 and carrier 410 in the routing mode, and wherein these first leads 470 are coated by first sealing 430.Yet in another embodiment of the present invention, chip 420 also can flip chip be electrically connected to carrier 410 by a plurality of conductive projections (not shown).In addition, in the present embodiment, wire element 440 can the routing mode be electrically connected to carrier 410 by many second leads 480, and wherein these second leads 480 are coated by second sealing 460.
In the present embodiment, connection pad 442 is the upper surface of array configurations in wire element 440.Yet in other embodiments of the invention, these connection pads 442 also can be other form and be disposed at first sealing, 430 surfaces.In addition, chip-packaging structure 400 can more comprise a plurality of soldered balls 490, is disposed at the back side 414 of carrier 410.Soldered ball 490 is electrically connected to chip 420 and wire element 440 by carrier 410, and chip-packaging structure 400 can see through these soldered balls 490 and other electronic component (as motherboard) electric connection.
The present invention more proposes a kind of stack type chip packaging structure, mainly be with above-mentioned chip-packaging structure as an encapsulating structure unit, itself and another encapsulating structure unit is piled up mutually forms.Fig. 5 is the generalized section of the stack type chip packaging structure of one embodiment of the invention.Please refer to Fig. 5, the stack type chip packaging structure 500 of present embodiment comprises one first encapsulating structure unit 510 and one second encapsulating structure unit 520.The first encapsulating structure unit 510 is above-mentioned chip-packaging structure 400.The second encapsulating structure unit 520 is disposed on the first encapsulating structure unit 510, and is electrically connected to wire element 440 by conducting element 450.Particularly, in the present embodiment, the second encapsulating structure unit 520 is a spherical grid array type encapsulating structure unit, its spherical pin (spherical lead) 522 and the conducting element 450 corresponding connections that are array configurations.In addition, owing to have quite enough areas on the wire element 440 with configuration conducting element 450, therefore applicable to the joint between the encapsulating structure unit of high integration.
Fig. 6 A to Fig. 6 I illustrates the making flow process of above-mentioned chip-packaging structure, mainly comprises the following steps.At first, please refer to shown in Fig. 6 A, above-mentioned carrier 410 is provided.Then, please refer to shown in Fig. 6 B, chip 420 is disposed on the loading end 412 of carrier 410, and make chip 420 be electrically connected to carrier 410.Present embodiment carries out a routing connection process, so that chip 420 is electrically connected to carrier 410 by many first leads 470.Certainly, other embodiments of the invention also can adopt flip-chip bond or alternate manner to make chip 420 be electrically connected to carrier 410.
Then, please refer to shown in Fig. 6 C, form first sealing 430 on the loading end 412 of carrier 410, make it cover chip 420.For instance, can form first sealing 430 by mould.In the present embodiment, formed first sealing 430 also coats first lead 470.
Afterwards, please refer to shown in Fig. 6 D, wire element 440 is disposed in first sealing 430, to provide a plurality of connection pads 442 in first sealing, 430 surfaces.Then, please refer to shown in Fig. 6 E, on connection pad 442, form conducting element 450.Particularly, present embodiment disposes a soldered ball on each connection pad 442.Yet other embodiments of the invention also can form the conductor of a conducting block or other type on each connection pad 442.
Then, please refer to shown in Fig. 6 F, electrically connect wire element 440 to carrier 410.In the present embodiment, for example be to carry out a routing connection process so that wire element 440 is electrically connected to carrier 410 by second lead 480.
Afterwards, please refer to shown in Fig. 6 G, second sealing 460 is covered on the loading end 412 of carrier 410, so that second sealing, 460 coating chips 420, first sealing 430, wire element 440 and conducting element 450, and make second sealing 460 expose the top of conducting element 450.For instance, present embodiment can form second sealing 460 by a dies with epoxy compound, wherein because second sealing 460 covers whole loading end 412, its external form is not subjected to the size of chip 420 and the influence of configuration, therefore dies with epoxy compound is applicable to various chip 420 sizes and configuration, and has higher process compatibility.In addition, in the present embodiment, formed second sealing 460 also can coat second lead 480.So far, finish the making of the chip-packaging structure 400 or the first encapsulating structure unit 510.
The chip-packaging structure processing procedure of present embodiment can further comprise the step shown in Fig. 6 H and Fig. 6 I, to form the chip-packaging structure of stacked type.Accept after the above-mentioned steps, please refer to shown in Fig. 6 H, the second encapsulating structure unit 520 is disposed on the first encapsulating structure unit 510, make the second encapsulating structure unit 520 be electrically connected to wire element 440 by these conducting elements 450.Then, please refer to shown in Fig. 6 I, present embodiment can also select to dispose the back side 414 of a plurality of soldered balls 490 in carrier 410, makes these soldered balls 490 be electrically connected to chip 420 and wire element 440 by carrier 410.So far, roughly finish the making of stack type chip packaging structure 500.
In sum, the present invention is disposed at the chip top with wire element, to connect two encapsulating structure unit, therefore help to save the free space on the carrier of encapsulating structure unit, and then the integrated level of raising stack type chip packaging structure, and can make carrier have enough loaded areas to carry the chip of large-size.Moreover, owing to have quite enough areas on the wire element, therefore help to improve the pin count of encapsulating structure unit to dispose a large amount of conducting elements.In addition, because the design that stack type chip packaging structure of the present invention adopts sealing to cover whole loader surface, so the external form of sealing is not subjected to the size of chip and the influence of configuration.That is to say that employed dies with epoxy compound designs applicable to various chip-packaging structure in the chip-packaging structure processing procedure of the present invention, has higher compatibility, and help to save production cost.
Claims (10)
1. stack type chip packaging structure, comprise: one first encapsulating structure unit and one second encapsulating structure unit, the described first encapsulating structure unit comprises a carrier, one chip and one first sealing, wherein carrier has a loading end and opposing backside surface, chip configuration is on this loading end and be electrically connected to this carrier, first sealing is disposed on this loading end and covers this chip, the described second encapsulating structure configuration of cells is on this first encapsulating structure unit, it is characterized in that: described stack type chip packaging structure also comprises a wire element, a plurality of conducting elements and one second sealing, this wire element is disposed in this first sealing, be electrically connected to this carrier and provide a plurality of connection pads in this first sealing surface, described a plurality of conducting element is disposed at respectively on those connection pads, described second sealing covers this loading end, and coat this chip, this first sealing, this wire element and those conducting elements, and this second sealing exposes the top of those conducting elements, the described second encapsulating structure unit has a plurality of spherical pins, and those spherical pins and those conducting elements by this first encapsulating structure unit are electrically connected to this wire element in this second sealing.
2. stack type chip packaging structure as claimed in claim 1 is characterized in that: at least one in this carrier and this wire element is a circuit base plate.
3. stack type chip packaging structure as claimed in claim 1 is characterized in that: this first encapsulating structure unit also comprises a plurality of conductive projections, and this chip is electrically connected to this carrier with flip chip by those conductive projections.
4. stack type chip packaging structure as claimed in claim 1, it is characterized in that: this first encapsulating structure unit also comprises many leads, at least a portion is connected between this chip and this carrier and/or between this wire element and this carrier in these leads, this first sealing of lead that is connected between this chip and this carrier coats, and the lead that is connected between this wire element and this carrier is coated by this second sealing.
5. stack type chip packaging structure as claimed in claim 1 is characterized in that: those conducting elements comprise a plurality of first soldered balls.
6. as claim 1,2,3,4 or 5 described stack type chip packaging structures, it is characterized in that: those connection pads are array configurations.
7. stack type chip packaging structure as claimed in claim 1 is characterized in that: this second encapsulating structure unit is a spherical grid array type encapsulating structure unit.
8. as claim 1 or 7 described stack type chip packaging structures, it is characterized in that: this first encapsulating structure unit also comprises a plurality of second soldered balls, those second soldered balls are disposed at the back side of this carrier, are electrically connected to this chip and this wire element by this carrier.
9. chip-packaging structure, comprise a carrier, one chip and one first sealing, wherein said carrier has a loading end and opposing backside surface, chip configuration is on this loading end and be electrically connected to this carrier, first sealing is disposed on this loading end and covers this chip, it is characterized in that: described chip-packaging structure also comprises: a wire element, a plurality of conducting elements and one second sealing, wherein wire element is disposed in this first sealing, this wire element is electrically connected to this carrier and provides a plurality of connection pads in this first sealing surface, a plurality of conducting elements are disposed at respectively on those connection pads, second sealing covers this loading end, and coat this chip, this first sealing, this wire element and those conducting elements, and this second sealing exposes the top of those conducting elements, electrically connects a plurality of spherical pin that another encapsulating structure unit of this chip-packaging structure top configuration is had with correspondence.
10. chip-packaging structure processing procedure comprises:
One carrier is provided, and this carrier has a loading end and opposing backside surface;
Dispose a chip on this loading end, and make this chip be electrically connected to this carrier;
Form one first sealing on this loading end, make it cover chip;
Dispose a wire element in this first sealing, to provide a plurality of connection pads in this first sealing surface;
Dispose a plurality of conducting elements on those connection pads;
Electrically connect this wire element to this carrier;
Cover one second sealing in this loading end, with by this this chip of second sealant covers, this first sealing, this wire element and those conducting elements, and this second sealing exposes the top of those conducting elements, to constitute one first encapsulating structure unit; And
Dispose one second encapsulating structure unit in this top, first encapsulating structure unit, this second encapsulating structure unit has a plurality of spherical pins, and those spherical pins and those conductive components by this first encapsulating structure unit are electrically connected to this cloth line component in this second sealing.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2007101290251A CN101118901B (en) | 2007-06-29 | 2007-06-29 | Stack type chip packaging structure and manufacture process |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2007101290251A CN101118901B (en) | 2007-06-29 | 2007-06-29 | Stack type chip packaging structure and manufacture process |
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| CN101118901A CN101118901A (en) | 2008-02-06 |
| CN101118901B true CN101118901B (en) | 2010-06-09 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9209163B2 (en) * | 2011-08-19 | 2015-12-08 | Marvell World Trade Ltd. | Package-on-package structures |
| CN102931108B (en) * | 2012-10-10 | 2014-04-30 | 矽力杰半导体技术(杭州)有限公司 | Encapsulating method for flip chip |
| CN103972202A (en) * | 2013-01-31 | 2014-08-06 | 联想(北京)有限公司 | Circuit device and PCB (printed circuit board) |
| CN108987288A (en) * | 2018-07-13 | 2018-12-11 | 江苏长电科技股份有限公司 | Monomer bimetallic plates encapsulating structure and its packaging method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW227553B (en) * | 1992-08-03 | 1994-08-01 | Chinese Health Inst | Method of making 2,3- dihydrogen-1,4,5,8- tetrahydroxy -9,10 anthryl diketone |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW227553B (en) * | 1992-08-03 | 1994-08-01 | Chinese Health Inst | Method of making 2,3- dihydrogen-1,4,5,8- tetrahydroxy -9,10 anthryl diketone |
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