CN100411287C - Lift type voltage converter and method for converting voltage - Google Patents

Abstract

The invention discloses a lifting voltage converter, wherein an input switching unit selectively couples a first end of an inductor to an input voltage and a ground potential. The output switching unit selectively couples the second end of the inductor to the output voltage and the ground potential. The first pulse generating circuit generates a first pulse signal having a first duty ratio. A first duty cycle is modulated in response to the output voltage. The second pulse generating circuit generates a second pulse signal having a second duty ratio. The second duty cycle is a fixed value greater than 0 and less than 1. When the first duty ratio is larger than a predetermined critical duty ratio, the mode control circuit makes one of the input switching unit and the output switching unit controlled by the first pulse signal and makes the other of the input switching unit and the output switching unit controlled by the second pulse signal.

Description

Up-down voltage converter and method for converting voltage

technical field

The present invention relates to a DC-to-DC voltage converter, in particular to an up-down voltage converter for converting an input voltage into an output voltage, wherein the input voltage can be greater than, equal to, or less than the output voltage.

Background technique

The DC-to-DC voltage converter can adjust an input voltage to a stable output voltage, and supply the current required by the external load under the stable output voltage. Various portable electronic systems, such as digital cameras, CD players, notebook computers, and mobile phones, etc., are equipped with suitable DC-to-DC voltage converters as their power sources. These portable electronic systems typically use a battery as an input voltage source, so the output voltage provided by the battery gradually decreases under long-term continuous use. In other words, at the initial stage of battery use, the output voltage provided by both ends of the battery is greater than the output voltage to be regulated, but after a period of continuous energy supply, the output voltage provided by the battery will be closer and closer to the regulated output voltage. into the output voltage. At this point, if the DC-to-DC converter can still effectively perform the voltage conversion function, the service life of the battery is extended.

It is foreseeable that under continuous operation, the output voltage provided by the battery will continue to decrease, and will eventually become lower than the desired regulated output voltage. Even in this case, the most complete utilization of the battery is made if the DC-DC converter can still effectively perform the voltage conversion function.

Therefore, people desire a buck-boost voltage converter that can efficiently convert the input voltage to the desired regulated output voltage regardless of whether the input voltage is greater than, equal to, or lower than the desired regulated output voltage .

Contents of the invention

An object of the present invention is to provide a buck-boost voltage converter capable of converting an input voltage into an output voltage, regardless of whether the input voltage is greater than, equal to, or less than the output voltage.

According to an aspect of the present invention, there is provided a buck-boost voltage converter, comprising: a switching circuit having an input switching unit for selectively coupling a first end of an inductor to an input voltage and a ground potential, and An output switching unit, used to selectively couple a second end of the inductor to an output voltage and the ground potential; a first pulse generating circuit, used to generate a first pulse signal, which has a first duty ratio , the first duty ratio is modulated in response to the output voltage; a second pulse generating circuit is used to generate a second pulse signal, which has a second duty ratio, and the second duty ratio is greater than a fixed value of 0 and less than 1; and a mode control circuit for controlling the switching circuit: when the first duty cycle is less than a predetermined critical duty cycle, operate in at least one simple mode, so that the input switching unit One of the output switching units is controlled by the first pulse signal, and the input switching unit and the other of the output switching units are maintained in a fixed coupling state, and when the first duty cycle is greater than a predetermined When the critical duty cycle is at least one boundary mode, one of the input switching unit and the output switching unit is controlled by the first pulse signal, and the other of the input switching unit and the output switching unit controlled by the second pulse signal.

The at least one simple mode has a simple buck mode and a simple boost mode. In the buck-only mode, the input switching unit is controlled by the first pulse signal, and the output switching unit maintains the second end of the fixed coupling inductor to the output voltage. In the simple boost mode, the output switching unit is controlled by the first pulse signal, and the input switching unit maintains the first end of the fixed coupling inductor to the input voltage.

The at least one border mode has a border buck mode and a border boost mode. In the junction buck mode, the input switching unit is controlled by the first pulse signal, and the output switching unit is controlled by the second pulse signal. In the boundary boost mode, the output switching unit is controlled by the first pulse signal, and the input switching unit is controlled by the second pulse signal.

According to another aspect of the present invention, a method for converting a voltage is provided, which is applied to a switching circuit, and the switching circuit has an input switching unit for selectively coupling a first end of an inductor to an input voltage and a ground potential, and an output switching unit for selectively coupling a second end of the inductor to an output voltage and the ground potential, the method comprising: generating a first pulse signal with a first duty cycle, the The first duty ratio is modulated in response to the output voltage; generating a second pulse signal with a second duty ratio, the second duty ratio is a fixed value greater than 0 and less than 1; monitoring the first duty ratio the first duty ratio of a pulse signal; and when the first duty ratio is greater than a predetermined critical duty ratio, one of the input switching unit and the output switching unit is controlled by the first pulse signal , and make the other of the input switching unit and the output switching unit controlled by the second pulse signal.

Description of drawings

Figure 1 shows a circuit diagram of a first example of a boost-boost voltage converter according to the present invention;

2 shows a schematic diagram of the operation method of the boost voltage converter according to the present invention;

FIG. 3(A) shows a timing diagram of the operation of the simple step-down mode according to the present invention;

FIG. 3(B) shows a timing diagram of operation of the junction buck mode according to the present invention;

FIG. 3(C) shows an operation timing diagram of the border boost mode according to the present invention;

FIG. 3(D) shows an operation timing diagram of the simple boost mode according to the present invention;

4 shows a circuit diagram of a duty ratio monitoring circuit according to the present invention;

Figure 5 shows a state diagram of the mode selection circuit according to the present invention;

FIG. 6 shows a detailed circuit diagram of the driving logic circuit according to the present invention;

FIG. 7(A) shows a circuit diagram of a second example of the boost voltage converter according to the present invention; and

FIG. 7(B) shows a circuit diagram of a third example of the buck-boost voltage converter according to the present invention.

Description of main component symbols

10 Synchronous switching circuit 11 Switching control circuit

20 modulation pulse generating circuit 21 voltage feedback circuit

22 difference amplifier circuit 23 transmission control circuit

24 comparison circuit 25 oscillation circuit

30 fixed pulse generating circuit 40 duty cycle monitoring circuit

41 simple/junction judgment unit 42 buck/boost judgment unit

50 mode selection circuit 60 drive logic circuit

61～66 logic gates 71, 72 asynchronous switching circuit

80 mode control circuit L inductance

Both ends of La, Lb inductance S1～S4 switching unit

DS duty cycle monitoring signal D1 first judgment signal

D2 second judgment signal MS mode selection signal

M1 first selection signal M2 second selection signal

P1～P4 driving signal MP modulation pulse signal

Duty cycle of D _MP modulated pulse signal

FP fixed pulse signal D Duty cycle of _FP fixed pulse signal

D _th , D _th(H) , D _th(L) critical duty cycle OSC oscillation signal

V _err1 , V _err2 error signal V _in input voltage

V _out output voltage V _fb voltage feedback signal

V _ref reference voltage X2, X3 diode

Detailed ways

The foregoing and other objects, features, and advantages of the present invention will be more apparent from the following description and accompanying drawings. Preferred embodiments according to the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 shows a circuit diagram of a first example of a buck-boost voltage converter according to the present invention. The buck-boost voltage converter is used to convert an input voltage V _in into an output voltage V _out , wherein the input voltage V _in can be greater than, equal to, or less than the output voltage V _out . Referring to FIG. 1 , the boost voltage converter of the first example includes a synchronous switching circuit 10 and a switching control circuit 11 .

The synchronous switching circuit 10 has an input switching unit and an output switching unit. Specifically, the input switching unit is composed of the first switching unit S1 and the second switching unit S2, and the output switching unit is composed of the third switching unit S3 and the fourth switching unit S4. The first switching unit S1 is disposed between the input voltage _Vin and the first end La of the inductor L. As shown in FIG. The second switching unit S2 is disposed between the first end La of the inductor L and the ground potential. The third switching unit S3 is disposed between the second end Lb of the inductor L and the output voltage V _out . The fourth switching unit S4 is disposed between the second end Lb of the inductor L and the ground potential. The switching units S1 to S4 are implemented by N-channel metal-oxide-semiconductor (NMOS), p-channel metal-oxide-semiconductor (PMOS), or other controllable switching elements. In the following description, it is assumed that the switching units S1 to S4 are all implemented by N-channel metal-oxide-semiconductor (NMOS).

The switching control circuit 11 has a modulation pulse generating circuit 20 , a fixed pulse generating circuit 30 , and a mode control circuit 80 . The mode control circuit has a duty ratio monitoring circuit 40 , a mode selection circuit 50 , and a driving logic circuit 60 . Based on the feedback of the output voltage V _out , the modulated pulse generating circuit 20 generates a modulated pulse signal MP having a duty ratio (Duty Ratio) D _MP modulated with the change of the output voltage V _out . The fixed pulse generating circuit 30 generates a fixed pulse signal FP whose duty ratio D _FP is a fixed value greater than 0 and less than 1. The duty ratio monitoring circuit 40 is used for detecting the duty ratio D _MP of the modulated pulse signal MP and generating a duty ratio monitoring signal DS. In response to the duty cycle monitoring signal DS, the mode selection circuit 50 generates a mode selection signal MS for controlling the driving logic circuit 60 . Once the operation mode is selected according to the mode selection signal MS, the driving logic circuit 60 generates four driving signals P1 to P4 based on the modulated pulse signal MP and the fixed pulse signal FP to respectively drive the four switches of the synchronous switching circuit 10 Units S1 to S4.

FIG. 2 shows a schematic diagram of the operation method of the buck-boost voltage converter according to the present invention. Referring to FIG. 2 , the buck-boost voltage converter according to the present invention selectively operates in a buck-only mode, a buck-junction mode, a boost-junction mode, and a boost-only mode. Both the simple buck mode and the crossover buck mode are applied when the input voltage V _in is greater than the output voltage V _out , and the crossover buck mode applies the input voltage V _in closer to the output voltage V _out . To be more precise, the buck-only mode is applied to the modulated pulse signal MP with a duty ratio D _MP between zero and a predetermined critical duty ratio D _th , while the buck-only mode is applied to the modulated pulse signal The duty ratio D _MP of MP is between the critical duty ratio D _th and 1. Both the simple boost mode and the crossover boost mode are applied when the input voltage V _in is lower than the output voltage V _out , and the input voltage V _in applied in the crossover boost mode is closer to the output voltage V _out . More precisely, the pure boost mode is applied to the duty cycle D _MP of the modulated pulse signal MP between zero and the critical duty cycle D _th , while the crossover boost mode is applied to the duty cycle of the modulated pulse signal MP The duty ratio D _MP is between the critical duty ratio D _th and 1.

In the simple step-down mode, as shown in FIG. 3(A), the first drive signal P1 is set to be the same as the modulated pulse signal MP, and the second drive signal P2 is set to be inverse phase to the first drive signal P1, the second The third driving signal P3 is set to be maintained at a high level H, and the fourth driving signal P4 is set to be inverse to the third driving signal P3 (that is, to be maintained at a low level L). In response to the first and second driving signals P1 and P2, the first and second switching units S1 and S2 perform ON/OFF operations synchronously with each other but in antiphase, so that the first end La of the inductor L is alternately coupled to the input voltage V _in and ground potential. However, the third switching unit S3 is maintained in the ON state and the fourth switching unit S4 is maintained in the OFF state, so that the second terminal Lb of the inductor L remains in a fixed state coupled to the output voltage V _out . Therefore, the buck-only mode according to the present invention is the same as the conventional buck-type voltage converter, and satisfies the relationship (V _out /V _in )=D _MP .

As the input voltage V _in decreases, the duty ratio D _MP of the modulated pulse signal MP must increase to maintain a constant output voltage V _out . When the duty cycle D _MP exceeds a predetermined critical duty cycle D _th , the operation of the buck-boost converter according to the present invention will change from the pure buck mode to the boundary buck mode.

In the boundary step-down mode, as shown in FIG. 3(B), the first drive signal P1 is set to be the same as the modulation pulse signal MP, and the second drive signal P2 is set to be inverse to the first drive signal P1 and the second drive signal. The third driving signal P3 is set to be inverse to the fixed pulse signal FP, and the fourth driving signal P4 is set to be inverse to the third driving signal P3. Therefore, the junction buck mode is different from the pure buck mode in that: for the junction buck mode, the third and fourth switching units S3 and S4 perform ON/OFF operations synchronously with each other but in antiphase, so that the inductor L The second end Lb of the second end Lb is alternately coupled to the output voltage V _out and the ground potential. Please note: the ON/OFF switching duty ratios of the third and fourth switching units S3 and S4 will not be modulated with the output voltage V _out because the duty ratio D _FP of the fixed pulse signal FP is fixed.

Once the input voltage _Vin continues to decrease and the duty ratio D _MP of the modulated pulse signal MP increases to the maximum value, that is, one, the operation of the boost voltage converter according to the present invention will change from the transitional step-down mode to the transitional step-up mode. pressure mode.

In the boundary boost mode, as shown in Figure 3(C), the first drive signal P1 is set to be inverse to the fixed pulse signal FP, the second drive signal P2 is set to be inverse to the first drive signal P1, and the third The driving signal P3 is set to be the same as the modulation pulse signal MP, and the fourth driving signal P4 is set to be inverse to the third driving signal P3. In response to the first and second driving signals P1 and P2, the first and second switching units S1 and S2 perform ON/OFF operations synchronously with each other but in antiphase, so that the first end La of the inductor L is alternately coupled to the input voltage V _in and ground potential. Please note: the ON/OFF switching duty ratios of the first and second switching units S1 and S2 will not be modulated with the output voltage V _out because the duty ratio D _FP of the fixed pulse signal FP is fixed. On the other hand, in response to the third and fourth driving signals P3 and P4, the third and fourth switching units S3 and S4 perform ON/OFF operations synchronously with each other but in antiphase, so that the second end Lb of the inductor L alternately Coupled to output voltage V _out and ground potential. Please note: the ON/OFF switching duty ratios of the third and fourth switching units S3 and S4 are modulated with the output voltage V _out .

As the input voltage V _in decreases, the duty ratio D _MP of the modulated pulse signal MP must decrease to maintain a constant output voltage V _out . When the duty cycle D _MP is lower than the critical duty cycle D _th , the operation of the buck-boost voltage converter according to the present invention is changed from the junction boost mode to the pure boost mode.

In the simple boost mode, as shown in FIG. 3(D), the first drive signal P1 is set to be maintained at a high level H, and the second drive signal P2 is set to be inverse to the first drive signal P1 (that is, to maintain At the low level L), the third driving signal P3 is set to be the same as the modulation pulse signal MP, and the fourth driving signal P4 is set to be inverse to the third driving signal P3. Therefore, the simple boost mode is different from the junction boost mode in that the first switching unit S1 is kept in the ON state and the second switching unit S2 is kept in the OFF state, so that the first end La of the inductor L is kept coupled to the input voltage Fixed state of _Vin . The boost-only mode according to the present invention is the same as the conventional boost voltage converter, and satisfies the relationship (V _ou /V _in )=1/(1-D _MP ).

In order to prevent the operation of the whole circuit system from being unstable due to a slight disturbance triggering the switching between the simplex mode and the borderline mode when the duty ratio D _MP is close to the critical duty ratio _Dth of the buck-boost voltage converter, the critical The duty ratio D _th has to be designed to have a hysteresis function (Hysteresis). Specifically, the critical duty ratio D _th has a higher value D _th(H) such as 0.95, and a lower value D _th(L) such as 0.85. The duty cycle D _MP of the modulated pulse signal MP must exceed a higher critical duty cycle D _th(H) to trigger the operation of the buck-boost voltage converter to change from the simple mode to the boundary mode. However, if it is desired to return from the borderline mode to the simple mode, the duty cycle D _MP of the modulated pulse signal MP must be reduced to be smaller than the lower critical duty cycle D _th(L) to trigger the mode transition.

Referring back to FIG. 1 , the specific structure and operation method of the modulated pulse generating circuit 20 will now be described in detail as follows. The modulation pulse generating circuit 20 has a voltage feedback circuit 21 , an error amplifier circuit 22 , a transmission control circuit 23 , a comparison circuit 24 , and an oscillation circuit 25 .

The voltage feedback circuit 21 is coupled to the output terminal of the synchronous switching circuit 10 for generating a voltage feedback signal V _fb representing the output voltage V _out . For example, the voltage feedback circuit 21 is implemented by a voltage divider formed by a plurality of series resistors.

The error amplifier circuit 22 has an inverting input terminal (-) and a non-inverting input terminal (+). The inverting input terminal is used for receiving the voltage feedback signal V _fb , and the non-inverting input terminal is used for receiving a predetermined reference voltage V _ref . Based on the comparison between the voltage feedback signal V _fb and the reference voltage V _ref , the error amplifier circuit 22 generates a first error signal V _err1 from the non-inverting output terminal (+) and a second error signal from the inverting output terminal (-) _Verr2 . The variation trends of the first error signal _Verr1 and the second error signal _Verr2 are opposite to each other. In other words, when the voltage feedback signal V _fb increases, the first error signal _Verr1 becomes smaller, but the second error signal _Verr2 becomes larger.

The transmission control circuit 23 is disposed between the error amplifier circuit 22 and the comparison circuit 24, and is used to selectively allow the first error signal _Verr1 or the second error signal _Verr2 to be applied to the comparison circuit according to the mode selection signal MS of the mode selection circuit 50. twenty four. In the buck-only mode and the buck-junction mode, the transmission control circuit 23 allows the first error signal _Verr1 to be applied to the comparison circuit 24 . In the pure boost mode and the boundary boost mode, the transmission control circuit 23 allows the second error signal _Verr2 to be applied to the comparison circuit 24 . The transmission control circuit 23 is composed of existing controllable transmission gates, so details will not be repeated here.

The comparison circuit 24 has a non-inverting input terminal (+) and an inverting input terminal (-). The non-inverting input terminal is used to receive the first or second error signal _Verr1 or _Verr2 , and the inverting input terminal is used to receive the oscillating signal OSC generated by the oscillating circuit 25 . Based on the comparison between the first or second error signal _Verr1 or _Verr2 and the oscillation signal OSC, the comparison circuit 24 generates a modulated pulse signal MP having a modulated duty cycle D _MP . As shown in FIGS. 3(A) and 3(B), in the simple step-down mode and the boundary step-down mode, the modulated pulse signal MP is determined by the first error signal _Verr1 and the oscillation signal OSC. Therefore, when the voltage feedback signal V _fb (representing the output voltage V _out ) increases, the first error signal _Verr1 decreases, so that the duty cycle D _MP of the modulation pulse signal MP decreases to reduce the output voltage V _out . As shown in FIGS. 3(C) and 3(D), in the border boost mode and the simple boost mode, the modulated pulse signal MP is determined by the second error signal _Verr2 and the oscillation signal OSC. Therefore, when the voltage feedback signal V _fb (representing the output voltage V _out ) increases, the second error signal _Verr1 increases, so that the duty ratio D _MP of the modulation pulse signal MP increases to reduce the output voltage V _out .

Referring to FIG. 4 , the duty cycle monitoring circuit 40 has a simple/junction judging unit 41 and a buck/boost judging unit 42 . The simple/intersection judging unit 41 is used for judging whether the duty ratio D _MP of the modulated pulse signal MP is smaller than the critical duty ratio D _th . When the duty cycle D _MP is smaller than the critical duty cycle D _th , the first judgment signal D1 is at a high level H. When the duty ratio D _MP is greater than the critical duty ratio D _th , the first judgment signal D1 is turned to a low level L. The buck/boost judging unit 42 is used to judge whether the duty cycle D _MP of the modulation pulse signal MP exceeds 1. When the duty cycle D _MP is less than 1, the second judgment signal D1 is at a low level L. When the duty cycle D _MP is greater than 1, the second judgment signal D1 is turned to a high level H. In one embodiment, the duty ratio monitoring signal DS of the duty ratio monitoring circuit 40 is composed of the first and second judgment signals D1 and D2.

Referring to FIG. 5, the mode selection circuit 50 is implemented by a finite state machine (Finite StateMachine). The mode selection signal MS is composed of the first selection signal M1 and the second selection signal M2. Both the first and second selection signals M1 and M2 are binary signals with a high level H and a low level L. As shown in FIG. Therefore, there are four possible combinations of the mode selection signal MS, which can be used to respectively select the four operation modes shown in FIG. 2 . Specifically, the state (M1, M2) = (L, L) is used to select the simple step-down mode, the state (M1, M2) = (L, H) is used to select the junctional step-down mode, and the state (M1, M2) =(H,L) is used to select the junction boost mode, and state (M1,M2)=(H,H) is used to select the buck-only mode. FIG. 5 also shows the related state transition conditions. The mode selection circuit 50 determines the operation mode to be selected in response to the first and second judgment signals D1 and D2.

Referring to FIG. 6 , based on the operation mode set by the first and second selection signals M1 and M2 , the driving logic circuit 60 uses the modulated pulse signal MP and the fixed pulse signal FP to generate first to fourth driving signals P1 to P4 . When the mode selection signal MS is in the state (M1, M2)=(L, L), the logic gate 62 blocks the fixed pulse signal FP from being applied to the logic gate 63 . As a result, the first and second driving signals P1 and P2 are generated by the modulated pulse signal MP through the logic gates 61 and 63 . On the other hand, the logic gate 64 blocks the modulation pulse signal MP from being applied to the logic gate 66 , and the logic gate 65 blocks the fixed pulse signal FP from being applied to the logic gate 66 . As a result, the third driving signal P3 is maintained at a high level H and the fourth driving signal P4 is maintained at a low level L. Thus, the state (M1, M2) = (L, L) effectively implements the buck-only mode shown in FIG. 3(A). When the mode selection signal MS transitions to the state (M1, M2)=(L, H), the third and fourth driving signals P3 and P4 are generated by the fixed pulse signal FP through the logic gates 65 and 66 . Thus, state (M1, M2) = (L, H) effectively implements the junction buck mode shown in FIG. 3(B).

When the mode selection signal MS is in the state (M1, M2)=(H, H), the logic gate 65 blocks the fixed pulse signal FP from being applied to the logic gate 66 . As a result, the third and fourth driving signals P3 and P4 are generated by the modulated pulse signal MP through the logic gates 64 and 66 . On the other hand, the logic gate 61 blocks the modulation pulse signal MP from being applied to the logic gate 63 , and the logic gate 62 blocks the fixed pulse signal FP from being applied to the logic gate 63 . As a result, the first driving signal P1 is maintained at a high level H and the second driving signal P2 is maintained at a low level L. Thus, the state (M1, M2) = (H, H) effectively implements the boost-only mode shown in FIG. 3(D). When the mode selection signal MS transitions to the state (M1, M2)=(H, L), the first and second driving signals P1 and P2 are generated by the fixed pulse signal FP through the logic gates 62 and 63 . Thus, state (M1, M2) = (L, H) effectively implements the boundary boost mode shown in FIG. 3(C).

FIG. 7(A) shows a circuit diagram of a second example of a boost voltage converter according to the present invention. The second example is different from the first example in that both the input switching unit and the output switching unit of the switching circuit 71 in the second example are asynchronous switching circuits. Specifically, the second switching unit S2 in the input switching unit is replaced by the diode X2, and the third switching unit S3 in the output switching unit is replaced by the diode X3. The switching control circuit 11 shown in FIG. 1 is also effectively applicable to the asynchronous switching circuit 71 of the second example. Since the diodes X2 and X3 are passive switching elements, the switching control circuit 11 only needs to provide the first and fourth driving signals P1 and P4 to control the first and fourth switching units S1 and S4 respectively.

FIG. 7(B) shows a circuit diagram of a third example of the buck-boost voltage converter according to the present invention. The third example is different from the second example in that only the input switching unit is changed to an asynchronous switching circuit in the switching circuit 72 of the third example. Specifically, the second switching unit S2 in the input switching unit is replaced by a diode X2. The switching control circuit 11 shown in FIG. 1 is also effectively applicable to the asynchronous switching circuit 72 of the third example. Since the diode X2 is a passive switching element, the switching control circuit 11 only needs to provide the first, third, and fourth driving signals P1, P3, and P4 respectively to control the first, third, and fourth switching units S1, S3, with S4. Please note that the switching control circuit 11 according to the present invention can also be effectively applied if only the third switching unit S3 of the output switching unit is changed to the diode X3 in the switching circuit.

While the present invention has been described by way of illustration of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and similar arrangements apparent to those skilled in the art. Accordingly, the scope of the claims should be accorded the broadest interpretation to embrace all such modifications and similar arrangements.

Claims (10)

1. A boost-boost voltage converter comprising: A switching circuit having an input switching unit for selectively coupling a first end of an inductor to an input voltage and a ground potential, and an output switching unit for selectively coupling a second end of the inductor to an output voltage and the ground potential; a first pulse generating circuit, used to generate a first pulse signal, which has a first duty cycle, and the first duty cycle is modulated in response to the output voltage; A second pulse generating circuit, used to generate a second pulse signal, which has a second duty ratio, and the second duty ratio is a fixed value greater than 0 and less than 1; and A mode control circuit for controlling the switching circuit: When the first duty cycle is less than a predetermined critical duty cycle, at least one simple mode is operated, so that one of the input switching unit and the output switching unit is controlled by the first pulse signal, and the input switching the cell is maintained in a fixed coupling state with the other of the output switching cells, and When the first duty cycle is greater than a predetermined critical duty cycle, at least one boundary mode is operated, so that one of the input switching unit and the output switching unit is controlled by the first pulse signal, and the input switching The other of the unit and the output switching unit is controlled by the second pulse signal. 2. The boost voltage converter as claimed in claim 1, wherein: The at least one simplex pattern has: a simple step-down mode, so that the input switching unit is controlled by the first pulse signal, and the output switching unit is maintained at a fixed coupling between the second end of the inductor and the output voltage, and In a simple boost mode, the output switching unit is controlled by the first pulse signal, and the input switching unit maintains a constant coupling between the first end of the inductor and the input voltage. 3. The boost voltage converter as claimed in claim 1, wherein: The at least one boundary pattern has: a junction buck mode, such that the input switching unit is controlled by the first pulse signal, and the output switching unit is controlled by the second pulse signal, and A boundary boost mode, such that the output switching unit is controlled by the first pulse signal, and the input switching unit is controlled by the second pulse signal. 4. The boost voltage converter of claim 1, wherein: The first pulse generating circuit has: a feedback circuit for generating a feedback signal representing the output voltage; an error amplification circuit, used to generate a first error signal and a second error signal according to the feedback signal and a predetermined reference voltage; a transmission control circuit for selectively allowing the first error signal and the second error signal to pass through; an oscillating circuit for generating an oscillating signal; and a comparison circuit for generating the first pulse signal, wherein when the transmission control circuit allows the first error signal to pass, the first pulse signal is generated by comparing the first error signal with the oscillation signal; When the transmission control circuit allows the second error signal to pass, the first pulse signal is generated by comparing the second error signal with the oscillation signal. 5. The boost voltage converter of claim 1, wherein: The mode control circuit has: a duty cycle monitoring circuit, used to monitor the first duty cycle of the first pulse signal; a mode selection circuit for generating a mode selection signal in response to the duty cycle monitoring circuit; and A driving logic circuit is used for controlling the first pulse signal and the second pulse signal to be applied to the switching circuit based on the mode selection signal. 6. The boost voltage converter as claimed in claim 5, wherein: The duty cycle monitoring circuit has: a first judging unit for generating a first judging signal indicating whether the first duty ratio exceeds a predetermined critical duty ratio, and A second judging unit is used to generate a second judging signal indicating whether the first duty cycle exceeds 1. 7. The boost voltage converter as claimed in claim 5, wherein: The mode selection circuit is implemented by a finite state machine, which changes state in response to the duty cycle monitoring circuit. 8. A method for converting a voltage, applied to a switching circuit, the switching circuit has an input switching unit for selectively coupling a first end of an inductor to an input voltage and a ground potential, and an output switching unit , for selectively coupling a second end of the inductor to an output voltage and the ground potential, the method comprising: generating a first pulse signal, which has a first duty cycle, and the first duty cycle is modulated in response to the output voltage; generating a second pulse signal, which has a second duty ratio, and the second duty ratio is a fixed value greater than 0 and less than 1; monitoring the first duty cycle of the first pulse signal; and When the first duty ratio is greater than a predetermined critical duty ratio, one of the input switching unit and the output switching unit is controlled by the first pulse signal, and the input switching unit and the output switching unit The other one is controlled by the second pulse signal. 9. The method for converting voltage as claimed in claim 8, further comprising: When the first duty ratio is less than the predetermined critical duty ratio, one of the input switching unit and the output switching unit is controlled by the first pulse signal, and the input switching unit and the output switching unit are maintained The other one is in a fixed coupled state. 10. The method of converting voltage as claimed in claim 8, wherein: In the step that the first duty cycle is less than the predetermined critical duty cycle, when the input switching unit is controlled by the first pulse signal, the output switching unit is maintained at the second fixedly coupled inductor. terminal to the output voltage, and when the output switching unit is controlled by the first pulse signal, the input switching unit maintains a fixed coupling between the first terminal of the inductor and the input voltage.

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