CN109687857B - Communication driving capability amplifying device - Google Patents
Communication driving capability amplifying device Download PDFInfo
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- CN109687857B CN109687857B CN201811521872.7A CN201811521872A CN109687857B CN 109687857 B CN109687857 B CN 109687857B CN 201811521872 A CN201811521872 A CN 201811521872A CN 109687857 B CN109687857 B CN 109687857B
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- triode
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/155—Ground-based stations
- H04B7/15528—Control of operation parameters of a relay station to exploit the physical medium
- H04B7/15535—Control of relay amplifier gain
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
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Abstract
The invention relates to a communication driving capability amplifying device, which comprises a communication signal generating source, a signal amplifying module and a plurality of receiving terminals; the method is characterized in that: the signal amplifying module comprises an AND Gate1, an AND Gate2 and a plurality of groups of triodes, the first input ends of the AND gates Gate1 and Gate2 are connected with an original signal source, and the second input ends of the AND gates Gate1 and Gate2 are enabling ends; each group of triodes comprises a first triode and a second triode, each group of triodes respectively inputs one path of original signals and outputs one path of output signals, the output end of the AND Gate1 is connected with the emitter of the first triode, and the output end of the AND Gate2 is connected with the emitter of the second triode; the base electrode of the first triode and the collector electrode of the second triode are connected with one path of original signal, and the collector electrode of the first triode and the base electrode of the second triode are connected with output signals. The invention can solve the problem that the terminal cannot receive the signal and cannot identify the signal in the process of insufficient driving capability of the communication signal in the prior art.
Description
Technical Field
The invention relates to a signal amplifying device, in particular to a communication driving capability amplifying device, and belongs to the technical field of wireless communication.
Background
In the prior art, various communication modes, such as UART, I2C, SPI, CAN, 485, etc., are used in the embedded field, but when there are multiple device terminals or the line is too long, the following problems occur:
(1) The driving capability of the communication signal from the singlechip is insufficient, so that some terminals can not receive the signal;
(2) If the signal line is too long, there is a phenomenon that the impedance is too large, and the terminal with the past level of the output is not recognized.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, provides a communication driving capability amplifying device, and solves the problem that a terminal cannot receive a signal in the process of being unable to identify the terminal due to the defect of the driving capability of a communication signal in the prior art.
According to the technical scheme provided by the invention, the communication driving capability amplifying device comprises a communication signal generating source, a signal amplifying module and a plurality of receiving terminals; the method is characterized in that: the signal amplifying module comprises an AND Gate1, an AND Gate2 and a plurality of groups of triodes, the first input ends of the AND gates Gate1 and Gate2 are connected with an original signal source, and the second input ends of the AND gates Gate1 and Gate2 are enabling ends; each group of triodes comprises a first triode and a second triode, each group of triodes respectively inputs one path of original signals and outputs one path of output signals, the output end of the AND Gate1 is connected with the emitter of the first triode, and the output end of the AND Gate2 is connected with the emitter of the second triode; the base electrode of the first triode and the collector electrode of the second triode are connected with one path of original signal, and the collector electrode of the first triode and the base electrode of the second triode are connected with output signals.
Further, the multiple groups of triodes are eight groups, eight original signals are respectively introduced, and eight output signals are output.
Further, the output end of the and Gate1 is connected with the emitters of the triode Q1, the triode Q2, the triode sum Q3, the triode Q4, the triode Q5, the triode Q6, the triode Q7 and the triode Q8, and the output end of the and Gate2 is connected with the emitters of the triode Q9, the triode Q10, the triode Q11, the triode Q12, the triode Q13, the triode Q14, the triode Q15 and the triode Q16; the base electrode of the triode Q1 and the collector electrode of the triode Q9 are connected with a first path of original signals, and the collector electrode of the triode Q1 and the base electrode of the triode Q9 are connected with a first path of output signals; the base electrode of the triode Q2 and the collector electrode of the triode Q10 are connected with a second path of original signals, and the collector electrode of the triode Q2 and the base electrode of the triode Q10 are connected with a second path of output signals; the base electrode of the triode Q3 and the collector electrode of the triode Q11 are connected with a third original signal, and the collector electrode of the triode Q3 and the base electrode of the triode Q11 are connected with a third output signal; the base electrode of the triode Q4 and the collector electrode of the triode Q12 are connected with a fourth path of original signals, and the collector electrode of the triode Q4 and the base electrode of the triode Q12 are connected with a fourth path of output signals; the base electrode of the triode Q5 and the collector electrode of the triode Q13 are connected with a fifth path of original signals, and the collector electrode of the triode Q5 and the base electrode of the triode Q13 are connected with a fifth path of output signals; the base electrode of the triode Q6 and the collector electrode of the triode Q14 are connected with a sixth path of original signals, and the collector electrode of the triode Q6 and the base electrode of the triode Q14 are connected with a sixth path of output signals; the base electrode of the triode Q7 and the collector electrode of the triode Q15 are connected with a seventh path of original signals, and the collector electrode of the triode Q7 and the base electrode of the triode Q15 are connected with a seventh path of output signals; the base electrode of the triode Q8 and the collector electrode of the triode Q16 are connected with an eighth path of original signals, and the collector electrode of the triode Q8 and the base electrode of the triode Q16 are connected with an eighth path of output signals.
According to the invention, after the signal sent by the signal source is subjected to level conversion through the triode, the driving capability is improved to the same capability as that of the power supply, and the problem that the terminal cannot receive the signal in the process of being unable to identify the terminal due to insufficient driving capability of the communication signal in the prior art is solved.
Drawings
Fig. 1 is a schematic block diagram of a communication driving capability amplifying device according to the present invention.
Fig. 2 is a logic frame force of the signal amplifying module.
Detailed Description
The invention will be further described with reference to the accompanying drawings.
As shown in fig. 1, the communication driving capability amplifying device of the present invention includes a communication signal generating source, a signal amplifying module and a plurality of receiving terminals; in this embodiment, the signal source generated by the communication signal generating source is amplified by the signal amplifying module, so that the situation that the terminal cannot receive the signal due to insufficient driving capability of the communication signal or the terminal cannot be identified due to overlong signal line can be avoided, and the stability of the received signal of the terminal is ensured.
As shown in fig. 2, the signal amplifying module includes and gates Gate1 and Gate2, first input ends of the and gates Gate1 and Gate2 are connected with an original signal source, second input ends of the and gates Gate1 and Gate2 are enable ends, and the ends play a role of a switch; the output end of the AND Gate1 is connected with the emitters of a triode Q1, a triode Q2, a triode Q3, a triode Q4, a triode Q5, a triode Q6, a triode Q7 and a triode Q8, and the output end of the AND Gate2 is connected with the emitters of a triode Q9, a triode Q10, a triode Q11, a triode Q12, a triode Q13, a triode Q14, a triode Q15 and a triode Q16; the base electrode of the triode Q1 and the collector electrode of the triode Q9 are connected with a first path of original signals, and the collector electrode of the triode Q1 and the base electrode of the triode Q9 are connected with a first path of output signals; the base electrode of the triode Q2 and the collector electrode of the triode Q10 are connected with a second path of original signals, and the collector electrode of the triode Q2 and the base electrode of the triode Q10 are connected with a second path of output signals; the base electrode of the triode Q3 and the collector electrode of the triode Q11 are connected with a third original signal, and the collector electrode of the triode Q3 and the base electrode of the triode Q11 are connected with a third output signal; the base electrode of the triode Q4 and the collector electrode of the triode Q12 are connected with a fourth path of original signals, and the collector electrode of the triode Q4 and the base electrode of the triode Q12 are connected with a fourth path of output signals; the base electrode of the triode Q5 and the collector electrode of the triode Q13 are connected with a fifth path of original signals, and the collector electrode of the triode Q5 and the base electrode of the triode Q13 are connected with a fifth path of output signals; the base electrode of the triode Q6 and the collector electrode of the triode Q14 are connected with a sixth path of original signals, and the collector electrode of the triode Q6 and the base electrode of the triode Q14 are connected with a sixth path of output signals; the base electrode of the triode Q7 and the collector electrode of the triode Q15 are connected with a seventh path of original signals, and the collector electrode of the triode Q7 and the base electrode of the triode Q15 are connected with a seventh path of output signals; the base electrode of the triode Q8 and the collector electrode of the triode Q16 are connected with an eighth path of original signals, and the collector electrode of the triode Q8 and the base electrode of the triode Q16 are connected with an eighth path of output signals.
The invention relates to a working principle of a communication driving capability amplifying device, which comprises the following steps: the communication signal generating source generates a signal source, and the signal is transmitted to a plurality of equipment terminals after being transmitted through the signal amplifying module. The signal from the signal source is generally weak in driving capability, and after level conversion by the triode, the driving capability is improved to be the same as that of the power supply.
Claims (1)
1. A communication driving capability amplifying device comprises a communication signal generating source, a signal amplifying module and a plurality of receiving terminals; the method is characterized in that: the signal amplifying module comprises an AND Gate I (Gate 1), an AND Gate II (Gate 2) and a plurality of groups of triodes, wherein first input ends of the AND Gate I (Gate 1) and the AND Gate II (Gate 2) are connected with an original signal source, and second input ends of the AND Gate I (Gate 1) and the AND Gate II (Gate 2) are enabled ends; each group of triodes comprises a first triode and a second triode, each group of triodes respectively inputs one path of original signals and outputs one path of output signals, the output end of the AND Gate one (Gate 1) is connected with the emitter of the first triode, and the output end of the AND Gate two (Gate 2) is connected with the emitter of the second triode; the base electrode of the first triode and the collector electrode of the second triode are connected with one path of original signal, and the collector electrode of the first triode and the base electrode of the second triode are connected with output signals;
the multiple groups of triodes are eight groups, eight original signals are respectively introduced, and eight output signals are output;
the output end of the AND Gate I (Gate 1) is connected with the emitters of a first triode (Q1), a second triode (Q2), a third triode (Q3), a fourth triode (Q4), a fifth triode (Q5), a sixth triode (Q6), a seventh triode (Q7) and an eighth triode (Q8), and the output end of the AND Gate II (Gate 2) is connected with the emitters of a ninth triode (Q9), a tenth triode (Q10), an eleventh triode (Q11), a twelfth triode (Q12), a thirteenth triode (Q13), a fourteen triode (Q14), a fifteen triode (Q15) and a sixteen triode (Q16); the base electrode of the triode I (Q1) and the collector electrode of the triode II (Q9) are connected with a first path of original signals, and the collector electrode of the triode I (Q1) and the base electrode of the triode II (Q9) are connected with a first path of output signals; the base electrode of the triode II (Q2) and the collector electrode of the triode II (Q10) are connected with a second path of original signals, and the collector electrode of the triode II (Q2) and the base electrode of the triode II (Q10) are connected with a second path of output signals; the base electrode of the triode III (Q3) and the collector electrode of the triode eleven (Q11) are connected with a third path of original signals, and the collector electrode of the triode III (Q3) and the base electrode of the triode eleven (Q11) are connected with a third path of output signals; the base electrode of the triode IV (Q4) and the collector electrode of the triode twelve (Q12) are connected with a fourth path of original signals, and the collector electrode of the triode IV (Q4) and the base electrode of the triode twelve (Q12) are connected with a fourth path of output signals; the base electrode of the triode five (Q5) and the collector electrode of the triode thirteenth (Q13) are connected with a fifth path of original signals, and the collector electrode of the triode five (Q5) and the base electrode of the triode thirteenth (Q13) are connected with a fifth path of output signals; the base electrode of the triode six (Q6) and the collector electrode of the triode fourteen (Q14) are connected with a sixth path of original signals, and the collector electrode of the triode six (Q6) and the base electrode of the triode fourteen (Q14) are connected with a sixth path of output signals; the base electrode of the triode seven (Q7) and the collector electrode of the triode fifteen (Q15) are connected with a seventh path of original signals, and the collector electrode of the triode seven (Q7) and the base electrode of the triode fifteen (Q15) are connected with a seventh path of output signals; the base electrode of the triode eight (Q8) and the collector electrode of the triode sixteen (Q16) are connected with an eighth path of original signals, and the collector electrode of the triode eight (Q8) and the base electrode of the triode sixteen (Q16) are connected with an eighth path of output signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811521872.7A CN109687857B (en) | 2018-12-13 | 2018-12-13 | Communication driving capability amplifying device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811521872.7A CN109687857B (en) | 2018-12-13 | 2018-12-13 | Communication driving capability amplifying device |
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| Publication Number | Publication Date |
|---|---|
| CN109687857A CN109687857A (en) | 2019-04-26 |
| CN109687857B true CN109687857B (en) | 2023-05-23 |
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| CN201811521872.7A Active CN109687857B (en) | 2018-12-13 | 2018-12-13 | Communication driving capability amplifying device |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4686396A (en) * | 1985-08-26 | 1987-08-11 | Xerox Corporation | Minimum delay high speed bus driver |
| US5422848A (en) * | 1992-07-06 | 1995-06-06 | Motorola Inc. | ECL-to-CMOS buffer having a single-sided delay |
| JPH09200015A (en) * | 1996-01-16 | 1997-07-31 | Fujitsu Ltd | Semiconductor switch control circuit |
| DE19900802C1 (en) * | 1999-01-12 | 2000-03-23 | Siemens Ag | Integrated ferroelectric memory |
-
2018
- 2018-12-13 CN CN201811521872.7A patent/CN109687857B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4686396A (en) * | 1985-08-26 | 1987-08-11 | Xerox Corporation | Minimum delay high speed bus driver |
| US5422848A (en) * | 1992-07-06 | 1995-06-06 | Motorola Inc. | ECL-to-CMOS buffer having a single-sided delay |
| JPH09200015A (en) * | 1996-01-16 | 1997-07-31 | Fujitsu Ltd | Semiconductor switch control circuit |
| DE19900802C1 (en) * | 1999-01-12 | 2000-03-23 | Siemens Ag | Integrated ferroelectric memory |
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| CN109687857A (en) | 2019-04-26 |
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Address after: 214000 Liyuan Development Zone, Binhu District, Wuxi City, Jiangsu Province, 04-6 Block (100 Dicui Road), 9 buildings and 2 floors Applicant after: ZHONGKEXIN INTEGRATED CIRCUIT Co.,Ltd. Address before: 214000 Liyuan Development Zone, Binhu District, Wuxi City, Jiangsu Province, 04-6 Block (100 Dicui Road), 9 buildings and 2 floors Applicant before: CHINA KEY SYSTEM & INTEGRATED CIRCUIT Co.,Ltd. |
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