CN109585294A - FINFET device, semiconductor devices and forming method thereof - Google Patents
FINFET device, semiconductor devices and forming method thereof Download PDFInfo
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- CN109585294A CN109585294A CN201810917121.0A CN201810917121A CN109585294A CN 109585294 A CN109585294 A CN 109585294A CN 201810917121 A CN201810917121 A CN 201810917121A CN 109585294 A CN109585294 A CN 109585294A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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Abstract
Provide FinFET and forming method thereof.Method includes being formed in the fin extended above area of isolation.It is formed above fin and sacrifices grid.First dielectric material is selectively deposited on the side wall for sacrificing grid to form spacer on the side wall for sacrificing grid.Use and sacrifices grid and spacer as combination mask to pattern fin to form groove in fin.Epitaxial source/drain is formed in a groove.The embodiments of the present invention also provide the forming methods of semiconductor devices.
Description
Technical field
The embodiment of the present invention is generally related to technical field of semiconductors, more particularly, to FINFET device, semiconductor
Device and forming method thereof.
Background technique
Semiconductor devices in various electronic applications, for example, such as personal computer, mobile phone, digital camera and other
Electronic equipment.Usually by following steps come manufacturing semiconductor devices: on a semiconductor substrate side be sequentially deposited insulating layer or
Dielectric layer, conductive layer and semiconductor material layer, and a variety of materials layer is patterned to form circuit unit using photoetching
With the element being located on circuit unit.
Semi-conductor industry continue through lasting reduction minimum feature size improve various electronic building bricks (for example, transistor,
Diode, resistor, capacitor etc.) integration density, this allows for more components to be integrated into given area.But with
There are the other problems that solve in the reduction of minimum feature size.
Summary of the invention
According to an aspect of the present invention, a kind of method for being used to form semiconductor devices is provided, comprising: be formed in isolation
The fin that overlying regions extend；It is formed above the fin and sacrifices grid；It is optionally deposited on the side wall for sacrificing grid
First dielectric material, to form spacer on the side wall for sacrificing grid, wherein first dielectric material is not deposited on
The top face for sacrificing grid；It is described to pattern as combination mask to use the sacrifice grid and the spacer
Fin, to form groove in the fin；And epitaxial source/drain is formed in the groove.
According to another aspect of the present invention, a kind of method for being used to form semiconductor devices is provided, comprising: so that isolation
Area depression is to expose the side wall of semiconductor fin；Gate electrode layer is formed above the semiconductor fin；On the gate electrode layer
It is rectangular at pattern mask；The part for removing the gate electrode layer exposed by the pattern mask, in the semiconductor
It is formed above fin and sacrifices grid；Flaorination process is implemented to form fluorination pattern mask to the pattern mask；Described sacrificial
The first dielectric material is optionally deposited on the side wall of domestic animal grid, to form spacer on the side wall for sacrificing grid；Make
The fluorination pattern mask, the sacrifice grid and the spacer is used to etch the semiconductor fin as combination mask,
To form groove in the semiconductor fin；And the deposited semiconductor material in the groove.
According to another aspect of the invention, a kind of method for being used to form semiconductor devices is provided, comprising: etching isolation
Region is to expose the side wall of semiconductor fin；The first oxide material is formed on the side wall of the semiconductor fin and top surface；Institute
It states and forms conductive material above the first oxide material；The second oxide material is formed above the conductive material；Etching institute
The second oxide material is stated to form the second oxide material of patterning；Use the second oxide material of the patterning as covering
Mould etches the conductive material, sacrifices grid to be formed above the semiconductor fin；In the second oxide of the patterning
The first dielectric material is formed on the side wall of material and top surface and above the expose portion of first oxide material；To institute
The expose portion for stating the second oxide material of patterning and first oxide material implements flaorination process, the flaorination process
Form fluorination the second oxide material of patterning；Remove first dielectric material；It is selected on the side wall for sacrificing grid
Deposit the second dielectric material to property；The second oxide material, the sacrifice grid and described second are patterned using the fluorination
Dielectric material etches the semiconductor fin as combination mask, to form groove in the semiconductor fin；And described
Epitaxial growth of semiconductor material in groove.
Detailed description of the invention
When reading in conjunction with the accompanying drawings, various aspects of the invention are best understood from described in detail below.It should
Note that according to the standard practices in industry, all parts are not drawn on scale.In fact, in order to clearly discuss, various parts
Size can be arbitrarily increased or decreased.
Fig. 1 is the perspective view of fin formula field effect transistor in accordance with some embodiments (" FinFET ") device.
Fig. 2A to Fig. 5 A is the sectional view in the intermediate stage of manufacture FinFET in accordance with some embodiments.
Fig. 6 A and Fig. 6 B are the sectional views in the intermediate stage of manufacture FinFET in accordance with some embodiments.
Fig. 7 A, Fig. 7 B and Fig. 7 C are the sectional views in the intermediate stage of manufacture FinFET in accordance with some embodiments.
Fig. 8 A, Fig. 8 B and Fig. 8 C are the sectional views in the intermediate stage of manufacture FinFET in accordance with some embodiments.
Fig. 9 A, Fig. 9 B and Fig. 9 C are the sectional views in the intermediate stage of manufacture FinFET in accordance with some embodiments.
Figure 10 A, Figure 10 B and Figure 10 C are the sectional views in the intermediate stage of manufacture FinFET in accordance with some embodiments.
Figure 11 A, Figure 11 B and Figure 11 C are the sectional views in the intermediate stage of manufacture FinFET in accordance with some embodiments.
Figure 12 A, Figure 12 B and Figure 12 C are the sectional views in the intermediate stage of manufacture FinFET in accordance with some embodiments.
Figure 13 A, Figure 13 B and Figure 13 C are the sectional views in the intermediate stage of manufacture FinFET in accordance with some embodiments.
Figure 14 A, Figure 14 B and Figure 14 C are the sectional views in the intermediate stage of manufacture FinFET in accordance with some embodiments.
Figure 15 A, Figure 15 B and Figure 15 C are the sectional views in the intermediate stage of manufacture FinFET in accordance with some embodiments.
Figure 16 A, Figure 16 B and Figure 16 C are the sectional views in the intermediate stage of manufacture FinFET in accordance with some embodiments.
Figure 17 A, Figure 17 B and Figure 17 C are the sectional views of FinFET in accordance with some embodiments.
Figure 18 A, Figure 18 B and Figure 18 C are the sectional views of FinFET in accordance with some embodiments.
Figure 19 A, Figure 19 B and Figure 19 C are the sectional views of FinFET in accordance with some embodiments.
Figure 20 A, Figure 20 B and Figure 20 C are the sectional views of FinFET in accordance with some embodiments.
Figure 21 A, Figure 21 B and Figure 21 C are the sectional views of FinFET in accordance with some embodiments.
Figure 22 A, Figure 22 B and Figure 22 C are the sectional views of FinFET in accordance with some embodiments.
Figure 23 is the flow chart for showing the method in accordance with some embodiments for forming FinFET.
Specific embodiment
Following disclosure provides for realizing many different embodiments or examples of different characteristic of the invention.Below
The particular instance of component and arrangement is described to simplify the present invention.Certainly, these are only example, are not intended to limit this hair
It is bright.For example, in the following description, above second component or the upper formation first component may include in a manner of directly contacting
The embodiment of the first component and second component is formed, and also may include that can be formed between the first component and second component
Additional component, so that the embodiment that the first component and second component can be not directly contacted with.In addition, the present invention can be each
Repeat reference numerals and/or character in a example.The repetition is that for purposes of simplicity and clarity, and itself is not indicated that
The relationship between each embodiment and/or configuration discussed.
In addition, for ease of description, can be used herein such as " ... under ", " ... below ", " lower part ",
" ... on ", the spatially relative term on " top " etc. an element or component as illustrated in the drawing are described and another is (another
It is some) relationship of element or component.Other than orientation shown in figure, spatially relative term, which is intended to be included in, to be used or operates
In device different orientation.Device can otherwise orient (be rotated by 90 ° or in other directions), and herein
Used in spatial relative descriptor can equally make and being interpreted accordingly.
Embodiment will be described with reference to specific context, that is, FinFET and forming method thereof.Grid work after use
Various embodiments presented herein are discussed in the context for the FinFET that skill is formed.In other embodiments, can make
With first grid technology.Moreover, some embodiments consider it is each used in planar device (for example, plane FET device)
Aspect.The various embodiments being discussed herein allow to be formed selectively gate spacer on the sidewalls of the gate, are formed for outer
The nucleated areas clearly limited for prolonging source/drain regions forms uniform epitaxial source/drain, expands process window, accurately
Technology controlling and process and easy process integration.
Fig. 1 shows the example of fin formula field effect transistor (FinFET) 10 with 3-D view.FinFET 10 includes substrate
Fin 16 on 12.Substrate 12 includes isolated area 14, and fin 16 is on adjacent isolation regions 14 and between adjacent isolation regions
Protrusion.Side wall of the gate-dielectric 18 along fin 16 and the top face positioned at fin 16, and gate electrode 20 is located at grid electricity
18 top of medium.Source/drain regions 22 and 24 are arranged in the opposite side of fin 16 relative to gate-dielectric 18 and gate electrode 20.
The purpose being merely to illustrate of FinFET 10 shown in Fig. 1 is provided, the scope of the present invention is not intended to limit.Therefore, many
Variation is possible, such as epitaxial source/drain, multiple fins, multilayer fin etc..
Fig. 2A to Figure 22 A to Figure 22 C is the sectional view in the intermediate stage of manufacture FinFET in accordance with some embodiments.
In Fig. 2A to Figure 22 A- Figure 22 C, other than multiple fins of multiple FinFET and each FinFET, along shown in Fig. 1
The attached drawing to end up with " A " label is shown with reference to cross section, A-A；Along shown in Fig. 1 refer to cross section B-B show with
The attached drawing of " B " label ending；And the attached drawing to end up with " C " label is shown along cross section C-C shown in Fig. 1.
Fig. 2A shows substrate 50.Substrate 50 can be semiconductor substrate, such as bulk semiconductor, semiconductor-on-insulator
(SOI) substrate etc., substrate 50 can be doped (for example, doped with p-type or n-type dopant) or undoped.Substrate 50 can be with
It is wafer, such as Silicon Wafer.In general, SOI substrate includes the semiconductor material layer to be formed on the insulating layer.Insulator layer can be
Buried oxide (BOX) layer, silicon oxide layer etc..Insulator layer is arranged on substrate, usually silicon or glass substrate.It can also
To use other substrates, such as multilayer or gradient substrate.In some embodiments, the semiconductor material of substrate 50 may include
Silicon；Germanium；Compound semiconductor, wherein the compound semiconductor includes silicon carbide, GaAs, gallium phosphide, indium phosphide, indium arsenide
And/or indium antimonide；Alloy semiconductor, wherein the alloy semiconductor include SiGe, GaAsP, AlInAs, AlGaAs, GaInAs,
GaInP and/or GaInAsP；Their combination etc..
Substrate 50 may further include integrated circuit device (not shown).As those skilled in the art will recognize that
It arrives, in substrate 50 and/or upper can form a variety of integrated circuit device, such as transistor, diode, capacitor, resistance
Device etc. or their combination, to generate the structure and function necessity of the design for obtained FinFET.It can make
Integrated circuit device is formed with any suitable method.
In some embodiments, suitable trap (not shown) can be formed in substrate 50.Caused by wherein
FinFET is in some embodiments of n-type device, and trap is p trap.It is p-type device in wherein generated FinFET
In some embodiments, trap is n trap.In other embodiments, both p trap and n trap are formed in substrate 50.In some embodiments
In, n-type impurity is injected into substrate 50 to form p trap.N-type impurity can be boron, BF2Deng, and can be injected and be equal to
Or less than 1018cm-3Concentration, such as about 1017cm-3To about 1018cm-3In the range of.In some embodiments, N-shaped is miscellaneous
Matter is injected into substrate 50 to form n trap.P-type impurity can be phosphorus, arsenic etc., and can be injected and be equal to or less than 1018cm-3Concentration, such as about 1017cm-3To about 1018cm-3In the range of.It, can be to substrate reality after injecting impurity appropriate
Annealing is applied to activate the p-type and p-type impurity of injection.
Fig. 2A also shows the formation mask 53 above substrate 50.In some embodiments, mask 53 can be used for then
Etching step in patterned substrate 50 (referring to Fig. 3 A).In some embodiments, mask 53 may include one or more
Mask layer.As shown in Figure 2 A, in some embodiments, mask 53 may include on the first mask layer 53A and the first mask layer 53A
Second mask layer 53B of side.First mask layer 53A can be hard mask layer, may include silica, silicon nitride, silicon oxynitride,
Silicon carbide, carbonitride of silicium, their combination etc., and any suitable technique can be used and formed, such as thermal oxide, hot nitrogen
Change, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), their combination etc..Subsequent
In etching step (referring to Fig. 3 A), the first mask layer 53A can be used for preventing or minimizing the substrate 50 below the first mask layer 53A
Etching.Second mask layer 53B may include photoresist, and in some embodiments, and the second mask layer 53B can be subsequent
Etching step in for pattern the first mask layer 53A.Second mask layer 53B can be formed simultaneously by using spin coating technique
And acceptable photoetching technique can be used and patterned.In some embodiments, mask 53 may include three or more
Mask layer.
Fig. 3 A shows the formation of the semiconductor bar 52 in substrate 50.Firstly, mask layer 53A and 53B can be patterned,
Wherein in mask layer 53A and 53B opening exposure substrate 50 will be formed groove 55 region.Next, implementable etching work
Skill, wherein etch process generates groove 55 by the opening in mask 53 in substrate 50.Substrate 50 is located at patterned cover
Rest part below mould 53 forms multiple semiconductor bars 52.Etching can be any acceptable etch process, such as react
Ion(ic) etching (RIE), neutral beam etching (NBE), their combination etc..Etch process can be anisotropic.In some realities
It applies in example, after forming semiconductor bar 52, any remainder of mask 53 can be removed by any suitable technique.?
In other embodiments, the part (such as first mask layer 53A) of mask 53 can be retained in the top of semiconductor bar 52.Some
In embodiment, semiconductor bar 52 can have the height H between about 70nm and about 95nm1, and between about 10nm peace treaty
Width W between 25nm1。
Fig. 4 A, which is shown, forms insulating materials to be formed in the groove 55 (referring to Fig. 3 A) between adjacent semiconductor item 52
Area of isolation 54.Insulating materials can be nitride of the oxide of silica, silicon nitride etc. or their combination,
And can by high-density plasma chemical gas deposition (HDP-CVD), flowable CVD (FCVD) (for example, it is long-range etc. from
Material based on CVD in daughter system deposit and afterwards solidification so that it is converted into another material, such as oxide), it
Combination etc. form the insulating materials.Also other insulating materials formed by any acceptable technique can be used.
In addition, in some embodiments, before filling groove 55 with the insulating materials of area of isolation 54, area of isolation 54
It may include the conformal liner (not shown) being formed on the side wall and bottom surface of groove 55 (referring to Fig. 3 A).In some embodiments
In, liner may include semiconductor (such as silicon) nitride, semiconductor (such as silicon) oxide, hot semiconductor (such as silicon) oxidation
Object, semiconductor (for example, silicon) nitrogen oxides, polymer, their combination etc..The formation of liner may include any suitable side
Method, such as ALD, CVD, HDP-CVD, PVD, their combination etc..In such embodiments, it is moved back in the subsequent of area of isolation 54
During fire, liner can prevent (or at least reducing) semiconductor material to be diffused into week from semiconductor bar 52 (for example, Si and/or Ge)
In the area of isolation 54 enclosed.It in some embodiments, can be to area of isolation after the insulating materials of deposition area of isolation 54
54 insulating materials implements annealing process.
Area of isolation 54 can be removed with further reference to the flatening process of Fig. 4 A, such as chemically mechanical polishing (CMP)
Any excessive insulating materials, so that the top surface of area of isolation 54 and the top surface of semiconductor bar 52 are coplanar.It is formed and is partly led wherein
After body item 52, the part of mask 53 is retained in some embodiments of 52 top of semiconductor bar, and flatening process can also be gone
Except the remainder of mask 53.
Fig. 5 A shows the recess of area of isolation 54 to form region shallow trench isolation (STI) 54.Area of isolation 54 is recessed
Sunken, so that fin 56 is protruded between adjacent area of isolation 54.In addition, the top surface of area of isolation 54 can have as shown in the figure
Flat surfaces, convex surface, concave surface (such as recess) or their combination.The top surface of area of isolation 54 can pass through etching appropriate
Be formed as flat, raised and/or recess.Acceptable etch process can be used (for example, to isolation in area of isolation 54
The material in region 54 selective etch process) it is recessed.For example, usingEtching, application material
SICONI tool (that is, SiCoNi precleaning tool) or dilute hydrofluoric acid (dHF) acid can be used to remove chemical oxidation
Object.
Those skilled in the art are it will be readily understood that only can be how with reference to Fig. 2A to Fig. 5 A technique described
Form an example of fin 56.In other embodiments, dielectric layer can be formed in the top face of substrate 50；It can etch and wear
Cross the groove of dielectric layer；It can epitaxial growth homoepitaxy structure in the trench；And dielectric layer can be recessed, so that outside homogeneity
Prolong structure to protrude from dielectric layer to form fin.In other embodiments, heteroepitaxial structure can be used for fin.For example, in Fig. 4 A
Semiconductor bar 52 can be recessed, and can in the position of the recess epitaxial growth one kind different from semiconductor bar 52 or
Multiple material.In another embodiment, dielectric layer can be formed in the top face of substrate 50；Dielectric layer can be etched through
Groove；One or more materials epitaxial growth heteroepitaxial structure in the trench different from substrate 50 can be used；And it is situated between
Electric layer can be recessed, so that heteroepitaxial structure is protruded from dielectric layer to form fin 56.
In wherein homoepitaxy or some embodiments of heteroepitaxial structure epitaxial growth, growth material can grown
Period carries out doping in situ.In other embodiments, it after homoepitaxy or heteroepitaxial structure epitaxial growth, can be used
Such as ion implanting adulterates homoepitaxy or heteroepitaxial structure.In various embodiments, fin 56 may include SiGe
(SixGe1-x, wherein x can be between about 0 and 1), silicon carbide, pure or substantially pure germanium, Group III-V compound semiconductor,
II-VI group compound semiconductor etc..For example, formed Group III-V compound semiconductor available material include but is not limited to InAs,
AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP etc..
Referring to Fig. 6 A and Fig. 6 B, dielectric layer 58 is formed on the side wall of fin 56 and top surface.In some embodiments, dielectric layer
58 can also be formed in 54 top of area of isolation.In other embodiments, the top surface of area of isolation 54 can not have dielectric layer 58.
Dielectric layer 58 may include the oxide of silica etc., and can deposit (for example, using ALD, CVD, PVD, they
Combination etc.) or according to thermally grown (for example, using thermal oxide etc.) dielectric layer of acceptable technology.In some embodiments, it is situated between
Electric layer 58 may include the dielectric material with acceptable breakdown voltage and leaking performance.Grid electricity is formed above dielectric layer 58
Pole layer 60, and mask 62 is formed above gate electrode layer 60.In some embodiments, gate electrode layer 60 can be deposited on dielectric
58 top of layer, and then planarized using such as CMP process.Mask 62 can be deposited on 60 top of gate electrode layer.Grid
Electrode layer 60 can be made of such as polysilicon, but also can be used has high etching selection for the material of area of isolation 54
The other materials of property.Mask 62 may include such as silica, silicon nitride, silicon oxynitride, silicon carbide, carbonitride of silicium, they
Combination etc. one or more layers, and any suitable technique can be used and form the mask, for example, thermal oxide, tropical resources,
ALD, PVD, CVD, their combination etc..In the shown embodiment, mask 62 includes oxide material, such as silica.One
In a little embodiments, mask 62 can have the thickness between about 20nm and about 70nm.
With reference to Fig. 7 A, Fig. 7 B and Fig. 7 C, can be used acceptable photoetching and etching technique come pattern mask 62 (referring to
Fig. 6 A and Fig. 6 B) to form pattern mask 72.It is transferred to by the pattern that acceptable etching technique will be patterned into mask 72
Gate electrode layer 60, to form grid 70.The respective channels area of the pattern covering fin 56 of grid 70, while the source electrode of exposure fin 56/
Drain region.In processing variation range, grid 70 also can have the length substantially vertical with the length direction of corresponding fin 56
Direction.The formation that spacing between the size and grid 70 of grid 70 can depend on tube core has the region of grid 70.One
In a little embodiments, when being located at logic region (for example, being provided with logic circuit) of such as tube core with grid compared with, grid
70 in the input/output region (for example, being provided with input/output circuitry) for being located at such as tube core when can have it is bigger
Size and bigger spacing.As described in greater detail below, grid 70 is to sacrifice grid and then by replacement gate
Replacement.Therefore, grid 70, which can also be referred to as, sacrifices grid 70.
Referring again to Fig. 7 A, Fig. 7 B and Fig. 7 C, it can be formed in substrate 50 and area source/drain (LDD) 75 is lightly doped.Class
It is similar to the injection technology discussed above with reference to Fig. 2A, impurity appropriate is injected into fin 56 to form LDD region domain 75.At it
In obtained FinFET be that n-type impurity is injected into fin 56 to form p-type LDD in some embodiments of p-type device
Area 75.In some embodiments that wherein obtained FinFET is n-type device, by p-type impurity be injected into fin 56 with
Form N-shaped LDD region 75.In the injection period of LDD region 75, grid 70 and patterned mask 72 may be used as exposure mask prevent (or
At least reducing) dopant is injected into the channel region of exposed fin 56.Therefore, LDD region 75 can be substantially formed in exposed
In the source/drain regions of fin 56.Before p-type impurity can be any n-type impurity being discussed above, and n-type impurity can be
Any n-type impurity that face discussed.LDD region 75 can have between about 1015cm-3To about 1016cm-3Between impurity concentration.?
After injection technology, it is possible to implement annealing process is to activate the impurity of injection.
Fig. 8 A to Figure 11 C shows the formation of the spacer 82 on the side wall of grid 70 in accordance with some embodiments.First
With reference to Fig. 8 A, Fig. 8 B and Fig. 8 C, dielectric layer is formed on the exposed surface for sacrificing grid 70, pattern mask 72 and dielectric layer 58
80.In some embodiments, dielectric layer 80 may include oxide, such as aluminium oxide (Al2O3) etc., and can be used CVD,
ALD etc. carrys out blanket and deposits the dielectric layer.Dielectric layer 80 includes aluminium oxide (Al wherein2O3) some embodiments in, can be used
Precursor forms dielectric layer 80, wherein the precursor includes trimethyl aluminium (TMA) and H2Mixture, trimethyl aluminium (TMA) and the O of O3/
O2Mixture etc..In some embodiments, can under the pressure between about 0.5 support and about 10 supports and about 25 DEG C with about
Dielectric layer 80 is formed at a temperature of between 350 DEG C.In some embodiments, dielectric layer 80 can have about 1nm and about 6nm it
Between thickness.
With reference to Fig. 9 A, Fig. 9 B and Fig. 9 C, work is added to fluorine is implemented on the expose portion of pattern mask 72 and dielectric layer 58
Skill (flaorination process), with the fluorinated region 59 formed in fluorination pattern mask 73 and dielectric layer 58.58 He of dielectric layer wherein
In some embodiments that pattern mask 72 is formed by the oxide of such as silica, flaorination process may include plasma work
Skill, such as SICONI technique.In some embodiments, SICONI technique is using including NF3、NH3, their combination etc. work
The plasma process that the mixture of skill gas is implemented.It in some embodiments, can be in about 90 DEG C and about 120 DEG C of temperature
Lower implementation SICONI technique.In some embodiments, dielectric layer 80 protects dielectric layer 58 and pattern mask 72 from being fluorinated
It is etched during technique.Therefore, in some embodiments, dielectric layer 80 can be by not being etched substantially during flaorination process
Material formed, allow for fluorine atom to be transferred to following layer (for example, dielectric layer 58 and pattern mask 72), and allow exist
Dielectric layer 58 and pattern mask 72 are protected during flaorination process.In some embodiments, fluorination pattern mask 73 can have
There is the atomic fraction (atomic fraction) of the fluorine between about 0.03 and about 0.05.In some embodiments, dielectric layer 58
Fluorinated region 59 can have the atomic fraction of the fluorine between about 0.03 and about 0.05.
With reference to Figure 10 A, Figure 10 B and Figure 10 C, after completing above-mentioned flaorination process, dielectric layer 80 is removed.In some implementations
In example, suitable etch process can be used and be optionally removed dielectric layer 80.Dielectric layer 80 includes aluminium oxide wherein
(Al2O3) some embodiments in, can be used dry method etch technology removal dielectric layer 80, wherein dry method etch technology using packet
Containing Cl2With SiCl4Mixture, Cl2With BCl3Mixture, Cl2With the process gas of the mixture of HBr etc..
With reference to Figure 11 A, Figure 11 B and Figure 11 C, spacer 82 is optionally formed on the side wall of grid 70.In some realities
It applies in example, spacer 82 may include dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide carbide
(SiOC), carbonitride of silicium (SiCN), carbon silicon oxynitride (SiOCN), their combination etc., and can be used CVD, ALD, they
Combination etc. form the spacer 82.In some embodiments, in the fluorination area of fluorination pattern mask 73 and dielectric layer 58
Inhibit the growth of the material of spacer 82 on the exposed surface in domain 59.Therefore, spacer 82 is optionally formed in grid 70
On side wall.By being formed selectively spacer 82, anisotropic etching process is omitted, this allow to avoid the formation of from it is each to
The possibility of anisotropic etch process is damaged, and the epitaxial source/drain to subsequently form provides the nucleation area clearly limited
Domain (well-defined nucleation area).In some embodiments, spacer 82 can have about 1nm with about
Width W between 6nm2。
Figure 12 A to Figure 15 C shows the formation of the spacer 82 on the side wall according to the grid 70 of alternative embodiment.First
With reference to Figure 12 A, Figure 12 B and Figure 12 C, dielectric layer 80 is optionally formed in the exposed surface of pattern mask 72 and dielectric layer 58
On.In some embodiments, dielectric layer 80 may include oxide, such as aluminium oxide (Al2O3) etc., and can be used CVD,
ALD etc. forms the dielectric layer.In some embodiments, can by select for dielectric layer 80 material appropriate precursor come
Realization is formed selectively dielectric layer 80.Dielectric layer 80 includes aluminium oxide (Al wherein2O3) some embodiments in, can make
With including triisobutyl aluminium (TiBA), three (dimethylamino) aluminium, three (DPM dpm,dipivalomethane acid) aluminium etc.
Precursor is formed selectively dielectric layer 80.In some embodiments, can under the pressure between about 0.5 support and about 10 supports and
Dielectric layer 80 is formed at a temperature of between about 25 DEG C and about 350 DEG C.In some embodiments, dielectric layer 80 can have about
Thickness between 1nm and about 6nm.
With reference to Figure 13 A, Figure 13 B and Figure 13 C, fluorine is implemented to the expose portion of pattern mask 72 and dielectric layer 58 and adds work
Skill (flaorination process), with the fluorinated region 59 formed in fluorination pattern mask 73 and dielectric layer 58.58 He of dielectric layer wherein
In some embodiments that pattern mask 72 is formed by the oxide of such as silica, flaorination process may include plasma work
Skill, such as SICONI technique.In some embodiments, SICONI technique is using including NF3、NH3, their combination etc. work
The plasma process that the mixture of skill gas is implemented.It in some embodiments, can be in about 90 DEG C and about 120 DEG C of temperature
Lower implementation SICONI technique.In some embodiments, dielectric layer 80 protects dielectric layer 58 and pattern mask 72 from being fluorinated
It is etched during technique.Therefore, in some embodiments, dielectric layer 80 can be by will not substantially be eclipsed during flaorination process
The material at quarter is formed, and allows for fluorine atom to be transferred to following layer (for example, dielectric layer 58 and pattern mask 72), and allow
Dielectric layer 58 and pattern mask 72 are protected during flaorination process.In some embodiments, fluorination pattern mask 73 can be with
Atomic fraction with the fluorine between about 0.03 and about 0.05.In some embodiments, the fluorinated region 59 of dielectric layer 58 can be with
Atomic fraction with the fluorine between about 0.03 and about 0.05.
With reference to Figure 14 A, Figure 14 B and Figure 14 C, after completing above-mentioned flaorination process, dielectric layer 80 is removed.In some implementations
In example, suitable etch process can be used and be optionally removed dielectric layer 80.Dielectric layer 80 includes aluminium oxide wherein
(Al2O3) some embodiments in, can be used dry method etch technology removal dielectric layer 80, wherein dry method etch technology using packet
Containing Cl2With SiCl4Mixture, Cl2With BCl3Mixture, Cl2With the process gas of the mixture of HBr etc..
With reference to Figure 15 A, Figure 15 B and Figure 15 C, spacer 82 is optionally formed on the side wall of grid 70.In some realities
It applies in example, spacer 82 may include dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide carbide
(SiOC), carbonitride of silicium (SiCN), carbon silicon oxynitride (SiOCN), their combination etc., and can be used CVD, ALD, they
Combination etc. form the spacer.In some embodiments, in the fluorinated region of fluorination pattern mask 73 and dielectric layer 58
Inhibit the growth of the material of spacer 82 on 59 exposed surface.Therefore, spacer 82 is optionally formed in the side of grid 70
On wall.By being formed selectively spacer 82, anisotropic etching process is omitted, this allows to be avoided losing from anisotropy
The possibility of carving technology is damaged, and the epitaxial source/drain to subsequently form provides the nucleated areas clearly limited.One
In a little embodiments, spacer 82 can have the width W between about 1nm and about 6nm2。
6A, Figure 16 B and Figure 16 C referring to Fig.1, are formed selectively after spacer 82, in fin on the side wall of grid 70
Implement Patternized technique on 56 to form groove 76 in the source/drain regions of fin 56.In some embodiments, Patternized technique
May include anisotropic dry etch process appropriate, at the same using fluorination pattern mask 73, grid 70, spacer 82,
And/or area of isolation 54 is as combination mask.Suitable anisotropic dry etch process may include reactive ion etching
(RIE), neutral beam etching (NBE), their combination etc..In some embodiments, can be removed during Patternized technique every
The fluorinated region 59 of dielectric layer 58 from 54 top of region.
With reference to Figure 17 A, Figure 17 B and Figure 17 C, epitaxial source/drain 84 is formed in groove 76 (referring to Figure 16 A, Figure 16 B
In Figure 16 C).In some embodiments, using metallorganic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy
(LPE), the epitaxial growth extension source in groove 76 such as vapour phase epitaxy (VPE), selective epitaxial growth (SEG), their combination
Pole/drain region 84.It is in some embodiments that n-type device and fin 56 are formed by silicon in wherein obtained FinFET,
Epitaxial source/drain 84 may include silicon, SiC, SiCP, SiP etc..Wherein resulting FinFET be p-type device simultaneously
And in some embodiments that are formed by silicon of fin 56, epitaxial source/drain 84 may include SiGe, SiGeB, Ge, GeSn etc..Outside
Prolong source/drain regions 84 can have the surface from the respective surfaces protrusion of fin 56 and can have facet (facet, again
Claim facet).In some embodiments, epitaxial source/drain 84 can extend past fin 56 and extend to semiconductor bar 52
In.In some embodiments, the material of epitaxial source/drain 84 can be injected with suitable dopant.In some embodiments
In, injection technology is similar with the formation technique of LDD region 75 above with reference to described in Fig. 7 A, Fig. 7 B and Fig. 7 C, and in order to succinct
For the sake of, it is not repeated to describe herein.It in other embodiments, can be in growth period original position doped epitaxial source/drain regions 84
Material.
It is in the shown embodiment, each in epitaxial source/drain 84 with further reference to Figure 17 A, Figure 17 B and Figure 17 C
It is a with other 84 physical separation of epitaxial source/drain.In other embodiments, adjacent epitaxial source/drain 84 can
It can merge.Such embodiment is depicted in Figure 22 A, Figure 22 B and Figure 22 C, wherein adjacent epitaxial source/drain 84 is closed
And to form public epitaxial source/drain 84.
With reference to Figure 18 A, Figure 18 B and Figure 18 C, above grid 70 and 84 disposed thereon of epitaxial source/drain is etched
Stop-layer 87 and interlayer dielectric (ILD) 88.In one embodiment, ILD 88 is the flowable film formed by flowable CVD.
In some embodiments, ILD 88 is by such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doping phosphosilicate glass
The dielectric material of glass (BPSG), undoped silicate glass (USG) etc. is formed, and can pass through such as CVD, PECVD, rotation
Any suitable method of glass technology, their combination etc. is applied to deposit the ILD 88.In some embodiments, etch stop
Layer 87 is used as stop-layer, while patterning ILD 88 to form the opening of the contact for subsequently forming.Therefore, Ke Yixuan
The material for etching stopping layer 87 is selected, so that the material of etching stopping layer 87 has etching speed more lower than the material of ILD 88
Rate.In some embodiments, it is possible to implement the flatening process of such as CMP is so that the top surface of ILD 88 and the top surface of grid 70 are neat
It is flat.In some embodiments, flatening process also removes fluorinated pattern mask 73.
With reference to Figure 19 A, Figure 19 B and Figure 19 C, grid 70 (referring to Figure 18 A, Figure 18 B and Figure 18 C) is removed in ILD 88
Form groove 90.In some embodiments, one or more suitable etch process can be used to remove grid 70.Groove 90
Each of expose the channel region of corresponding fin 56.In some embodiments, when grid 70 is etched, dielectric layer 58 can be with
As etching stopping layer.In some embodiments, after eliminating the gate electrode layer 60 of grid 70, dielectric layer can also be removed
58 expose portion.In some embodiments, the expose portion of dielectric layer 58 can be retained in groove 90.
With reference to Figure 20 A, Figure 20 B and Figure 20 C, gate dielectric is formed in groove 90 (referring to Figure 19 A, Figure 19 B and Figure 19 C)
Layer 92 and gate electrode layer 94.In some embodiments, gate dielectric 92 is conformally deposited in groove 90.In some embodiments
In, gate dielectric 92 includes silica, silicon nitride or their multilayer.In other embodiments, gate dielectric 92 includes
High-k dielectric material, and in these embodiments, gate dielectric 92 can have greater than about 7.0 k value, and can wrap
Include the silicate of metal oxide or Hf, Al, Zr, La, Mg, Ba, Ti, Pb and their combination.The formation of gate dielectric 92
Method may include molecular beam deposition (MBD), ALD, PECVD, their combination etc..In some embodiments, gate dielectric
92 can have the thickness between about 0.5nm and about 4nm.
With further reference to Figure 20 A, Figure 20 B and Figure 20 C, in the portion above the channel region of fin 56 of wherein dielectric layer 58
Divide in some embodiments not being removed, the part above the channel region of fin 56 of dielectric layer 58 can serve as gate dielectric
Boundary layer between layer 92 and the channel region of fin 56.It is gone in the part above the channel region of fin 56 of wherein dielectric layer 58
In some embodiments removed, boundary layer can be formed above the channel region of fin 56 before forming gate dielectric 92, and
Gate dielectric 92 is formed above boundary layer.Boundary layer is partly led useful as the high k dielectric layer subsequently formed and following
The buffering of body material.In some embodiments, boundary layer includes the chemical oxygen SiClx that can be formed by chemical reaction.For example, can be with
Use deionized water+ozone (O3)、NH4OH+H2O2+H2O (APM) or other methods form chemical oxide.Other embodiments
It can use the different materials to form boundary layer or technique (for example, thermal oxide or depositing operation).In some embodiments, interface
Layer can have the thickness between about 0.5nm and about 2nm.
Next, gate electrode layer 94 be deposited on the top of gate dielectric 92 and fill groove 90 rest part (referring to
Figure 19 A, Figure 19 B and Figure 19 C).In some embodiments, gate electrode layer 94 may include one or more layers suitable conduction material
Material.Gate electrode layer 94 may include from W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Co, Pd, Ni,
The metal selected in the group of Re, Ir, Ru, Pt, Zr and their combination.In some embodiments, gate electrode layer 94 can wrap
Include the metal selected from the group of TiN, WN, TaN, Ru and their combination.Such as Ti-Al, Ru-Ta, Ru- can be used
The metal alloy of Zr, Pt-Ti, Co-Ni and Ni-Ta and/or such as WN can be usedx、TiNx、MoNx、TaNxAnd TaSixNyGold
Belong to nitride.The appropriate process that ALD, CVD, PVD, plating, their combination etc. can be used forms gate electrode layer 94.?
In some embodiments, gate electrode layer 94 can have the thickness between about 0.5nm and about 6nm.Utilizing gate electrode layer 94
After filling groove 90, it is possible to implement the flatening process of such as CMP removes the more of gate dielectric 92 and gate electrode layer 94
Remaining part point, which is located at the top face of ILD 88.Therefore obtained gate electrode layer 94 and gate dielectric 92
The remainder of material forms the replacement gate 96 of obtained FinFET.In other embodiments, grid 70 can be with
It leaves rather than is substituted by replacement gate 96.
With reference to Figure 21 A, Figure 21 B and Figure 21 C, in 88 disposed thereon ILD 102 of ILD, contact 104 is formed through ILD
102 and ILD 88, and contact 108 is formed through ILD 102.In one embodiment, using with above with reference to figure
18A, Figure 18 B similar with the ILD 88 that Figure 18 C is described material and method forms ILD 102, and for simplicity,
This is not repeated to describe.In some embodiments, ILD 102 and ILD 88 are formed from the same material.In other embodiments,
ILD 102 and ILD 88 are formed from different materials.
With further reference to Figure 21 A, Figure 21 B and Figure 21 C, the opening for contact 104 is formed through ILD 88 and ILD
102 and etching stopping layer 87, and the opening for contact 108 is formed through ILD 102 and etching stopping layer
87.These openings can be all formed simultaneously in same technique or in separated technique.Acceptable light can be used
It carves and etching technique is open to be formed.In some embodiments, the lining of diffusion barrier layer, adhesion layer etc. is formed in the opening
Pad and conductive material.Liner may include titanium, titanium nitride, tantalum, tantalum nitride, their combination etc..Conductive material can be
Copper, copper alloy, silver, gold, tungsten, aluminium, nickel or their combination etc..The flatening process of such as CMP can be implemented, with from ILD
102 top surface removes excess stock.Remaining liner and conductive material form contact 104 and 108.Annealing process can be implemented
Silicide (not shown) is formed with the interface between epitaxial source/drain 84 and corresponding contact 104.Contact 104
It is physically and electrically coupled to epitaxial source/drain 84, and contact 108 is physically and electrically coupled to replacement gate 96.Although
Contact 104 is shown with cross section identical with contact 108 in Figure 21 B, but the purpose that the figure is merely to illustrate, and
In some embodiments, contact 104 be can be set in the cross section different from contact 108.
Figure 22 A, Figure 22 B and Figure 22 C show similar with FinFET shown in Figure 21 A, Figure 21 B and Figure 21 C
The sectional view of FinFET, wherein identical element is marked with identical number designation.In some embodiments, scheme
The FinFET of 22A, Figure 22 B and Figure 22 C can be used Figure 21 A, Figure 21 B as described in above with reference to Fig. 2A to Figure 21 C and
The similar material and method of Figure 21 C and FinFET are formed, and for simplicity, the description is no longer heavy herein
It is multiple.In the shown embodiment, adjacent epitaxial source/drain 84 merges to form public epitaxial source/drain 84.One
In a little embodiments, gap (not shown) can be formed in public 84 lower section of epitaxial source/drain, and be located at public extension source
Between pole/drain region 84 and area of isolation 54.In some embodiments, gap is filled with the material of ILD 88.In shown implementation
In example, public epitaxial source/drain 84 has flat top surface.In other embodiments, public epitaxial source/drain 84
It can have the top surface of non-flat forms.
Figure 23 is the flow chart for showing the method 230 in accordance with some embodiments for forming FinFET.Method 230 is from step
Rapid 231 start, and wherein substrate (for example, substrate 50 shown in Fig. 2A) is patterned to form such as above with reference to Fig. 2A to Fig. 5 A
The fin (for example, fin 56 shown in Fig. 5 A) of description.In step 232, such as above with reference to Fig. 6 A, Fig. 6 B and Fig. 7 A to Fig. 7 C
It is described, it is formed above fin and sacrifices gate stack (for example, grid 70 shown in Fig. 7 A and Fig. 7 B).In step 233, such as
Above with reference to described in Fig. 8 A to Figure 11 C or Figure 12 A to Figure 15 C, between being formed selectively on the side wall for sacrificing gate stack
Spacing body (for example, spacer 82 shown in Figure 11 B or Figure 15 B).In step 234, as above with reference to figures 16A to Figure 16 C institute
It states, uses and sacrifice gate stack and spacer as combination mask to pattern fin, to form groove in fin (for example, figure
Groove 76 shown in 16B and Figure 16 C).In this step 235, as described in above referring to figs. 17A through Figure 17 C, extension in a groove
It grows source/drain regions (for example, epitaxial source/drain 84 shown in Figure 17 B and Figure 17 C).In step 236, as above
Face forms alternative gate stack part (for example, replacing shown in Figure 20 A and Figure 20 B with reference to described in Figure 18 A to Figure 20 C above fin
For grid 96).
The various embodiments being discussed herein allow to be formed selectively gate spacer on the sidewalls of the gate, and formation is used for
The nucleated areas of epitaxial source/drain clearly limited forms uniform epitaxial source/drain, expands process window, essence
True technology controlling and process and simplified technique are integrated.
According to one embodiment, a kind of method includes: the fin for being formed in and extending above area of isolation；It is formed above fin sacrificial
Domestic animal grid；It is optionally deposited the first dielectric material on the side wall for sacrificing grid, between being formed on the side wall for sacrificing grid
Spacing body, wherein the first dielectric material is not deposited on the top face for sacrificing grid；Use and sacrifices grid and spacer as combination
Mask patterns fin, to form groove in fin；And epitaxial source/drain is formed in a groove.In one embodiment
In, it includes: that gate electrode layer is formed above fin that sacrifice grid is formed above fin；Patterning is formed above gate electrode layer to cover
Mould；And it will be patterned into the pattern of mask and be transferred to gate electrode layer.In one embodiment, this method further includes, in sacrificial gate
It is optionally deposited on the side wall of pole before the first dielectric material, flaorination process is implemented to pattern mask.In one embodiment
In, this method further includes before implementing flaorination process to pattern mask, being formed on the side wall of pattern mask and top surface
Second dielectric material.In one embodiment, this method further includes after implementing flaorination process to pattern mask, removing
Second dielectric material.In one embodiment, the second dielectric material is formed on the side wall of pattern mask and top surface further includes
The second dielectric material is formed on the side wall for sacrificing grid.In one embodiment, on the side wall and top surface of pattern mask
Forming the second dielectric material includes selectively by the second dielectric deposition on the side wall and top surface of pattern mask.
In embodiment, it includes: to form gate electrode layer above the fin that the sacrifice grid is formed above the fin；
Pattern mask is formed above the gate electrode layer；And the pattern of the pattern mask is transferred to the gate electrode
Layer.
In embodiment, it is used to form the method for semiconductor devices further include: select on the side wall for sacrificing grid
Property deposit first dielectric material before, to the pattern mask implement flaorination process.
In embodiment, it is used to form the method for semiconductor devices further include: described in implementing to the pattern mask
Before flaorination process, the second dielectric material is formed on the side wall of the pattern mask and top surface.
In embodiment, it is used to form the method for semiconductor devices further include: described in implementing to the pattern mask
After flaorination process, second dielectric material is removed.
In embodiment, formed on the side wall of the pattern mask and top surface second dielectric material further include
Second dielectric material is formed on the side wall for sacrificing grid.
In embodiment, it includes selection that second dielectric material is formed on the side wall of the pattern mask and top surface
Property by second dielectric deposition on the side wall and top surface of the pattern mask.
According to another embodiment, a kind of method includes: so that area of isolation is recessed to expose the side wall of semiconductor fin；Half
Gate electrode layer is formed above conductor fin；Pattern mask is formed above gate electrode layer；Remove the grid exposed by pattern mask
Grid is sacrificed to be formed above semiconductor fin in the part of electrode layer；Flaorination process is being implemented to form fluorine to pattern mask
Change pattern mask；It is optionally deposited the first dielectric material on the side wall for sacrificing grid, on the side wall for sacrificing grid
Form spacer；Use fluorination pattern mask, sacrifice grid and spacer as mask is combined to etch semiconductor fin, with
Groove is formed in semiconductor fin；And deposited semiconductor material in a groove.In one embodiment, this method further includes,
Before implementing flaorination process to pattern mask, the second dielectric material is formed on the side wall of pattern mask and top surface.One
In a embodiment, the second dielectric material includes aluminium oxide.In one embodiment, this method further include: above semiconductor fin
It is formed before gate electrode layer, forms third dielectric material above semiconductor fin.In one embodiment, this method further include:
It is formed above semiconductor fin after sacrificing grid, forms the second dielectric material above the expose portion of third dielectric material；
And flaorination process is implemented to the expose portion of third dielectric material.In one embodiment, pattern mask includes oxide
Material.In one embodiment, implementing flaorination process includes that use contains NF3The mixture of process gas implement plasma
Body technology.
In embodiment, it is used to form the method for semiconductor devices further include: described in implementing to the pattern mask
Before flaorination process, the second dielectric material is formed on the side wall of the pattern mask and top surface.
In embodiment, second dielectric material includes aluminium oxide.
In embodiment, it is used to form the method for semiconductor devices further include: described in being formed above the semiconductor fin
Before gate electrode layer, third dielectric material is formed above the semiconductor fin.
In embodiment, it is used to form the method for semiconductor devices further include: described in being formed above the semiconductor fin
After sacrificing grid, second dielectric material is formed above the expose portion of the third dielectric material；And to described
The expose portion of third dielectric material implements the flaorination process.
In embodiment, the pattern mask includes oxide material.
In embodiment, implementing the flaorination process includes that use contains NF3The mixture of process gas implement
Ionomer technology.
According to yet another embodiment, a kind of method includes: the side wall for etching area of isolation to expose semiconductor fin；In semiconductor
The first oxide material is formed on the side wall of fin and top surface；Conductive material is formed above the first oxide material；In conduction material
Material top forms the second oxide material；The second oxide material is etched to form the second oxide material of patterning；Use figure
The second oxide material of caseization etches conductive material as mask, sacrifices grid to be formed above semiconductor fin；In pattern
Change on the side wall and top surface of the second oxide material and the expose portion of the first oxide material top forms the first dielectric material
Material；Implement flaorination process, flaorination process shape in the expose portion to the second oxide material of patterning and the first oxide material
The second oxide material is patterned at fluorination；Remove the first dielectric material；The is optionally deposited on the side wall for sacrificing grid
Two dielectric materials；Use the second oxide material of fluorination patterning, sacrifice grid and the second dielectric material as combination mask
Semiconductor fin is etched, to form groove in semiconductor fin；And epitaxial growth of semiconductor material in a groove.Implement at one
In example, this method further includes, and before implementing flaorination process, forms the first dielectric material on the side wall for sacrificing grid.One
In a embodiment, this method further includes being replaced sacrificing grid with replacement gate.In one embodiment, implementing flaorination process includes
Using containing NF3And NH3The mixture of process gas implement plasma process.In one embodiment, removal first is situated between
Electric material includes the first dielectric material of etching.In one embodiment, flaorination process does not etch the first dielectric material substantially.
In embodiment, it is used to form the method for semiconductor devices further include: before implementing the flaorination process, in institute
It states and forms first dielectric material on the side wall for sacrificing grid.
In embodiment, it is used to form the method for semiconductor devices further include: replace the sacrifice grid with replacement gate.
In embodiment, implementing the flaorination process includes that use contains NF3And NH3Process gas mixture come it is real
Apply plasma process.
In embodiment, removing first dielectric material includes etching first dielectric material.
In embodiment, the flaorination process does not etch first dielectric material.
Fin can be patterned by any suitable method.It is, for example, possible to use one or more photoetching processes (including
Double patterning or multiple Patternized technique) pattern fin.In general, double patterning or multiple Patternized technique combine light
Quarter and self-registered technology, so that allowing the pattern created to have can such as obtain than using single direct photoetching process otherwise
The closely spaced spacing obtained.For example, in one embodiment, it is rectangular on substrate to be carried out at sacrificial layer and using photoetching process
Patterning.Spacer is formed along the side wall of patterned sacrificial layer using self-registered technology.Then sacrificial layer is removed, and so
After remaining spacer can be used to pattern fin.
The feature of several embodiments discussed above so that those skilled in the art may be better understood it is of the invention
Various aspects.It should be appreciated by those skilled in the art that they can easily design or more using based on the present invention
Change other for reaching purpose identical with embodiment defined herein and/or realizing the process and structure of same advantage.Ability
Field technique personnel it should also be appreciated that these equivalent structures without departing from the spirit and scope of the present invention, and without departing substantially from this
In the case where the spirit and scope of invention, a variety of variations can be carried out, replaced and changed.
Claims (10)
1. a kind of method for being used to form semiconductor devices, comprising:
It is formed in the fin extended above area of isolation；
It is formed above the fin and sacrifices grid；
It is optionally deposited the first dielectric material on the side wall for sacrificing grid, with the shape on the side wall for sacrificing grid
Part at interval, wherein first dielectric material is not deposited on the top face for sacrificing grid；
The sacrifice grid and the spacer is used to pattern the fin as combination mask, it is to be formed in the fin recessed
Slot；And
Epitaxial source/drain is formed in the groove.
2. the method according to claim 1 for being used to form semiconductor devices, wherein formed above the fin described sacrificial
Domestic animal grid includes:
Gate electrode layer is formed above the fin；
Pattern mask is formed above the gate electrode layer；And
The pattern of the pattern mask is transferred to the gate electrode layer.
3. the method according to claim 2 for being used to form semiconductor devices, further includes:
It is real to the pattern mask before being optionally deposited first dielectric material on the side wall for sacrificing grid
Apply flaorination process.
4. the method according to claim 3 for being used to form semiconductor devices, further includes:
Before implementing the flaorination process to the pattern mask, formed on the side wall of the pattern mask and top surface
Second dielectric material.
5. the method according to claim 4 for being used to form semiconductor devices, further includes:
After implementing the flaorination process to the pattern mask, second dielectric material is removed.
6. the method according to claim 4 for being used to form semiconductor devices, wherein in the side wall of the pattern mask
It further include forming second dielectric material on the side wall for sacrificing grid with second dielectric material is formed on top surface.
7. the method according to claim 4 for being used to form semiconductor devices, wherein in the side wall of the pattern mask
It include selectively covering second dielectric deposition in the patterning with second dielectric material is formed on top surface
On the side wall and top surface of mould.
8. a kind of method for being used to form semiconductor devices, comprising:
So that area of isolation is recessed to expose the side wall of semiconductor fin；
Gate electrode layer is formed above the semiconductor fin；
Pattern mask is formed above the gate electrode layer；
The part of the gate electrode layer exposed by the pattern mask is removed, is sacrificed with being formed above the semiconductor fin
Grid；
Flaorination process is implemented to form fluorination pattern mask to the pattern mask；
It is optionally deposited the first dielectric material on the side wall for sacrificing grid, with the shape on the side wall for sacrificing grid
Part at interval；
Use the fluorination pattern mask, the sacrifice grid and the spacer as combination mask described partly to lead to etch
Body fin, to form groove in the semiconductor fin；And
The deposited semiconductor material in the groove.
9. the method according to claim 8 for being used to form semiconductor devices, further includes:
Before implementing the flaorination process to the pattern mask, formed on the side wall of the pattern mask and top surface
Second dielectric material.
10. a kind of method for being used to form semiconductor devices, comprising:
Area of isolation is etched to expose the side wall of semiconductor fin；
The first oxide material is formed on the side wall of the semiconductor fin and top surface；
Conductive material is formed above first oxide material；
The second oxide material is formed above the conductive material；
Second oxide material is etched to form the second oxide material of patterning；
The second oxide material of the patterning is used to etch the conductive material as mask, in the semiconductor fin
It is rectangular at sacrifice grid；
It is described patterning the second oxide material side wall and top surface on and first oxide material expose portion
Top forms the first dielectric material；
Flaorination process is implemented to the expose portion of the second oxide material of the patterning and first oxide material, it is described
Flaorination process forms fluorination the second oxide material of patterning；
Remove first dielectric material；
The second dielectric material is optionally deposited on the side wall for sacrificing grid；
Use the fluorination to pattern the second oxide material, the sacrifice grid and second dielectric material to cover as combination
Mould etches the semiconductor fin, to form groove in the semiconductor fin；And
The epitaxial growth of semiconductor material in the groove.
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| US201762565794P | 2017-09-29 | 2017-09-29 | |
| US62/565,794 | 2017-09-29 | ||
| US15/907,633 | 2018-02-28 | ||
| US15/907,633 US10505021B2 (en) | 2017-09-29 | 2018-02-28 | FinFet device and method of forming the same |
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| DE102018106191A1 (en) | 2019-04-04 |
| CN109585294B (en) | 2022-03-08 |
| DE102018106191B4 (en) | 2023-06-15 |
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