CN109585294B

CN109585294B - FINFET device, semiconductor device and forming method thereof

Info

Publication number: CN109585294B
Application number: CN201810917121.0A
Authority: CN
Inventors: 柯忠廷; 卢柏全; 李志鸿; 徐志安
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2017-09-29
Filing date: 2018-08-13
Publication date: 2022-03-08
Anticipated expiration: 2038-08-13
Also published as: DE102018106191A1; CN109585294A; DE102018106191B4

Abstract

FinFET devices and methods of forming the same are provided. The method includes forming a fin extending over an isolation region. A sacrificial gate is formed over the fin. A first dielectric material is selectively deposited on the sidewalls of the sacrificial gate to form spacers on the sidewalls of the sacrificial gate. The fin is patterned using the sacrificial gate and the spacer as a combinatorial mask to form a recess in the fin. Epitaxial source/drain regions are formed in the recesses. The embodiment of the invention also provides a forming method of the semiconductor device.

Description

FINFET device, semiconductor device and forming method thereof

Technical Field

Embodiments of the invention relate generally to the field of semiconductor technology and, more particularly, to FINFET devices, semiconductor devices, and methods of forming the same.

Background

Semiconductor devices are used in various electronic applications such as, for example, personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by the following steps: layers of insulating or dielectric, conductive, and semiconductor materials are sequentially deposited over a semiconductor substrate, and the various material layers are patterned using photolithography to form circuit components and elements located over the circuit components.

The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuing to reduce the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed.

Disclosure of Invention

According to an aspect of the present invention, there is provided a method for forming a semiconductor device, including: forming a fin extending over the isolation region; forming a sacrificial gate over the fin; selectively depositing a first dielectric material on sidewalls of the sacrificial gate to form spacers on the sidewalls of the sacrificial gate, wherein the first dielectric material is not deposited over a top surface of the sacrificial gate; patterning the fin using the sacrificial gate and the spacer as a combinatorial mask to form a recess in the fin; and forming epitaxial source/drain regions in the recesses.

According to another aspect of the present invention, there is provided a method for forming a semiconductor device, comprising: recessing the isolation region to expose sidewalls of the semiconductor fin; forming a gate electrode layer over the semiconductor fin; forming a patterned mask over the gate electrode layer; removing portions of the gate electrode layer exposed by the patterned mask to form a sacrificial gate over the semiconductor fin; performing a fluorination process on the patterned mask to form a fluorinated patterned mask; selectively depositing a first dielectric material on sidewalls of the sacrificial gate to form spacers on the sidewalls of the sacrificial gate; etching the semiconductor fin using the fluorinated patterned mask, the sacrificial gate, and the spacer as a combinatorial mask to form a recess in the semiconductor fin; and depositing a semiconductor material in the recess.

According to yet another aspect of the present invention, there is provided a method for forming a semiconductor device, comprising: etching the isolation region to expose sidewalls of the semiconductor fin; forming a first oxide material on sidewalls and a top surface of the semiconductor fin; forming a conductive material over the first oxide material; forming a second oxide material over the conductive material; etching the second oxide material to form a patterned second oxide material; etching the conductive material using the patterned second oxide material as a mask to form a sacrificial gate over the semiconductor fin; forming a first dielectric material on sidewalls and a top surface of the patterned second oxide material and over exposed portions of the first oxide material; performing a fluorination process on the patterned second oxide material and the exposed portions of the first oxide material, the fluorination process forming a fluorinated patterned second oxide material; removing the first dielectric material; selectively depositing a second dielectric material on sidewalls of the sacrificial gate; etching the semiconductor fin using the fluorinated patterned second oxide material, the sacrificial gate, and the second dielectric material as a combinatorial mask to form a recess in the semiconductor fin; and epitaxially growing a semiconductor material in the recess.

Drawings

The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a perspective view of a fin field effect transistor ("FinFET") device according to some embodiments.

Fig. 2A-5A are cross-sectional views of an intermediate stage in fabricating a FinFET device according to some embodiments.

Fig. 6A and 6B are cross-sectional views of an intermediate stage in fabricating a FinFET device according to some embodiments.

Fig. 7A, 7B, and 7C are cross-sectional views of an intermediate stage in fabricating a FinFET device according to some embodiments.

Fig. 8A, 8B, and 8C are cross-sectional views of an intermediate stage in fabricating a FinFET device according to some embodiments.

Fig. 9A, 9B, and 9C are cross-sectional views of an intermediate stage in fabricating a FinFET device according to some embodiments.

Fig. 10A, 10B, and 10C are cross-sectional views of an intermediate stage in fabricating a FinFET device according to some embodiments.

Fig. 11A, 11B, and 11C are cross-sectional views of an intermediate stage in fabricating a FinFET device according to some embodiments.

Fig. 12A, 12B, and 12C are cross-sectional views of an intermediate stage in fabricating a FinFET device according to some embodiments.

Fig. 13A, 13B, and 13C are cross-sectional views of an intermediate stage in fabricating a FinFET device according to some embodiments.

Fig. 14A, 14B, and 14C are cross-sectional views of an intermediate stage in fabricating a FinFET device according to some embodiments.

Fig. 15A, 15B, and 15C are cross-sectional views of an intermediate stage in fabricating a FinFET device according to some embodiments.

Fig. 16A, 16B, and 16C are cross-sectional views of an intermediate stage in fabricating a FinFET device according to some embodiments.

Fig. 17A, 17B, and 17C are cross-sectional views of FinFET devices according to some embodiments.

Fig. 18A, 18B, and 18C are cross-sectional views of FinFET devices according to some embodiments.

Fig. 19A, 19B, and 19C are cross-sectional views of FinFET devices according to some embodiments.

Fig. 20A, 20B, and 20C are cross-sectional views of FinFET devices according to some embodiments.

Fig. 21A, 21B, and 21C are cross-sectional views of FinFET devices according to some embodiments.

Fig. 22A, 22B, and 22C are cross-sectional views of FinFET devices according to some embodiments.

Fig. 23 is a flow diagram illustrating a method of forming a FinFET device, according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Embodiments, i.e., FinFET devices and methods of forming the same, will be described with reference to specific contexts. Various embodiments presented herein are discussed in the context of FinFET devices formed using a gate-last process. In other embodiments, a gate first process may be used. Moreover, some embodiments contemplate various aspects for use in planar-type devices (e.g., planar FET devices). The various embodiments discussed herein allow for the selective formation of gate spacers on the sidewalls of the gate, the formation of well-defined nucleation regions for epitaxial source/drain regions, the formation of uniform epitaxial source/drain regions, the enlargement of the process window, precise process control and easy process integration.

Fig. 1 shows an example of a fin field effect transistor (FinFET)10 in a three-dimensional view. The FinFET 10 includes a fin 16 on a substrate 12. The substrate 12 includes isolation regions 14, and the fins 16 project over and between adjacent isolation regions 14. A gate dielectric 18 is along the sidewalls of the fin 16 and over the top surface of the fin 16, and a gate electrode 20 is over the gate dielectric 18. Source/

drain regions

22 and 24 are disposed in opposite sides of the fin 16 relative to the gate dielectric 18 and the gate electrode 20. The FinFET 10 shown in fig. 1 is provided for illustrative purposes only and is not meant to limit the scope of the present invention. Thus, many variations are possible, such as epitaxial source/drain regions, multiple fins, multiple layers of fins, and the like.

Fig. 2A-22C are cross-sectional views of intermediate stages in fabricating a FinFET device according to some embodiments. In fig. 2A-22C, the figure ending with the "a" designation is shown along the reference cross-section a-a shown in fig. 1, except for the plurality of finfets and the plurality of fins of each FinFET; the figure ending with the "B" label is shown along the reference cross-section B-B shown in figure 1; and the figure ending with the "C" label is shown along the cross-section C-C shown in figure 1.

Fig. 2A shows a substrate 50. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, and the substrate 50 may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a layer of semiconductor material formed on an insulating layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of substrate 50 may include silicon; germanium; a compound semiconductor, wherein the compound semiconductor comprises silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor, wherein the alloy semiconductor comprises SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; combinations thereof and the like.

Substrate 50 may further include integrated circuit devices (not shown). As will be appreciated by one of ordinary skill in the art, a variety of integrated circuit devices, such as transistors, diodes, capacitors, resistors, and the like, or combinations thereof, may be formed in and/or on the substrate 50 to create structural and functional requirements for the design of the resulting FinFET device. Any suitable method may be used to form the integrated circuit device.

In some embodiments, suitable wells (not shown) may be formed in the substrate 50. In some embodiments, where the resulting FinFET device is an n-type device, the well is a p-well. FinFET produced thereinIn some embodiments where the device is a p-type device, the well is an n-well. In other embodiments, both p-wells and n-wells are formed in the substrate 50. In some embodiments, p-type impurities are implanted into substrate 50 to form a p-well. The p-type impurity may be boron or BF₂Etc., and may be injected to equal to or less than 10¹⁸cm^-3E.g. at a concentration of about 10¹⁷cm^-3To about 10¹⁸cm^-3Within the range of (1). In some embodiments, n-type impurities are implanted into the substrate 50 to form an n-well. The n-type impurity may be phosphorus, arsenic, or the like, and may be implanted to 10 or less¹⁸cm^-3E.g. at a concentration of about 10¹⁷cm^-3To about 10¹⁸cm^-3Within the range of (1). After implanting the appropriate impurities, an anneal may be performed on the substrate to activate the implanted p-type and n-type impurities.

Fig. 2A also shows the formation of a mask 53 over the substrate 50. In some embodiments, the mask 53 may be used in a subsequent etching step to pattern the substrate 50 (see fig. 3A). In some embodiments, mask 53 may include one or more mask layers. As shown in fig. 2A, in some embodiments, the mask 53 may include a first mask layer 53A and a second mask layer 53B over the first mask layer 53A. The first mask layer 53A may be a hard mask layer, may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, combinations thereof, and the like, and may be formed using any suitable process, such as thermal oxidation, thermal nitridation, Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), combinations thereof, and the like. In a subsequent etching step (see fig. 3A), the first mask layer 53A may be used to prevent or minimize etching of the substrate 50 below the first mask layer 53A. The second mask layer 53B may comprise photoresist and, in some embodiments, the second mask layer 53B may be used to pattern the first mask layer 53A in a subsequent etching step. The second mask layer 53B may be formed by using a spin coating technique and may be patterned using an acceptable photolithography technique. In some embodiments, mask 53 may include three or more mask layers.

FIG. 3A shows a semiconductor strip in a substrate 5052. First, masking

layers

53A and 53B may be patterned, with openings in masking

layers

53A and 53B exposing regions of substrate 50 where trenches 55 will be formed. Next, an etching process may be performed, wherein the etching process creates trenches 55 in the substrate 50 through the openings in the mask 53. The remaining portion of the substrate 50 underlying the patterned mask 53 forms a plurality of semiconductor strips 52. The etch may be any acceptable etch process such as Reactive Ion Etch (RIE), Neutral Beam Etch (NBE), combinations thereof, and the like. The etching process may be anisotropic. In some embodiments, after forming the semiconductor strips 52, any remaining portions of the mask 53 may be removed by any suitable process. In other embodiments, portions of the mask 53 (e.g., the first mask layer 53A) may remain over the semiconductor strips 52. In some embodiments, the semiconductor strips 52 may have a height H between about 70nm and about 95nm₁And a width W between about 10nm and about 25nm₁。

Fig. 4A illustrates the formation of insulating material in trenches 55 (see fig. 3A) between adjacent semiconductor strips 52 to form isolation regions 54. The insulating material may be an oxide such as silicon oxide, a nitride such as silicon nitride, or the like, or combinations thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (fcvd) (e.g., CVD-based material in a remote plasma system is deposited and post-cured to convert it to another material, such as an oxide), combinations thereof, or the like. Other insulating materials formed by any acceptable process may also be used.

Furthermore, in some embodiments, prior to filling trench 55 with the insulating material of isolation region 54, isolation region 54 may include a conformal liner (not shown) formed on sidewalls and a bottom surface of trench 55 (see fig. 3A). In some embodiments, the liner may comprise a semiconductor (e.g., silicon) nitride, a semiconductor (e.g., silicon) oxide, a thermal semiconductor (e.g., silicon) oxide, a semiconductor (e.g., silicon) oxynitride, a polymer, combinations thereof, and the like. The formation of the liner may include any suitable method, such as ALD, CVD, HDP-CVD, PVD, combinations thereof, and the like. In such embodiments, during the subsequent anneal of the isolation regions 54, the liner may prevent (or at least reduce) diffusion of semiconductor material from the semiconductor strips 52 (e.g., Si and/or Ge) into the surrounding isolation regions 54. In some embodiments, after depositing the insulating material of the isolation regions 54, an annealing process may be performed on the insulating material of the isolation regions 54.

With further reference to fig. 4A, a planarization process, such as Chemical Mechanical Polishing (CMP), may remove any excess insulating material of the isolation regions 54 so that the top surfaces of the isolation regions 54 and the top surfaces of the semiconductor strips 52 are coplanar. In some embodiments in which portions of the mask 53 remain over the semiconductor strips 52 after the semiconductor strips 52 are formed, the planarization process may also remove remaining portions of the mask 53.

Fig. 5A illustrates the recessing of the isolation regions 54 to form Shallow Trench Isolation (STI) regions 54. The isolation regions 54 are recessed such that the fins 56 protrude from between adjacent isolation regions 54. Further, the top surface of the isolation region 54 may have a flat surface, convex, concave (e.g., concave), or a combination thereof as shown. The top surface of isolation region 54 may be formed flat, convex, and/or concave by suitable etching. The isolation regions 54 may be recessed using an acceptable etch process (e.g., an etch process that is selective to the material of the isolation regions 54). For example, use

The chemical oxide may be removed by etching, applying a material SICONI tool (i.e., SICONI preclean tool), or using dilute hydrofluoric acid (dHF) acid.

Those of ordinary skill in the art will readily appreciate that the process described with reference to fig. 2A-5A is merely one example of how the fin 56 may be formed. In other embodiments, a dielectric layer may be formed over the top surface of the substrate 50; a trench may be etched through the dielectric layer; a homoepitaxial structure can be epitaxially grown in the trench; and the dielectric layer may be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form the fin. In other embodiments, a heteroepitaxial structure may be used for the fins. For example, the semiconductor strips 52 in fig. 4A may be recessed, and one or more materials different from the semiconductor strips 52 may be epitaxially grown in the recessed locations. In yet another embodiment, a dielectric layer may be formed over the top surface of the substrate 50; a trench may be etched through the dielectric layer; the heteroepitaxial structure may be epitaxially grown in the trench using one or more materials different from the substrate 50; and the dielectric layer may be recessed such that the hetero-epitaxial structure protrudes from the dielectric layer to form fin 56.

In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the growth material may be doped in situ during growth. In other embodiments, the homoepitaxial or heteroepitaxial structure may be doped after epitaxial growth of the homoepitaxial or heteroepitaxial structure, such as by ion implantation. In various embodiments, fin 56 may comprise silicon germanium (Si)_xGe_1-xWhere x may be between about 0 and 1), silicon carbide, pure or substantially pure germanium, group III-V compound semiconductors, group II-VI compound semiconductors, and the like. For example, useful materials for forming III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

Referring to fig. 6A and 6B, a dielectric layer 58 is formed on the sidewalls and top surface of fin 56. In some embodiments, a dielectric layer 58 may also be formed over the isolation region 54. In other embodiments, the top surface of the isolation region 54 may be free of the dielectric layer 58. The dielectric layer 58 may comprise an oxide such as silicon oxide, and may be deposited (e.g., using ALD, CVD, PVD, combinations thereof, and the like) or thermally grown (e.g., using thermal oxidation and the like) according to acceptable techniques. In some embodiments, the dielectric layer 58 may comprise a dielectric material having acceptable breakdown voltage and leakage properties. A gate electrode layer 60 is formed over dielectric layer 58 and a mask 62 is formed over gate electrode layer 60. In some embodiments, a gate electrode layer 60 may be deposited over the dielectric layer 58 and then planarized using, for example, a CMP process. A mask 62 may be deposited over gate electrode layer 60. The gate electrode layer 60 may be made of, for example, polysilicon, but other materials having high etching selectivity to the material of the isolation region 54 may also be used. Mask 62 may include one or more layers such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, combinations thereof, and the like, and may be formed using any suitable process, such as thermal oxidation, thermal nitridation, ALD, PVD, CVD, combinations thereof, and the like. In the illustrated embodiment, mask 62 comprises an oxide material, such as silicon oxide. In some embodiments, mask 62 may have a thickness between about 20nm and about 70 nm.

Referring to fig. 7A, 7B, and 7C, mask 62 (see fig. 6A and 6B) may be patterned using acceptable photolithography and etching techniques to form patterned mask 72. The pattern of patterned mask 72 is transferred to gate electrode layer 60 by an acceptable etching technique to form gate 70. The pattern of gate 70 covers the respective channel regions of fin 56 while exposing the source/drain regions of fin 56. Gate 70 may also have a length direction that is substantially perpendicular to the length direction of the corresponding fin 56, within process variations. The size of the gates 70 and the spacing between the gates 70 may depend on the area of the die in which the gates 70 are formed. In some embodiments, the gates 70 may have a larger size and larger pitch when located in an input/output region such as a die (e.g., where input/output circuitry is located) than when located in a logic region such as a die (e.g., where logic circuitry is located). As described in more detail below, gate 70 is a sacrificial gate and is subsequently replaced by a replacement gate. Thus, the gate 70 may also be referred to as a sacrificial gate 70.

Referring again to fig. 7A, 7B and 7C, lightly doped source/drain (LDD) regions 75 may be formed in the substrate 50. Similar to the implantation process discussed above with reference to fig. 2A, appropriate impurities are implanted into fin 56 to form LDD regions 75. In some embodiments where the resulting FinFET device is a p-type device, a p-type impurity is implanted into fin 56 to form p-type LDD region 75. In some embodiments where the resulting FinFET device is an n-type device, an n-type impurity is implanted into fin 56 to form n-type LDD region 75. During the implantation of LDD regions 75, gate 70 and patterned mask 72 may be used as masks to prevent (or at least reduce) dopantsImplanted into the channel region of exposed fin 56. Accordingly, LDD regions 75 may be formed substantially in the source/drain regions of exposed fin 56. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The LDD region 75 may have a thickness of between about 10¹⁵cm^-3To about 10¹⁶cm^-3Impurity concentration in between. After the implantation process, an annealing process may be performed to activate the implanted impurities.

Fig. 8A-11C illustrate the formation of spacers 82 on sidewalls of the gate 70 according to some embodiments. Referring first to fig. 8A, 8B and 8C, a dielectric layer 80 is formed on exposed surfaces of sacrificial gate 70, patterned mask 72 and dielectric layer 58. In some embodiments, the dielectric layer 80 may include an oxide, such as aluminum oxide (Al)₂O₃) Etc., and the dielectric layer may be blanket deposited using CVD, ALD, etc. In which the dielectric layer 80 comprises aluminum oxide (Al)₂O₃) In some embodiments, the dielectric layer 80 may be formed using a precursor comprising Trimethylaluminum (TMA) and H₂Mixture of O, Trimethylaluminum (TMA) and O₃/O₂Mixtures of (a) and (b), and the like. In some embodiments, the dielectric layer 80 may be formed at a pressure between about 0.5 torr and about 10 torr and at a temperature between about 25 ℃ and about 350 ℃. In some embodiments, the dielectric layer 80 may have a thickness between about 1nm and about 6 nm.

Referring to fig. 9A, 9B and 9C, a fluorine addition process (fluorination process) is performed on the patterned mask 72 and the exposed portions of the dielectric layer 58 to form fluorinated patterned mask 73 and fluorinated regions 59 in the dielectric layer 58. In some embodiments in which the dielectric layer 58 and the patterned mask 72 are formed of an oxide, such as silicon oxide, the fluorination process may comprise a plasma process, such as a SICONI process. In some embodiments, the SICONI process is performed using a process including NF₃、NH₃A mixture of process gases, combinations thereof, and the like. In some embodiments, the SICONI process can be performed at a temperature of about 90 ℃ and about 120 ℃. In some embodiments, dielectric layer 80 protects dielectric layer 58 and patterned maskMold 72 is protected from being etched during the fluorination process. Thus, in some embodiments, the dielectric layer 80 may be formed of a material that is substantially unetched during the fluorination process, allowing fluorine atoms to be transferred to the underlying layers (e.g., the dielectric layer 58 and the patterned mask 72), and allowing the dielectric layer 58 and the patterned mask 72 to be protected during the fluorination process. In some embodiments, the fluorinated patterned mask 73 may have an atomic fraction of fluorine (atomic fraction) between about 0.03 and about 0.05. In some embodiments, the fluorinated region 59 of the dielectric layer 58 may have an atomic fraction of fluorine between about 0.03 and about 0.05.

Referring to fig. 10A, 10B and 10C, after the above-described fluorination process is completed, the dielectric layer 80 is removed. In some embodiments, dielectric layer 80 may be selectively removed using a suitable etch process. In which the dielectric layer 80 comprises aluminum oxide (Al)₂O₃) In some embodiments, dielectric layer 80 may be removed using a dry etch process, wherein the dry etch process utilizes a composition comprising Cl₂And SiCl₄Mixture of (1), Cl₂And BCl₃Mixture of (1), Cl₂Mixtures with HBr, and the like.

Referring to fig. 11A, 11B, and 11C, spacers 82 are selectively formed on sidewalls of the gate electrode 70. In some embodiments, the spacers 82 may comprise a dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), combinations thereof, and the like, and the spacers 82 may be formed using CVD, ALD, combinations thereof, and the like. In some embodiments, growth of the material of the spacers 82 is inhibited on the fluorinated patterned mask 73 and the exposed surfaces of the fluorinated regions 59 of the dielectric layer 58. Thus, the spacers 82 are selectively formed on the sidewalls of the gate electrode 70. By selectively forming the spacers 82, the anisotropic etching process is omitted, which allows avoiding the formation of possible damage from the anisotropic etching process and provides well-defined nucleation areas for subsequently formed epitaxial source/drain regions. In some embodiments, the spacers 82 may have a width W between about 1nm and about 6nm₂。

Fig. 12A-15C illustrate the formation of spacers 82 on the sidewalls of gate 70 in accordance with an alternative embodiment. Referring first to fig. 12A, 12B and 12C, a dielectric layer 80 is selectively formed on exposed surfaces of the patterned mask 72 and the dielectric layer 58. In some embodiments, the dielectric layer 80 may include an oxide, such as aluminum oxide (Al)₂O₃) Etc., and the dielectric layer may be formed using CVD, ALD, etc. In some embodiments, selective formation of the dielectric layer 80 may be achieved by selecting appropriate precursors for the material of the dielectric layer 80. Wherein the dielectric layer 80 comprises aluminum oxide (Al)₂O₃) In some embodiments, the dielectric layer 80 may be selectively formed using a precursor including Triisobutylaluminum (TiBA), tris (dimethylamino) aluminum, tris (2,2,6, 6-tetramethyl-3, 5-heptanedionato) aluminum, or the like. In some embodiments, the dielectric layer 80 may be formed at a pressure between about 0.5 torr and about 10 torr and a temperature between about 25 ℃ and about 350 ℃. In some embodiments, the dielectric layer 80 may have a thickness between about 1nm and about 6 nm.

Referring to fig. 13A, 13B and 13C, a fluorine addition process (fluorination process) is performed on the patterned mask 72 and the exposed portions of the dielectric layer 58 to form fluorinated patterned mask 73 and fluorinated regions 59 in the dielectric layer 58. In some embodiments in which the dielectric layer 58 and the patterned mask 72 are formed of an oxide, such as silicon oxide, the fluorination process may comprise a plasma process, such as a SICONI process. In some embodiments, the SICONI process is performed using a process including NF₃、NH₃A mixture of process gases, combinations thereof, and the like. In some embodiments, the SICONI process can be performed at a temperature of about 90 ℃ and about 120 ℃. In some embodiments, the dielectric layer 80 protects the dielectric layer 58 and the patterned mask 72 from being etched during the fluorination process. Thus, in some embodiments, the dielectric layer 80 may be formed of a material that is substantially not etched during the fluorination process, allowing fluorine atoms to be transferred to the underlying layers (e.g., the dielectric layer 58 and the patterned mask 72), and allowing the dielectric layer 58 and the patterned mask 72 to be protected during the fluorination process. In some embodiments, fluorinated patterningMask 73 may have an atomic fraction of fluorine between about 0.03 and about 0.05. In some embodiments, the fluorinated region 59 of the dielectric layer 58 may have an atomic fraction of fluorine between about 0.03 and about 0.05.

Referring to fig. 14A, 14B and 14C, after the above-described fluorination process is completed, the dielectric layer 80 is removed. In some embodiments, dielectric layer 80 may be selectively removed using a suitable etch process. In which the dielectric layer 80 comprises aluminum oxide (Al)₂O₃) In some embodiments, dielectric layer 80 may be removed using a dry etch process, wherein the dry etch process utilizes a composition comprising Cl₂And SiCl₄Mixture of (1), Cl₂And BCl₃Mixture of (1), Cl₂Mixtures with HBr, and the like.

Referring to fig. 15A, 15B, and 15C, spacers 82 are selectively formed on sidewalls of the gate electrode 70. In some embodiments, the spacers 82 may comprise a dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), combinations thereof, and the like, and may be formed using CVD, ALD, combinations thereof, and the like. In some embodiments, growth of the material of the spacers 82 is inhibited on the fluorinated patterned mask 73 and the exposed surfaces of the fluorinated regions 59 of the dielectric layer 58. Thus, the spacers 82 are selectively formed on the sidewalls of the gate electrode 70. By selectively forming the spacers 82, the anisotropic etching process is omitted, which allows avoiding possible damage from the anisotropic etching process and provides well-defined nucleation regions for subsequently formed epitaxial source/drain regions. In some embodiments, the spacers 82 may have a width W between about 1nm and about 6nm₂。

Referring to fig. 16A, 16B, and 16C, after spacers 82 are selectively formed on sidewalls of gate 70, a patterning process is performed on fin 56 to form recesses 76 in source/drain regions of fin 56. In some embodiments, the patterning process may include an appropriate anisotropic dry etch process while using the fluorinated patterned mask 73, the gate 70, the spacers 82, and/or the isolation regions 54 as a combinatorial mask. Suitable anisotropic dry etching processes may include Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), combinations thereof, and the like. In some embodiments, the fluorinated regions 59 of the dielectric layer 58 over the isolation regions 54 may be removed during the patterning process.

Referring to fig. 17A, 17B, and 17C, epitaxial source/drain regions 84 are formed in the recesses 76 (see fig. 16A, 16B, and 16C). In some embodiments, epitaxial source/drain regions 84 are epitaxially grown in recesses 76 using metal organic cvd (mocvd), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), Vapor Phase Epitaxy (VPE), Selective Epitaxial Growth (SEG), combinations thereof, and the like. In some embodiments where the resulting FinFET device is an n-type device and fin 56 is formed of silicon, epitaxial source/drain regions 84 may comprise silicon, SiC, SiCP, SiP, or the like. In some embodiments where the resulting FinFET device is a p-type device and fin 56 is formed of silicon, epitaxial source/drain regions 84 may comprise SiGe, SiGeB, Ge, GeSn, or the like. Epitaxial source/drain regions 84 may have surfaces that are raised from respective surfaces of fin 56 and may have facets. In some embodiments, epitaxial source/drain regions 84 may extend through fin 56 and into semiconductor strip 52. In some embodiments, the material of epitaxial source/drain regions 84 may be implanted with a suitable dopant. In some embodiments, the implantation process is similar to the process of forming LDD regions 75 described above with reference to fig. 7A, 7B, and 7C, and for the sake of brevity, a description is not repeated here. In other embodiments, the material of epitaxial source/drain regions 84 may be doped in-situ during growth.

With further reference to fig. 17A, 17B, and 17C, in the illustrated embodiment, each of the epitaxial source/drain regions 84 is physically separated from the other epitaxial source/drain regions 84. In other embodiments, adjacent epitaxial source/drain regions 84 may merge. Such an embodiment is depicted in fig. 22A, 22B, and 22C, where adjacent epitaxial source/drain regions 84 merge to form a common epitaxial source/drain region 84.

Referring to fig. 18A, 18B and 18C, an etch stop layer 87 and an interlayer dielectric (ILD)88 are deposited over the gate 70 and over the epitaxial source/drain regions 84. In one embodiment, ILD 88 is a flowable film formed by flowable CVD. In some embodiments, ILD 88 is formed of a dielectric material such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), Undoped Silicate Glass (USG), or the like, and ILD 88 may be deposited by any suitable method such as CVD, PECVD, spin-on-glass processes, combinations thereof, or the like. In some embodiments, etch stop layer 87 is used as a stop layer while ILD 88 is patterned to form openings for subsequently formed contacts. Accordingly, the material for etch stop layer 87 may be selected such that the material of etch stop layer 87 has a lower etch rate than the material of ILD 88. In some embodiments, a planarization process such as CMP may be performed to make the top surface of ILD 88 flush with the top surface of gate 70. In some embodiments, the planarization process also removes the fluorinated patterned mask 73.

Referring to fig. 19A, 19B and 19C, gate 70 (see fig. 18A, 18B and 18C) is removed to form a recess 90 in ILD 88. In some embodiments, one or more suitable etch processes may be used to remove gate 70. Each of recesses 90 exposes a channel region of a respective fin 56. In some embodiments, the dielectric layer 58 may serve as an etch stop when the gate 70 is etched. In some embodiments, after the gate electrode layer 60 of the gate 70 is removed, the exposed portions of the dielectric layer 58 may also be removed. In some embodiments, the exposed portion of the dielectric layer 58 may remain in the recess 90.

Referring to fig. 20A, 20B, and 20C, a gate dielectric layer 92 and a gate electrode layer 94 are formed in the groove 90 (see fig. 19A, 19B, and 19C). In some embodiments, a gate dielectric layer 92 is conformally deposited in the recess 90. In some embodiments, gate dielectric layer 92 comprises silicon oxide, silicon nitride, or multilayers thereof. In other embodiments, gate dielectric layer 92 comprises a high-k dielectric material, and in these embodiments, gate dielectric layer 92 may have a k value greater than about 7.0, and may comprise a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The method of forming the gate dielectric layer 92 may include Molecular Beam Deposition (MBD), ALD, PECVD, combinations thereof, and the like. In some embodiments, gate dielectric layer 92 may have a thickness between about 0.5nm and about 4 nm.

With further reference to fig. 20A, 20B, and 20C, in some embodiments in which the portion of dielectric layer 58 over the channel region of fin 56 is not removed, the portion of dielectric layer 58 over the channel region of fin 56 may act as an interfacial layer between gate dielectric layer 92 and the channel region of fin 56. In some embodiments in which the portion of dielectric layer 58 over the channel region of fin 56 is removed, an interfacial layer may be formed over the channel region of fin 56 and gate dielectric layer 92 formed over the interfacial layer prior to forming gate dielectric layer 92. The interfacial layer helps to act as a buffer for the subsequently formed high-k dielectric layer and the underlying semiconductor material. In some embodiments, the interfacial layer comprises a chemical silicon oxide that may be formed by a chemical reaction. For example, deionized water + ozone (O) may be used₃)、NH₄OH+H₂O₂+H₂O (apm) or other methods to form chemical oxides. Other embodiments may utilize different materials or processes (e.g., thermal oxidation or deposition processes) that form the interfacial layer. In some embodiments, the interfacial layer may have a thickness between about 0.5nm and about 2 nm.

Next, a gate electrode layer 94 is deposited over the gate dielectric layer 92 and fills the remainder of the recess 90 (see fig. 19A, 19B, and 19C). In some embodiments, gate electrode layer 94 may include one or more layers of a suitable conductive material. Gate electrode layer 94 can include a metal selected from the group of W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Co, Pd, Ni, Re, Ir, Ru, Pt, Zr, and combinations thereof. In some embodiments, gate electrode layer 94 may include a metal selected from the group of TiN, WN, TaN, Ru, and combinations thereof. Metal alloys such as Ti-Al, Ru-Ta, Ru-Zr, Pt-Ti, Co-Ni, and Ni-Ta and/or alloys such as WN may be used_x、TiN_x、MoN_x、TaN_xAnd TaSi_xN_yThe metal nitride of (2). Such as ALD, CVD, PVD, plating, their, can be usedGate electrode layer 94 is formed by a suitable process such as combination. In some embodiments, gate electrode layer 94 may have a thickness between about 0.5nm and about 6 nm. After filling recess 90 with gate electrode layer 94, a planarization process such as CMP may be performed to remove excess portions of gate dielectric layer 92 and gate electrode layer 94 that are above the top surface of ILD 88. The resulting remaining portions of the materials of gate electrode layer 94 and gate dielectric layer 92 thus form the replacement gate 96 of the resulting FinFET device. In other embodiments, gate 70 may be left instead of replaced by replacement gate 96.

Referring to fig. 21A, 21B, and 21C, ILD 102 is deposited over ILD 88, contact 104 is formed through ILD 102 and ILD 88, and contact 108 is formed through ILD 102. In one embodiment, ILD 102 is formed using materials and methods similar to ILD 88 described above with reference to fig. 18A, 18B, and 18C, and for the sake of brevity, the description is not repeated here. In some embodiments, ILD 102 and ILD 88 are formed of the same material. In other embodiments, ILD 102 and ILD 88 are formed of different materials.

With further reference to fig. 21A, 21B, and 21C, an opening for contact 104 is formed through ILD 88 and ILD 102, and etch stop layer 87, and an opening for contact 108 is formed through ILD 102 and etch stop layer 87. These openings may all be formed simultaneously in the same process or in separate processes. The openings may be formed using acceptable photolithography and etching techniques. In some embodiments, a liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the opening. The liner may comprise titanium, titanium nitride, tantalum nitride, combinations thereof, and the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, aluminum, nickel, combinations thereof, or the like. A planarization process, such as CMP, may be performed to remove excess material from the top surface of ILD 102. The remaining pads and conductive

material form contacts

104 and 108. An annealing process may be performed to form a silicide (not shown) at the interface between the epitaxial source/drain regions 84 and the respective contacts 104. Contact 104 is physically and electrically coupled to epitaxial source/drain region 84, and contact 108 is physically and electrically coupled to replacement gate 96. Although the contacts 104 are shown in fig. 21B in the same cross-section as the contacts 108, this figure is for illustration purposes only, and in some embodiments, the contacts 104 may be disposed in a different cross-section than the contacts 108.

Fig. 22A, 22B, and 22C illustrate cross-sectional views of FinFET devices similar to those shown in fig. 21A, 21B, and 21C, where like elements are labeled with like reference numerals. In some embodiments, the FinFET device of fig. 22A, 22B, and 22C may be formed using similar materials and methods and FinFET devices of fig. 21A, 21B, and 21C as described above with reference to fig. 2A-21C, and for brevity, this description is not repeated here. In the illustrated embodiment, adjacent epitaxial source/drain regions 84 merge to form a common epitaxial source/drain region 84. In some embodiments, a void (not shown) may be formed below the common epitaxial source/drain region 84 and between the common epitaxial source/drain region 84 and the isolation region 54. In some embodiments, the voids are filled with the material of ILD 88. In the illustrated embodiment, the common epitaxial source/drain regions 84 have a planar top surface. In other embodiments, the common epitaxial source/drain regions 84 may have a non-planar top surface.

Fig. 23 is a flow chart illustrating a method 230 of forming a FinFET device, according to some embodiments. The method 230 begins at step 231, where a substrate (e.g., the substrate 50 shown in fig. 2A) is patterned to form a fin (e.g., the fin 56 shown in fig. 5A) as described above with reference to fig. 2A-5A. In step 232, a sacrificial gate stack (e.g., gate 70 shown in fig. 7A and 7B) is formed over the fin as described above with reference to fig. 6A, 6B, and 7A-7C. In step 233, spacers (e.g., spacers 82 shown in fig. 11B or 15B) are selectively formed on sidewalls of the sacrificial gate stack, as described above with reference to fig. 8A-11C or 12A-15C. In step 234, the fin is patterned using the sacrificial gate stack and the spacers as a combinatorial mask to form a recess (e.g., recess 76 shown in fig. 16B and 16C) in the fin, as described above with reference to fig. 16A-16C. In step 235, source/drain regions (e.g., epitaxial source/drain regions 84 shown in fig. 17B and 17C) are epitaxially grown in the recesses as described above with reference to fig. 17A-17C. In step 236, a replacement gate stack (e.g., replacement gate 96 shown in fig. 20A and 20B) is formed over the fin as described above with reference to fig. 18A-20C.

Various embodiments discussed herein allow for the selective formation of gate spacers on the sidewalls of the gate, the formation of well-defined nucleation regions for epitaxial source/drain regions, the formation of uniform epitaxial source/drain regions, the enlargement of process windows, precise process control and simplified process integration.

According to one embodiment, a method comprises: forming a fin extending over the isolation region; forming a sacrificial gate over the fin; selectively depositing a first dielectric material on sidewalls of the sacrificial gate to form spacers on the sidewalls of the sacrificial gate, wherein the first dielectric material is not deposited over a top surface of the sacrificial gate; patterning the fin using the sacrificial gate and the spacer as a combinatorial mask to form a recess in the fin; and forming epitaxial source/drain regions in the recesses. In one embodiment, forming a sacrificial gate over the fin includes: forming a gate electrode layer over the fin; forming a patterned mask over the gate electrode layer; and transferring the pattern of the patterned mask to the gate electrode layer. In one embodiment, the method further comprises performing a fluorination process on the patterned mask prior to selectively depositing the first dielectric material on the sidewalls of the sacrificial gate. In one embodiment, the method further comprises forming a second dielectric material on the sidewalls and top surface of the patterned mask prior to performing the fluorination process on the patterned mask. In one embodiment, the method further comprises removing the second dielectric material after performing a fluorination process on the patterned mask. In one embodiment, forming a second dielectric material on the sidewalls and top surface of the patterned mask further comprises forming a second dielectric material on the sidewalls of the sacrificial gate. In one embodiment, forming the second dielectric material on the sidewalls and the top surface of the patterned mask includes selectively depositing the second dielectric material on the sidewalls and the top surface of the patterned mask.

In an embodiment, forming the sacrificial gate over the fin comprises: forming a gate electrode layer over the fin; forming a patterned mask over the gate electrode layer; and transferring a pattern of the patterned mask to the gate electrode layer.

In an embodiment, the method for forming a semiconductor device further comprises: a fluorination process is performed on the patterned mask prior to selectively depositing the first dielectric material on the sidewalls of the sacrificial gate.

In an embodiment, the method for forming a semiconductor device further comprises: a second dielectric material is formed on sidewalls and a top surface of the patterned mask prior to performing the fluorination process on the patterned mask.

In an embodiment, the method for forming a semiconductor device further comprises: removing the second dielectric material after performing the fluorination process on the patterned mask.

In an embodiment, forming the second dielectric material on the sidewalls and top surface of the patterned mask further comprises forming the second dielectric material on the sidewalls of the sacrificial gate.

In an embodiment, forming the second dielectric material on the sidewalls and the top surface of the patterned mask comprises selectively depositing the second dielectric material on the sidewalls and the top surface of the patterned mask.

According to another embodiment, a method comprises: recessing the isolation region to expose sidewalls of the semiconductor fin; forming a gate electrode layer over the semiconductor fin; forming a patterned mask over the gate electrode layer; removing portions of the gate electrode layer exposed by the patterned mask to form a sacrificial gate over the semiconductor fin; performing a fluorination process on the patterned mask to form a fluorinated patterned mask; selectively depositing a first dielectric material on sidewalls of the sacrificial gate to form spacers on the sidewalls of the sacrificial gate; etching the semiconductor fin using the fluorinated patterned mask, the sacrificial gate, and the spacer as a combinatorial mask to form a recess in the semiconductor fin; and depositing a semiconductor material in the recess. In thatIn one embodiment, the method further comprises forming a second dielectric material on the sidewalls and top surface of the patterned mask prior to performing the fluorination process on the patterned mask. In one embodiment, the second dielectric material comprises aluminum oxide. In one embodiment, the method further comprises: a third dielectric material is formed over the semiconductor fin before forming the gate electrode layer over the semiconductor fin. In one embodiment, the method further comprises: forming a second dielectric material over the exposed portion of the third dielectric material after forming the sacrificial gate over the semiconductor fin; and performing a fluorination process on the exposed portion of the third dielectric material. In one embodiment, the patterned mask includes an oxide material. In one embodiment, performing the fluorination process comprises using a composition comprising NF₃The plasma process is performed with a mixture of process gases.

In an embodiment, the second dielectric material comprises aluminum oxide.

In an embodiment, the method for forming a semiconductor device further comprises: forming a third dielectric material over the semiconductor fin before forming the gate electrode layer over the semiconductor fin.

In an embodiment, the method for forming a semiconductor device further comprises: forming the second dielectric material over exposed portions of the third dielectric material after forming the sacrificial gate over the semiconductor fin; and performing the fluorination process on the exposed portion of the third dielectric material.

In an embodiment, the patterned mask comprises an oxide material.

In an embodiment, performing the fluorination process comprises using a composition comprising NF₃The plasma process is performed with a mixture of process gases.

According to yet another embodiment, a method comprises: etching the isolation region to expose sidewalls of the semiconductor fin; in a semiconductorForming a first oxide material on sidewalls and a top surface of the fin; forming a conductive material over the first oxide material; forming a second oxide material over the conductive material; etching the second oxide material to form a patterned second oxide material; etching the conductive material using the patterned second oxide material as a mask to form a sacrificial gate over the semiconductor fin; forming a first dielectric material on sidewalls and a top surface of the patterned second oxide material and over exposed portions of the first oxide material; performing a fluorination process on the patterned second oxide material and the exposed portion of the first oxide material, the fluorination process forming a fluorinated patterned second oxide material; removing the first dielectric material; selectively depositing a second dielectric material on sidewalls of the sacrificial gate; etching the semiconductor fin using the fluorinated patterned second oxide material, the sacrificial gate, and the second dielectric material as a combinatorial mask to form a recess in the semiconductor fin; and epitaxially growing a semiconductor material in the recess. In one embodiment, the method further comprises, prior to performing the fluorination process, forming a first dielectric material on sidewalls of the sacrificial gate. In one embodiment, the method further comprises replacing the sacrificial gate with a replacement gate. In one embodiment, performing the fluorination process comprises using a composition comprising NF₃And NH₃The plasma process is performed with a mixture of process gases. In one embodiment, removing the first dielectric material includes etching the first dielectric material. In one embodiment, the fluorination process does not substantially etch the first dielectric material.

In an embodiment, the method for forming a semiconductor device further comprises: forming the first dielectric material on sidewalls of the sacrificial gate prior to performing the fluorination process.

In an embodiment, the method for forming a semiconductor device further comprises: the sacrificial gate is replaced with a replacement gate.

In an embodiment, performing the fluorination process comprises using a composition comprising NF₃And NH₃The plasma process is performed with a mixture of process gases.

In an embodiment, removing the first dielectric material comprises etching the first dielectric material.

In an embodiment, the fluorination process does not etch the first dielectric material.

The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine lithographic and self-aligned processes, allowing the created patterns to have pitches that are smaller than those otherwise obtainable using a single direct lithographic process, for example. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed along sidewalls of the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the fin may then be patterned using the remaining spacers.

The foregoing has discussed features of several embodiments so that those skilled in the art may better understand the various aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising:

forming a fin extending over an isolation region and a dielectric layer over the fin;

forming a sacrificial gate comprising a gate electrode layer formed over the dielectric layer;

selectively depositing a first dielectric material on sidewalls of the sacrificial gate to form spacers on the sidewalls of the sacrificial gate, wherein the first dielectric material is not deposited over a top surface of the sacrificial gate;

patterning the fin using the sacrificial gate and the spacer as a combinatorial mask to form a recess in the fin; and

epitaxial source/drain regions are formed in the recesses,

performing a fluorination process on a patterned mask over the sacrificial gate and on the dielectric layer not covered by the sacrificial gate prior to the depositing the first dielectric material.

2. The method for forming a semiconductor device of claim 1, wherein forming the sacrificial gate over the fin comprises:

forming a gate electrode layer over the fin;

forming a patterned mask over the gate electrode layer; and

transferring a pattern of the patterned mask to the gate electrode layer.

3. The method for forming a semiconductor device according to claim 2, the spacer having a width between 1nm and 6 nm.

4. The method for forming a semiconductor device according to claim 3, further comprising:

a second dielectric material is formed on sidewalls and a top surface of the patterned mask prior to performing the fluorination process on the patterned mask.

5. The method for forming a semiconductor device according to claim 4, further comprising:

removing the second dielectric material after performing the fluorination process on the patterned mask.

6. The method of claim 4, wherein forming the second dielectric material on the sidewalls and top surface of the patterned mask further comprises forming the second dielectric material on sidewalls of the sacrificial gate.

7. The method of claim 4, wherein forming the second dielectric material on the sidewalls and top surface of the patterned mask comprises selectively depositing the second dielectric material on the sidewalls and top surface of the patterned mask.

8. A method for forming a semiconductor device, comprising:

recessing the isolation region to expose sidewalls of the semiconductor fin;

forming a dielectric layer over the semiconductor fin and a gate electrode layer over the dielectric layer;

forming a patterned mask over the gate electrode layer;

removing portions of the gate electrode layer exposed by the patterned mask to form a sacrificial gate over the semiconductor fin, the sacrificial gate including the dielectric layer under the gate electrode layer;

performing a fluorination process on the patterned mask to form a fluorinated patterned mask and on the dielectric layer not covered by the sacrificial gate;

selectively depositing a first dielectric material on sidewalls of the sacrificial gate to form spacers on the sidewalls of the sacrificial gate;

etching the semiconductor fin using the fluorinated patterned mask, the sacrificial gate, and the spacer as a combinatorial mask to form a recess in the semiconductor fin; and

depositing a semiconductor material in the recess.

9. The method for forming a semiconductor device according to claim 8, further comprising:

10. The method for forming a semiconductor device according to claim 9, wherein the second dielectric material comprises aluminum oxide.

11. The method for forming a semiconductor device according to claim 9, the spacer having a width between 1nm and 6 nm.

12. The method for forming a semiconductor device according to claim 9, further comprising:

after forming the sacrificial gate over the semiconductor fin, forming the second dielectric material over exposed portions of the dielectric layer.

13. The method of forming a semiconductor device of claim 8, wherein the patterned mask comprises an oxide material.

14. The method of claim 8, wherein performing the fluorination process comprises using a composition comprising NF₃The plasma process is performed with a mixture of process gases.

15. A method for forming a semiconductor device, comprising:

etching the isolation region to expose sidewalls of the semiconductor fin;

forming a first oxide material on sidewalls and a top surface of the semiconductor fin;

forming a conductive material over the first oxide material;

forming a second oxide material over the conductive material;

etching the second oxide material to form a patterned second oxide material;

etching the conductive material using the patterned second oxide material as a mask to form a sacrificial gate over the semiconductor fin;

forming a first dielectric material on sidewalls and a top surface of the patterned second oxide material and over exposed portions of the first oxide material;

performing a fluorination process on the patterned second oxide material and the exposed portions of the first oxide material, the fluorination process forming a fluorinated patterned second oxide material;

removing the first dielectric material;

selectively depositing a second dielectric material on sidewalls of the sacrificial gate;

etching the semiconductor fin using the fluorinated patterned second oxide material, the sacrificial gate, and the second dielectric material as a combinatorial mask to form a recess in the semiconductor fin; and

and epitaxially growing a semiconductor material in the groove.

16. The method for forming a semiconductor device according to claim 15, further comprising:

forming the first dielectric material on sidewalls of the sacrificial gate prior to performing the fluorination process.

17. The method for forming a semiconductor device according to claim 15, further comprising:

the sacrificial gate is replaced with a replacement gate.

18. The method of claim 15, wherein performing the fluorination process comprises using a composition comprising NF₃And NH₃The plasma process is performed with a mixture of process gases.

19. The method for forming a semiconductor device according to claim 15, wherein removing the first dielectric material comprises etching the first dielectric material.

20. The method for forming a semiconductor device according to claim 15, wherein the fluorination process does not etch the first dielectric material.