CN109300994B - Pseudo negative resistance type low residual voltage TVS device and preparation method thereof - Google Patents
Pseudo negative resistance type low residual voltage TVS device and preparation method thereof Download PDFInfo
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- 230000002457 bidirectional effect Effects 0.000 claims description 3
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
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Abstract
The invention discloses a pseudo negative resistance type low residual voltage TVS device and a preparation method thereof, and is characterized by comprising a thin sheet negative resistance process and an irradiation modification process. The TVS device is in the protection thunderbolt surge, and lower residual voltage is favorable to better protection later stage circuit. A high surge capacity is advantageous for adapting to higher surge level requirements. And the negative resistance stability point cannot be lower than the operating voltage (for power ports, if lower than the operating voltage, the loop voltage will flow back into the TVS device). The invention combines the P-type sheet negative resistance process and the irradiation modification process, and realizes controllable negative resistance stable point voltage while reducing residual voltage and improving surge capacity.
Description
Technical Field
The invention relates to the technical field of microelectronics, in particular to a pseudo-negative resistance type low-residual voltage TVS device with low residual voltage, controllable negative resistance stable point and high surge and a preparation method thereof.
Background
The transient voltage suppression diode (Transient Voltage Suppressor), TVS for short, is a high-efficiency electrostatic surge protection device and plays an important role in protection in a circuit. With the continuous application of handheld devices, electrostatic protection devices are widely used. Strong surge capability, low residual voltage is the direction of device optimization.
The improvement of the surge capacity can effectively protect the device from being damaged when the device is disturbed by a harsher surge. The low residual voltage can better eliminate the influence on the rear-stage circuit when the surge passes, and prevent the rear-stage circuit from being damaged after being influenced by the residual voltage. The current industry generally uses P substrates to make devices into NPN bi-directional structures. The P region is narrower in width and less than the electron diffusion length. When a surge occurs, a negative resistance effect is generated due to injection of a large current.
The negative resistance effect can effectively reduce residual voltage. And according to the theory of semiconductor thermal burn-out, the larger the surge current can pass under the condition of negative resistance. From the surge capacity and residual voltage angles, the stronger the negative resistance characteristic, the better the surge capacity and the lower the residual voltage. When the negative resistance device is used at a power supply port, the negative resistance stability point is lower than the power supply voltage. Causing the supply port voltage to reverse flow into the TVS protection device. This pulls down the supply voltage and energy is loaded on the TVS device resulting in device damage. Therefore, in practical application, on the premise of low residual voltage requirement, the negative resistance stability point is higher than the working voltage of the power supply port. The conventional TVS cannot meet the requirements due to too high residual voltage, and the negative resistance device cannot meet the practical application requirements due to too low negative resistance stability point under low peak residual voltage. The invention combines the P-type sheet negative resistance process and the irradiation modification process, and can meet the requirement of low peak residual voltage and simultaneously meet the requirement of controllable negative resistance stabilization point.
Disclosure of Invention
The invention aims to provide a low residual voltage, a controllable negative resistance stable point, a high-surge bidirectional transient suppression diode device and a manufacturing method thereof.
In order to meet the requirements, the invention adopts the following technical scheme:
a preparation method of a pseudo negative resistance type low residual voltage TVS device comprises the following process steps:
feeding and blanking, namely selecting a polishing sheet with proper resistivity according to voltage, and enabling a <111> crystal orientation and a P-type substrate to be subjected to a cleaning process in order to ensure surface cleaning;
the thinning process is that the original substrate is thinned by adopting a CMP or sand blowing process, the thickness is reduced to 30-250 μm, and the thickness value is about 180 μm. In order to ensure the surface cleaning, a cleaning process is required;
a junction making process, wherein the substrate is subjected to a junction making process, wherein the junction making process can generally use a coating process, a paper source diffusion process, a POCL3 pre-deposition process, an injection process and the like, and then a junction pushing annealing is performed to enable the pressure resistance and the junction depth to reach design values;
an oxidation process, wherein an isolation layer is formed by oxidation, which can be applied to a mesa process and a plane process;
photoetching, developing and etching processes, namely copying a designated pattern on a silicon wafer through photoetching and developing, and etching to complete groove corrosion;
glass passivation corrosion is performed to form a window, protection of a PN junction interface of the groove is completed through a glass coating process and a glass sintering process, and then contact surfaces are passivated and removed through photoetching;
the irradiation and annealing process, the product is subjected to an irradiation process, the dosage of which is between 0.001KGy and 1KKGy, including but not limited to electron irradiation, nuclear irradiation and other irradiation processes capable of reducing minority carrier lifetime of the semiconductor device, and then is annealed, and nitrogen-hydrogen annealing, nitrogen annealing or vacuum annealing is used to stabilize the irradiation and improve interface state, and then is cleaned;
surface metal preparation, using evaporation, sputtering or liquid metallization. And then ohmic contact is formed through high-temperature annealing.
The invention focuses on adopting a sheet negative resistance process and an irradiation modification process.
The TVS device is a device with a functional structure doped with NPN type and capable of realizing bidirectional surge protection.
The pseudo negative resistance TVS device adopts the P-type polishing sheet to carry out sheet flowing and deep junction technology to form a negative resistance effect structure. Then using irradiation modification, introducing into the composite center through electron irradiation with a certain dosage. The introduction of the composite center can effectively reduce minority carrier lifetime and reduce the amplification factor of an NPN device, so that the device is restored to approximate non-negative resistance characteristics. When a surge occurs, under the effect of large current injection. The low series resistance of the device results in lower device residual voltage due to the short base distance. However, the minority carrier lifetime is reduced, and the negative resistance effect is not obvious, so that the negative resistance stability point of the device is high. Ensuring not lower than the power supply voltage and ensuring no abnormality in application.
The low residual voltage is realized by a sheet negative resistance process. The high surge is achieved by reducing the residual voltage. The negative resistance stability point is high and controllable, and is realized by irradiation modification, chip thickness junction depth and other coordination adjustment.
The negative resistance stabilization point refers to the average voltage value of the stabilization section when the surge waveform of the negative resistance device generates negative resistance effect when the negative resistance device is impacted by the surge.
The pseudo negative resistance means that the chip has an insignificant negative resistance effect before irradiation when surge or large current passes.
Drawings
FIG. 1 is a schematic diagram of a negative resistance stability point.
Fig. 2 is a schematic cross-sectional view of a substrate thinning chip process.
Fig. 3 is a schematic cross-sectional view of the chip after glass passivation.
Fig. 4 is a schematic cross-sectional view of a post-metal chip.
FIG. 5 is a schematic diagram of a graphical representation of a non-negative resistance chip.
FIG. 6 is a schematic diagram of a graphical representation of a negative resistance chip.
Fig. 7 is a schematic diagram of a pseudo negative resistance chip.
FIG. 8 is a schematic diagram of an oscilloscope showing a surge curve of a non-negative resistance chip.
Fig. 9 is a schematic diagram of an oscilloscope showing a negative resistance chip surge curve.
Fig. 10 is a schematic diagram of an oscilloscope showing a pseudo negative resistance chip surge curve.
Fig. 11 is a schematic diagram showing three chip surge curves versus an oscilloscope.
Detailed Description
The following description of the preferred embodiments of the present invention is given with reference to the accompanying drawings, so as to explain the technical scheme of the present invention in detail.
The specific embodiment will be described by taking a 20V bi-directional mesa process pseudo-negative resistance type low residual voltage TVS device as an example.
And feeding and discharging, wherein the resistivity is 0.039Ω & cm, and the p-type substrate feeding and discharging is <111 >. And then subjected to an HF cleaning process.
And thinning the original substrate. And thinning to 140 mu m by adopting a sand blowing process. And then subjected to an HF cleaning process. The thinning process pair is shown in fig. 2.
And (3) a junction manufacturing process, a POCL3 pre-deposition process and a push junction annealing process. Annealing conditions were 1200 ℃ for 30 hours.
And an oxidation process, wherein an oxidation layer is grown for 70 minutes at 1050 ℃ and a dry oxygen humidifying method is adopted.
Photolithography, development and etching processes, in which a specified pattern is reproduced on a silicon wafer by photolithography and development. The trench etch is completed by etching. And (3) opening a window by glass passivation and corrosion, and finishing the protection of the PN junction interface of the groove through a glass coating process and a glass sintering process. And then the contact surface is passivated and removed by photoetching. The longitudinal cross-sectional structure after passivation is shown in fig. 3.
And the irradiation and annealing process adopts electron irradiation of 500Gy for metering irradiation. And then adopting vacuum annealing to stabilize and recover the irradiation defect.
The electrode preparation uses a titanium nickel silver structure. Then N-H annealing at 450 ℃ is adopted. The chip cross section is shown in fig. 4.
And after the chip sample preparation is finished, packaging by using a traditional SMB (surface mount technology) process. And comparing the I-V curve of the traditional 20V non-negative resistance product, the pseudo negative resistance product and the negative resistance product. Fig. 5 is a schematic diagram of a graph showing a non-negative resistance chip, fig. 6 is a schematic diagram of a graph showing a negative resistance chip, and fig. 7 is a schematic diagram of a graph showing a pseudo-negative resistance chip. The negative resistance chip has obvious negative resistance phenomenon on the graphic instrument, but the curves of the non-negative resistance and the pseudo-negative resistance products are similar, and the obvious negative resistance phenomenon is not seen.
And 8-20 surge waveform comparison is carried out on the traditional 20V non-negative resistance product, the pseudo negative resistance product and the negative resistance product. FIG. 8 is a schematic diagram of an oscilloscope showing a surge curve of a non-negative resistance chip. Fig. 9 is a schematic diagram of an oscilloscope showing a negative resistance chip surge curve. Fig. 10 is a schematic diagram of an oscilloscope showing a pseudo negative resistance chip surge curve. Fig. 11 is a schematic diagram showing three chip surge curves versus an oscilloscope. As can be seen from the results, the residual voltage of the non-negative resistance product is very high around 40V, and the high residual voltage can cause damage to the subsequent circuit. The peak value of the residual voltage of the negative resistance product is about 32V, but the stable point of the residual voltage negative resistance is too low, about 18V. This causes the supply voltage to pull down when used at the 20V supply port. The anti-surge device is damaged in advance, and the whole machine is restarted in a short time due to the excessively low voltage.
The surge protection device prepared by the invention is used for a semiconductor device for surge protection and static protection, and the working voltage range of the surge protection device is between 3V and 100V.
Claims (3)
1. The preparation method of the pseudo negative resistance type low residual voltage TVS device is characterized by comprising the following steps of:
selecting a P-type substrate, and carrying out thinning process until the thickness is 30-250 mu m;
a junction making process is adopted to form an NPN structure;
the dosage used in the irradiation modification process is between 0.001KGy and 1 KKGy;
preparing surface metal to form ohmic contact;
the TVS device is a device with a functional structure doped with NPN type and capable of realizing bidirectional surge protection;
a pseudo negative resistance type low residual voltage TVS device adopts a deep junction technology to form a negative resistance effect structure; then using irradiation modification, introducing into the composite center through irradiation of a certain dose.
2. The method for manufacturing a pseudo negative resistance type low residual voltage TVS device according to claim 1, wherein said irradiation modification process comprises an electron irradiation process and a nuclear irradiation process to reduce minority carrier lifetime of the semiconductor device.
3. A pseudo-negative resistance low residual voltage TVS device, prepared according to the method of any one of claims 1-2.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0497290A2 (en) * | 1991-01-28 | 1992-08-05 | Kabushiki Kaisha Toshiba | Switching semiconductor device and method of manufacturing the same |
| US5343065A (en) * | 1991-12-02 | 1994-08-30 | Sankosha Corporation | Method of controlling surge protection device hold current |
| CN102769026A (en) * | 2011-05-06 | 2012-11-07 | 江苏锦丰电子有限公司 | Low-capacitance high-speed transmission semiconductor surge protection device |
| JP2013069989A (en) * | 2011-09-26 | 2013-04-18 | Toshiba Corp | Semiconductor device |
| CN103956324A (en) * | 2014-04-30 | 2014-07-30 | 天津中环半导体股份有限公司 | Production technology for transient voltage suppressor chip with channeling effect |
| CN108428697A (en) * | 2017-11-09 | 2018-08-21 | 上海长园维安微电子有限公司 | A kind of low-capacitance bidirectional band negative resistance TVS device |
-
2018
- 2018-09-27 CN CN201811130910.6A patent/CN109300994B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0497290A2 (en) * | 1991-01-28 | 1992-08-05 | Kabushiki Kaisha Toshiba | Switching semiconductor device and method of manufacturing the same |
| US5343065A (en) * | 1991-12-02 | 1994-08-30 | Sankosha Corporation | Method of controlling surge protection device hold current |
| CN102769026A (en) * | 2011-05-06 | 2012-11-07 | 江苏锦丰电子有限公司 | Low-capacitance high-speed transmission semiconductor surge protection device |
| JP2013069989A (en) * | 2011-09-26 | 2013-04-18 | Toshiba Corp | Semiconductor device |
| CN103956324A (en) * | 2014-04-30 | 2014-07-30 | 天津中环半导体股份有限公司 | Production technology for transient voltage suppressor chip with channeling effect |
| CN108428697A (en) * | 2017-11-09 | 2018-08-21 | 上海长园维安微电子有限公司 | A kind of low-capacitance bidirectional band negative resistance TVS device |
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