CN109300994B - 一种伪负阻型低残压tvs器件及其制备方法 - Google Patents
一种伪负阻型低残压tvs器件及其制备方法 Download PDFInfo
- Publication number
- CN109300994B CN109300994B CN201811130910.6A CN201811130910A CN109300994B CN 109300994 B CN109300994 B CN 109300994B CN 201811130910 A CN201811130910 A CN 201811130910A CN 109300994 B CN109300994 B CN 109300994B
- Authority
- CN
- China
- Prior art keywords
- negative resistance
- residual voltage
- tvs device
- irradiation
- low residual
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 47
- 238000012986 modification Methods 0.000 claims abstract description 9
- 230000004048 modification Effects 0.000 claims abstract description 9
- 230000000694 effects Effects 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000002457 bidirectional effect Effects 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 230000002349 favourable effect Effects 0.000 abstract 1
- APTZNLHMIGJTEW-UHFFFAOYSA-N pyraflufen-ethyl Chemical compound C1=C(Cl)C(OCC(=O)OCC)=CC(C=2C(=C(OC(F)F)N(C)N=2)Cl)=C1F APTZNLHMIGJTEW-UHFFFAOYSA-N 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 15
- 238000000137 annealing Methods 0.000 description 11
- 239000011521 glass Substances 0.000 description 7
- 238000004140 cleaning Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 238000000576 coating method Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000006641 stabilisation Effects 0.000 description 3
- 238000011105 stabilization Methods 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000007664 blowing Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000004576 sand Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 208000033999 Device damage Diseases 0.000 description 1
- 206010053615 Thermal burn Diseases 0.000 description 1
- QQMBHAVGDGCSGY-UHFFFAOYSA-N [Ti].[Ni].[Ag] Chemical group [Ti].[Ni].[Ag] QQMBHAVGDGCSGY-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Emergency Protection Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
本发明公开了一种伪负阻型低残压TVS器件及其制备方法,其特征在于,包括采用薄片负阻工艺与辐照改性工艺。TVS器件在防护雷击浪涌时,较低的残压有利于更好的保护后级电路。高的浪涌能力有利于适用更高浪涌等级要求。且负阻稳定点不能低于工作电压(针对于电源口,如低于工作电压会造成回路电压倒灌入TVS器件)。本发明使用P型薄片负阻工艺和辐照改性工艺相结合,在降低残压、提高浪涌能力的同时实现负阻稳定点电压可控。
Description
技术领域
本发明涉及微电子技术领域,具体涉及到一种低残压、负阻稳定点可控、高浪涌的伪负阻型低残压TVS器件及其制备方法。
背景技术
瞬态电压抑制二极管(Transient Voltage Suppressor),简称TVS,是一种高效能的静电浪涌保护器件,在电路中起到重要的保护作用。随着手持设备的不断应用,静电保护器件得到广泛应用。强的浪涌能力,低的残压是器件优化的方向。
提高浪涌能力可以有效保护器件在受到更恶劣的浪涌干扰时保证防护器件不被损坏。低的残压可以更好的消除浪涌通过时对后级电路的影响,防止后端电路受到残压影响后损坏。目前行业通常使用的做法是使用P衬底把器件做成NPN双向结构。此P区域宽度较窄,小于电子扩散长度。当浪涌发生时由于大电流的注入,会产生负阻效应。
负阻效应可以有效降低残压。且根据半导体热烧毁理论,在存在负阻情况下,可以通过的浪涌电流就越大。从浪涌能力和残压角度分析,负阻特性越强浪涌能力越优且残压越低。负阻器件使用在电源口时会因为负阻稳定点较低,低于电源电压。导致电源口电压反流入TVS防护器件。这样会拉低电源电压,且能量会加载在TVS器件上导致器件损坏。故实际应用中在残压要求残压低的前提下,还需要负阻稳定点高于电源口工作电压。传统TVS由于残压过高无法满足要求,而负阻型器件在低的峰值残压下由于负阻稳定点过低可能低于电源工作电压也无法满足实际应用要求。本发明使用P型薄片负阻工艺和辐照改性工艺相结合,可以在满足低的峰值残压的同时满足负阻稳定点可控。
发明内容
本发明目的在于提供一种低残压、负阻稳定点可控、高浪涌双向瞬态抑制二极管器件及其制造方法。
为了满足以上要求,本发明采取以下技术方案:
一种伪负阻型低残压TVS器件的制备方法,工艺步骤如下:
投片下料,依照电压选择合适电阻率抛光片,通常使<111>晶向,P型衬底,为保证表面清洁,需要经过清洗工艺;
减薄工艺,原衬底进行减薄,一般可以采用CMP或吹沙工艺进行减薄,减薄到指定厚度30μm到250μm之间,通常厚度值在180μm左右。为保证表面清洁,需要经过清洗工艺;
制结工艺,将衬底进行制结工艺,制结工艺一般可以使用涂布工艺、纸源扩散工艺、POCL3预淀积工艺、注入工艺等,之后进行推结退火使耐压和结深达到设计值;
氧化工艺,氧化形成隔离层,可以适用于台面工艺和平面工艺;
光刻显影蚀刻工艺,通过光刻和显影把指定图形复制在硅片上,经过蚀刻完成沟槽腐蚀;
玻璃钝化腐蚀开窗口,通过涂玻璃工艺与玻璃烧结工艺完成沟槽PN结界面的保护,再通过光刻蚀刻把接触面钝化进行去除;
辐照和退火工艺,制品进行辐照工艺,使用剂量为0.001KGy到1KKGy之间,包括却不只限于电子辐照、核辐照等可以降低半导体器件少子寿命的辐照工艺,之后进行退火,使用氮氢退火、氮气退火或者真空退火,以使辐照趋于稳定且改善界面态,之后进行清洗;
表面金属制备,使用蒸发、溅射或者液体镀金属层。之后经过高温退火形成欧姆接触。
本发明的重点在于采用薄片负阻工艺与辐照改性工艺。
本发明所述TVS器件为功能性结构掺杂为NPN型,可双向浪涌防护的器件。
本发明的伪负阻TVS器件,采用P型抛光片薄片进行流片,深结工艺来形成负阻效应结构。之后使用辐照改性,通过一定剂量的电子辐照引入复合中心。复合中心的引入可以有效降低少子寿命,降低NPN器件放大倍数,从而使器件恢复到近似非负阻特性。在浪涌发生时,在大电流注入效应下。由于基区距离短,器件串联电阻低使器件残压变低。但是又由于少子寿命降低,负阻效应不明显,使器件负阻稳定点高。确保不低于电源电压,保证应用无异常。
低残压是通过薄片负阻型工艺实现。高浪涌是通过降低残压实现。负阻稳定点高且可控是通过辐照改性和芯片厚度结深等配合调节实现。
负阻稳定点指负阻器件在受到浪涌冲击时浪涌波形产生负阻效应时,稳定段的平均电压值。
伪负阻指在浪涌或者大电流通过时,较芯片未辐照之前有不明显的负阻效应。
附图说明
图1为负阻稳定点示意图。
图2为衬底减薄芯片过程剖面示意图。
图3为玻璃钝化后芯片剖面示意图。
图4为金属后芯片剖面示意图。
图5为图示仪显示非负阻芯片曲线示意图。
图6为图示仪显示负阻芯片曲线示意图。
图7为图示仪显示伪负阻芯片曲线示意图。
图8为示波器显示非负阻芯片浪涌曲线示意图。
图9为示波器显示负阻芯片浪涌曲线示意图。
图10为示波器显示伪负阻芯片浪涌曲线示意图。
图11为示波器显示三种芯片浪涌曲线对比示意图。
具体实施方式
下面结合附图给出本发明较佳实施例,以详细说明本发明的技术方案。
以20V双向台面工艺伪负阻型低残压TVS器件为例对具体实施方式进行说明。
投片下料,选择电阻率为0.039Ω·cm,<111>P型衬底投片下料。之后经过HF清洗工艺。
减薄工艺,对原衬底进行减薄。采用吹沙工艺进行减薄,减薄到140μm。之后经过HF清洗工艺。减薄工艺对比如图2。
制结工艺,POCL3预淀积工艺,之后进行推结退火。退火条件为1200℃30小时。
氧化工艺,在1050摄氏度条件下生长70分钟氧化层,采用干氧加湿氧的方法。
光刻显影蚀刻工艺,通过光刻和显影把指定图形复制在硅片上。经过蚀刻完成沟槽腐蚀。玻璃钝化腐蚀开窗口,通过涂玻璃工艺与玻璃烧结工艺完成沟槽PN结界面的保护。再通过光刻蚀刻把接触面钝化进行去除。钝化后纵向剖面结构如图3。
辐照和退火工艺,采用电子辐照500Gy计量辐照。之后采用真空退火稳定、恢复辐照缺陷。
电极制备使用钛镍银结构。之后采取450℃N-H退火。芯片剖面如图4。
芯片制样完成后使用传统SMB封装,solder工艺进行封装。并且对传统20V非负阻产品、伪负阻产品、负阻产品进行I-V曲线对比。图5为图示仪显示非负阻芯片曲线示意图,图6为图示仪显示负阻芯片曲线示意图,图7为图示仪显示伪负阻芯片曲线示意图。负阻芯片在图示仪上可见明显的负阻现象,但非负阻和伪负阻产品曲线类似未见明显的负阻现象。
对传统20V非负阻产品、伪负阻产品、负阻产品进行8-20浪涌波形对比。图8为示波器显示非负阻芯片浪涌曲线示意图。图9为示波器显示负阻芯片浪涌曲线示意图。图10为示波器显示伪负阻芯片浪涌曲线示意图。图11为示波器显示三种芯片浪涌曲线对比示意图。由结果可见,非负阻产品残压很高在40V附近,高的残压会造成后级电路的损坏。负阻产品残压峰值约在32V左右,但是残压负阻稳定点过低,约18V。当此期间使用在20V电源口时会造成电源电压拉低。导致防浪涌器件提前损坏,并且过低的电压会造成整机短时间异常重启。
本发明制备的浪涌保护器件用于浪涌防护和静电防护的半导体器件,其工作电压范围在3V到100V之间。
Claims (3)
1.一种伪负阻型低残压TVS器件的制备方法,其特征在于,包括采用薄片负阻工艺与辐照改性工艺,包括如下工艺步骤:
选P型衬底,进行减薄工艺,减薄到指定厚度30μm到250μm之间;
制结工艺,形成NPN结构;
所述的辐照改性工艺中使用剂量为0.001KGy到1KKGy之间;
表面金属制备,形成欧姆接触;
所述TVS器件为功能性结构掺杂为NPN型,可双向浪涌防护的器件;
伪负阻型低残压TVS器件,采用深结工艺来形成负阻效应结构;之后使用辐照改性,通过一定剂量的辐照引入复合中心。
2.如权利要求1所述的伪负阻型低残压TVS器件的制备方法,其特征在于,所述的辐照改性工艺包括电子辐照、核辐照,以降低半导体器件少子寿命的辐照工艺。
3.一种伪负阻型低残压TVS器件,其特征在于,根据权利要求1-2任意一项所述方法制备。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811130910.6A CN109300994B (zh) | 2018-09-27 | 2018-09-27 | 一种伪负阻型低残压tvs器件及其制备方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811130910.6A CN109300994B (zh) | 2018-09-27 | 2018-09-27 | 一种伪负阻型低残压tvs器件及其制备方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN109300994A CN109300994A (zh) | 2019-02-01 |
CN109300994B true CN109300994B (zh) | 2023-05-30 |
Family
ID=65164598
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201811130910.6A Active CN109300994B (zh) | 2018-09-27 | 2018-09-27 | 一种伪负阻型低残压tvs器件及其制备方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN109300994B (zh) |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0497290A2 (en) * | 1991-01-28 | 1992-08-05 | Kabushiki Kaisha Toshiba | Switching semiconductor device and method of manufacturing the same |
US5343065A (en) * | 1991-12-02 | 1994-08-30 | Sankosha Corporation | Method of controlling surge protection device hold current |
CN102769026A (zh) * | 2011-05-06 | 2012-11-07 | 江苏锦丰电子有限公司 | 低电容高速传输半导体浪涌保护器件 |
JP2013069989A (ja) * | 2011-09-26 | 2013-04-18 | Toshiba Corp | 半導体装置 |
CN103956324A (zh) * | 2014-04-30 | 2014-07-30 | 天津中环半导体股份有限公司 | 一种具备沟道效应的瞬态电压抑制器芯片的生产工艺 |
CN108428697A (zh) * | 2017-11-09 | 2018-08-21 | 上海长园维安微电子有限公司 | 一种低电容双向带负阻tvs器件 |
-
2018
- 2018-09-27 CN CN201811130910.6A patent/CN109300994B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0497290A2 (en) * | 1991-01-28 | 1992-08-05 | Kabushiki Kaisha Toshiba | Switching semiconductor device and method of manufacturing the same |
US5343065A (en) * | 1991-12-02 | 1994-08-30 | Sankosha Corporation | Method of controlling surge protection device hold current |
CN102769026A (zh) * | 2011-05-06 | 2012-11-07 | 江苏锦丰电子有限公司 | 低电容高速传输半导体浪涌保护器件 |
JP2013069989A (ja) * | 2011-09-26 | 2013-04-18 | Toshiba Corp | 半導体装置 |
CN103956324A (zh) * | 2014-04-30 | 2014-07-30 | 天津中环半导体股份有限公司 | 一种具备沟道效应的瞬态电压抑制器芯片的生产工艺 |
CN108428697A (zh) * | 2017-11-09 | 2018-08-21 | 上海长园维安微电子有限公司 | 一种低电容双向带负阻tvs器件 |
Also Published As
Publication number | Publication date |
---|---|
CN109300994A (zh) | 2019-02-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101540343B (zh) | 偏移场板结构的4H-SiC PiN/肖特基二极管及其制作方法 | |
US7728409B2 (en) | Semiconductor device and method of manufacturing the same | |
CN102569067B (zh) | 一种平面高压超快软恢复二极管的制造方法 | |
JP2021168389A (ja) | ダイヤモンド半導体システムと方法 | |
CN106601826B (zh) | 一种快恢复二极管及其制作方法 | |
CN104810281A (zh) | 一种台面沟槽隔离法瞬态电压抑制二极管阵列的芯片及其生产工艺 | |
US20150206749A1 (en) | Diamond Semiconductor System and Method | |
CN103839805B (zh) | 一种功率器件的制备方法 | |
CN110364575A (zh) | 一种具有浮动场环终端结构的结势垒肖特基二极管及其制备方法 | |
CN105789331A (zh) | 半导体整流器件及其制作方法 | |
US8536448B2 (en) | Zener diode within a diode structure providing shunt protection | |
CN103187250A (zh) | 多次外延生长方法 | |
CN108807284B (zh) | 一种外延接合基板及其制造方法 | |
CN109300994B (zh) | 一种伪负阻型低残压tvs器件及其制备方法 | |
CN103531465A (zh) | 快恢复二极管制备方法 | |
CN106611797A (zh) | 一种具有局域金属寿命控制的功率器件及其制作方法 | |
CN109860309A (zh) | 一种tvs的结构设计和制作方法 | |
CN110942989B (zh) | 一种用于硅基快恢复二极管芯片的铂金掺杂方法 | |
CN212085008U (zh) | 一种具有负阻特性的半导体放电管 | |
CN106558624B (zh) | 一种快速恢复二极管及其制造方法 | |
JP6594296B2 (ja) | 改善された逆サージ能力及び削減されたリーク電流のポリシリコン層を有するツェナーダイオード | |
CN112054020B (zh) | 一种低电容静电防护芯片器件及其制备方法 | |
CN111223914A (zh) | 一种具有负阻特性的半导体放电管及其制造方法 | |
CN112820698A (zh) | 一种快充电源及接口浪涌保护芯片制造工艺 | |
CN111223771A (zh) | 一种垂直型硅基氮化镓功率器件减薄方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
CB02 | Change of applicant information |
Address after: Seven road 201202 Shanghai Pudong New Area Shiwan No. 1001 Applicant after: Shanghai Wei'an Semiconductor Co.,Ltd. Address before: 201202 Shanghai city Pudong New Area Town Road No. 1001 to seven Shiwan Building 2 Applicant before: SHANGHAI CHANGYUAN WAYON MICROELECTRONICS Co.,Ltd. |
|
CB02 | Change of applicant information | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |