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CN109037240A - 阵列基板及其制作方法、显示面板、显示装置 - Google Patents

阵列基板及其制作方法、显示面板、显示装置 Download PDF

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CN109037240A
CN109037240A CN201810844123.1A CN201810844123A CN109037240A CN 109037240 A CN109037240 A CN 109037240A CN 201810844123 A CN201810844123 A CN 201810844123A CN 109037240 A CN109037240 A CN 109037240A
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layer
igzo film
grid
film layer
array substrate
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CN109037240B (zh
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周斌
操彬彬
闫梁臣
王东方
赵策
丁录科
刘军
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BOE Technology Group Co Ltd
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Abstract

本公开属于显示技术领域，提出一种阵列基板，该阵列基板包括IGZO膜层、栅极层以及栅极绝缘层；栅极层在与IGZO膜层重叠的位置设置断线以形成第一栅线和第二栅线；栅极绝缘层设于IGZO膜层与栅极层之间，其上设置有至少两个通孔，第一栅线与IGZO膜层通过其中一个通孔连接，第二栅线与IGZO膜层通过另一通孔连接；从而将IGZO膜层串连接入栅极层。在完成IGZO膜层的导体化工艺之后，给栅极层通电，能够导通说明IGZO膜层的导体化工艺成功，不能够导通说明IGZO膜层的导体化工艺失败，不需要进行下一步工艺，以节省人力物力。当然，在此步骤中已经检出不合格产品，最后完成所有工序后产品的合格率会得到提升。

Description

阵列基板及其制作方法、显示面板、显示装置
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及阵列基板的制作方法、安装有该阵列基板的显示面板、安装有该显示面板的显示装置。
背景技术
在OLED TV的技术中，顶栅型的薄膜晶体管实现了窄沟道，使其体积较小，从而增大开口率，提高画面质量；但是，在每个像素点中，非晶硅薄膜晶体管都会占用像素的一定面积，使透光面积减少。而铟镓锌氧化物形成的薄膜晶体管则是透明的，而且对可见光不敏感，所以大大增加了器件开口率，从而提高了亮度，降低功耗。
目前，由于铟镓锌氧化物的导体化工艺的不稳定性，非常容易出现导体化不良的情况；而铟镓锌氧化物的导体化工艺决定了源漏极与铟镓锌氧化物的连接电阻，该连接电阻又决定了产品的合格率；但是，此种导体化不良，无法通过光学设备检测出来，只能在完成所有工序成后才能被测试出来。因此，对导体化不良的产品必须进行后续工序，浪费人力、物力，且造成产品合格率降低。
因此，有必要研究一种新的阵列基板及阵列基板的制作方法、安装有该阵列基板的显示面板、安装有该显示面板的显示装置。
所述背景技术部分公开的上述信息仅用于加强对本公开的背景的理解，因此它可以包括不构成对本领域普通技术人员已知的相关技术的信息。
发明内容
本公开的目的在于克服上述相关技术的铟镓锌氧化物的导体化不良只能在完成所有工序成后才能被测试出来不足，提供一种能够提前检测铟镓锌氧化物的导体化不良的阵列基板及阵列基板的制作方法、安装有该阵列基板的显示面板、安装有该显示面板的显示装置。
本公开的额外方面和优点将部分地在下面的描述中阐述，并且部分地将从描述中变得显然，或者可以通过本公开的实践而习得。
根据本公开的一个方面，提供一种阵列基板，包括：
IGZO膜层；
栅极层，在与所述IGZO膜层重叠的位置设置断线以形成第一栅线和第二栅线；
栅极绝缘层，设于所述IGZO膜层与所述栅极层之间，其上设置有至少两个通孔，所述第一栅线与所述IGZO膜层通过至少一个所述通孔连接，所述第二栅线与所述IGZO膜层通过另外的至少一个所述通孔连接。
在本公开的一种示例性实施例中，所述IGZO膜层设于所述栅极绝缘层之下，所述栅极层设于所述栅极绝缘层之上。
在本公开的一种示例性实施例中，所述阵列基板还包括：
基板，
遮光层，设于所述基板之上；
缓冲层，设于所述遮光层以及所述基板之上，其上设置所述IGZO膜层；
层间绝缘层，设于所述栅极层以及所述缓冲层之上；
源漏极层，设于所述层间绝缘层之上；
钝化层，设于所述源漏极层之上；
像素电极层，设于所述钝化层之上。
在本公开的一种示例性实施例中，所述IGZO膜层设于所述栅极绝缘层之上，所述栅极层设于所述栅极绝缘层之下。
根据本公开的一个方面，提供一种阵列基板的制作方法，包括：
形成IGZO膜层；
在所述IGZO膜层之上形成栅极绝缘层，并在所述栅极绝缘层上形成至少两个通孔；
在所述栅极绝缘层之上形成栅极层，在所述栅极层的与所述IGZO膜层重叠的位置断线形成第一栅线和第二栅线，所述第一栅线贯穿至少一个所述通孔与所述IGZO膜层连接，所述第二栅线贯穿另外的至少一个所述通孔与所述IGZO膜层连接。
在本公开的一种示例性实施例中，在所述栅极绝缘层上形成至少两个通孔之后，所述制作方法还包括：
对所述IGZO膜层进行导体化处理。
根据本公开的一个方面，提供一种阵列基板的制作方法，包括：
形成栅极层，对所述栅极层进行刻蚀处理使其断线形成第一栅线和第二栅线；
在所述栅极层之上形成栅极绝缘层，并在所述栅极绝缘层上形成连通至所述第一栅线的至少一个第一通孔以及连通至所述第二栅线的至少一个第二通孔；
在所述栅极绝缘层之上形成IGZO膜层，所述IGZO膜层贯穿所述第一通孔以及所述第二通孔与所述栅极层连接。
在本公开的一种示例性实施例中，所述制作方法还包括：
对所述IGZO膜层进行导体化处理。
根据本公开的一个方面，提供一种显示面板，包括：
上述任意一项所述的阵列基板。
根据本公开的一个方面，提供一种显示装置，包括：
上述任意一项所述的显示面板。
由上述技术方案可知，本公开具备以下优点和积极效果中的至少之一：
本公开的阵列基板及阵列基板的制作方法，栅极层断线形成第一栅线和第二栅线；栅极绝缘层上设置有至少两个通孔，第一栅线与IGZO膜层通过至少一个通孔连接，第二栅线与IGZO膜层通过另外的至少一个通孔连接，从而将IGZO膜层串连接入栅极层。在完成IGZO膜层的导体化工艺之后，给栅极层通电，能够导通说明IGZO膜层的导体化工艺成功，不能够导通说明IGZO膜层的导体化工艺失败，不需要进行下一步工艺，以节省人力物力。且能够提升导体化的均一性。当然，在此步骤中已经检出不合格产品，最后完成所有工序后产品的合格率会得到提升。
附图说明
通过参照附图详细描述其示例实施方式，本公开的上述和其它特征及优点将变得更加明显。
图1是本公开阵列基板的一示例实施方式的结构示意图；
图2是图1中形成栅极层后的俯视结构示意图；
图3是本公开阵列基板的另一示例实施方式的结构示意图；
图4是本公开阵列基板的制作方法的一示例实施方式的流程示意框图；
图5是本公开阵列基板的制作方法的另一示例实施方式的流程示意框图；
图中主要元件附图标记说明如下：
1、基板；2、遮光层；3、缓冲层；4、IGZO膜层；5、栅极绝缘层；
6、栅极层；61、第一栅线；62、第二栅线；
7、层间绝缘层；8、源漏极层。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
本公开首先提供了一种阵列基板，该阵列基板可以包括IGZO膜层4、栅极层6以及栅极绝缘层5。栅极层6在与IGZO膜层4重叠的位置设置断线以形成第一栅线61和第二栅线62；栅极绝缘层5设于IGZO膜层4与栅极层6之间，栅极绝缘层5上设置有至少两个通孔，第一栅线61与IGZO膜层4通过至少一个通孔连接，第二栅线62与IGZO膜层4通过另外的至少一个通孔连接。
下面通过两个示例实施方式对本公开的阵列基板进行具体说明。
示例实施方式一
在本示例实施方式中，阵列基板中的薄膜晶体管为顶栅型。该阵列基板可以包括基板1、遮光层2、缓冲层3、IGZO膜层4、栅极绝缘层5、栅极层6、层间绝缘层7、源漏极层8以及像素电极层。
参照图1所示的阵列基板的一示例实施方式的结构示意图；具体为：遮光层2设于基板1之上，其材质可以为金属钼。缓冲层3设于遮光层2以及基板1之上，其厚度大约为大于等于300nm且小于等于500nm，其材质可以为SiOx。
IGZO膜层4设于缓冲层3之上，其厚度大约为大于等于10nm且小于等于80nm，IGZO膜层4作为有源层。参照图2所示的图1中形成栅极层后的俯视结构示意图；栅极绝缘层5设于IGZO膜层4之上，其厚度大约为大于等于100nm且小于等于200nm，其材质可以为SiOx；且可以通过刻蚀处理在栅极绝缘层5上形成两个连通至IGZO膜层4的通孔。栅极层6设于栅极绝缘层5之上，其厚度大约为400nm，其材质可以为铜，形成的栅极层6会通过通孔与IGZO膜层4连接，并通过光刻和刻蚀处理使栅极层6断线形成第一栅线61和第二栅线62，断线位置位于两个通孔之间，形成第一栅线61与IGZO膜层4通过其中一个通孔连接，第二栅线62与IGZO膜层4通过另一通孔连接的结构，从而将IGZO膜层4串连接入栅极层6。在完成IGZO膜层4的导体化工艺之后，给栅极层6通电，能够导通说明IGZO膜层4的导体化工艺成功，不能够导通说明IGZO膜层4的导体化工艺失败，不需要进行下一步工艺，以节省人力物力。当然，在此步骤中已经检出不合格产品，最后完成所有工序后产品的合格率会得到提升。还可以对IGZO膜层4进行再次导体化工艺，然后再次检测。
另外，通孔的个数还可以设置为三个、四个或更多个，可对称设置，也可以不对称设置，只要在断线的两侧均设置有通孔即可。
层间绝缘层7设于栅极层6以及缓冲层3之上，其厚度大约为大于等于300nm且小于等于500nm，其材质可以为SiOx。源漏极层8设于层间绝缘层7之上，其厚度大约为大于等于400nm且小于等于600nm，其材质可以为铜；钝化层设于源漏极层8之上，其厚度大约为大于等于200nm且小于等于400nm，其材质可以为SiOx或SiNx。像素电极层设于钝化层之上，其厚度大约为大于等于10nm且小于等于80nm，其材质可以为铟镓锌氧化物。
示例实施方式二
在本示例实施方式中，阵列基板中的薄膜晶体管为底栅型。该阵列基板可以包括基板1、栅极层6、栅极绝缘层5、IGZO膜层4以及源漏极层8等等。
参照图3所示的阵列基板的另一示例实施方式的结构示意图，具体为：栅极层6设于基板之上，并通过光刻和刻蚀处理使栅极层6断线形成第一栅线61和第二栅线62。栅极绝缘层5设于栅极层6之上，可以通过刻蚀处理在栅极绝缘层5上形成两个连通至栅极层6的通孔，且第一通孔连通至第一栅线61，第二通孔连通至第二栅线62，也就是说两个通孔位于断线的两侧。IGZO膜层4设于栅极绝缘层5之上，IGZO膜层4通过第一通孔与第一栅线61连接，且通过第二通孔与第二栅线62连接，同样能够使IGZO膜层4串连接入栅极层6。在完成IGZO膜层4的导体化工艺之后，给栅极层6通电，能够导通说明IGZO膜层4的导体化工艺成功，不能够导通说明IGZO膜层4的导体化工艺失败，不需要进行下一步工艺，以节省人力物力。当然，在此步骤中已经检出不合格产品，最后完成所有工序后产品的合格率会得到提升。源漏极层8设置在IGZO膜层4之上。当然，在本示例实施方式中，通孔的个数也可以设置为三个、四个或更多个，可对称设置，也可以不对称设置，只要在断线的两侧均设置有通孔即可。
进一步的，本公开还提供了一种阵列基板的制作方法，参照图4所示的阵列基板的制作方法的一示例实施方式的流程示意框图，该阵列基板的制作方法可以包括以下步骤：
步骤S10，形成IGZO膜层4。
步骤S20，在IGZO膜层4之上形成栅极绝缘层5，并在栅极绝缘层5上形成至少两个通孔。
步骤S30，在栅极绝缘层5之上形成栅极层6，在栅极层6的与IGZO膜层4重叠的位置断线形成第一栅线61和第二栅线62，第一栅线61贯穿其至少一个通孔与IGZO膜层4连接，第二栅线62贯穿另外的至少一个通孔与IGZO膜层4连接。
该阵列基板的具体的制作方法如下：
可以通过溅射工艺沉积厚度大约为大于等于10且小于等于80nm的钼形成遮光层2，并根据需要进行光刻、刻蚀。
可以通过等离子体增强化学的气相沉积法沉积厚度大约为大于等于300且小于等于500nm的SiOx作为缓冲层3；
可以通过溅射工艺沉积厚度大约为大于等于10且小于等于80nm的IGZO膜层4作为有源层，并根据需要进行光刻、刻蚀形成需要的形状。
可以通过等离子体增强化学的气相沉积法沉积厚度大约为大于等于100且小于等于200nm的SiOx作为栅极绝缘层5；根据需要进行图形化，并形成至少两个通孔。然后对IGZO膜层4进行导体化处理，即通过He等离子轰击IGZO膜层4进行导体化。
可以通过溅射工艺制备厚度大约为400nm的栅极层6，并根据所需图形进行光刻和刻蚀，使其与IGZO膜层4重叠的位置断线形成第一栅线61和第二栅线62，第一栅线61贯穿至少一个通孔与IGZO膜层4连接，第二栅线62贯穿另外的至少一个通孔与IGZO膜层4连接。
可以通过等离子体增强化学的气相沉积法沉积厚度大约为大于等于300且小于等于500nm的SiOx作为层间绝缘层7，并根据需要进行图形化。
可以通过溅射工艺制备厚度大约为大于等于400nm且小于等于600nm的源漏极层8，并根据所需图形进行光刻和刻蚀。
可以通过等离子体增强化学的气相沉积法沉积厚度大约为大于等于200且小于等于400nm的SiOx或SiNx作为钝化层，并根据需要进行图形化。
可以通过溅射工艺沉积厚度大约为大于等于10且小于等于80nm的IGZO为像素电极层，并根据需要进行光刻、刻蚀。
进一步的，本公开还提供了一种阵列基板的制作方法，参照图5所示的阵列基板的制作方法的另一示例实施方式的流程示意框图，该阵列基板的制作方法可以包括以下步骤：
步骤S60，形成栅极层6，对栅极层6进行刻蚀处理使其断线形成第一栅线61和第二栅线62。
步骤S70，在栅极层6之上形成栅极绝缘层5，并在栅极绝缘层5上形成连通至第一栅线61的第一通孔以及连通至第二栅线62的第二通孔。
步骤S80，在栅极绝缘层5之上形成IGZO膜层4，IGZO膜层4贯穿第一通孔以及第二通孔与栅极层6连接。
在本示例实施方式中，形成IGZO膜层4后对IGZO膜层4进行导体化处理。
该阵列基板的制作方法在上述阵列基板的示例实施方式二中已经进行了详细说明，因此，此处不再赘述。
进一步的，本公开还提供了一种显示面板，该显示面板可以包括上述阵列基板。关于阵列基板的具体结构在上述阵列基板的说明中已经进行了详细的说明，因此，此处不再赘述。
进一步的，本公开还提供了一种显示装置，该显示装置可以包括上述显示面板，该显示面板包括上述阵列基板。关于阵列基板的具体结构在上述阵列基板的说明中已经进行了详细的说明，因此，此处不再赘述。
上述所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中，如有可能，各实施例中所讨论的特征是可互换的。在上面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组件、材料等。在其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本公开的各方面。
本说明书中使用“约”“大约”的用语通常表示在一给定值或范围的20％之内，较佳是10％之内，且更佳是5％之内。在此给定的数量为大约的数量，意即在没有特定说明的情况下，仍可隐含“约”“大约”“大致”“大概”的含义。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
本说明书中，用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包含”、“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。应可理解的是，本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书所述的实施方式说明了已知用于实现本公开的最佳方式，并且将使本领域技术人员能够利用本公开。

Claims (10)

1.一种阵列基板，其特征在于，包括：
IGZO膜层；
栅极层，在与所述IGZO膜层重叠的位置设置断线以形成第一栅线和第二栅线；
栅极绝缘层，设于所述IGZO膜层与所述栅极层之间，其上设置有至少两个通孔，所述第一栅线与所述IGZO膜层通过至少一个所述通孔连接，所述第二栅线与所述IGZO膜层通过另外的至少一个所述通孔连接。
2.根据权利要求1所述的阵列基板，其特征在于，所述IGZO膜层设于所述栅极绝缘层之下，所述栅极层设于所述栅极绝缘层之上。
3.根据权利要求2所述的阵列基板，其特征在于，所述阵列基板还包括：
基板，
遮光层，设于所述基板之上；
缓冲层，设于所述遮光层以及所述基板之上，其上设置所述IGZO膜层；
层间绝缘层，设于所述栅极层以及所述缓冲层之上；
源漏极层，设于所述层间绝缘层之上；
钝化层，设于所述源漏极层之上；
像素电极层，设于所述钝化层之上。
4.根据权利要求1所述的阵列基板，其特征在于，所述IGZO膜层设于所述栅极绝缘层之上，所述栅极层设于所述栅极绝缘层之下。
5.一种阵列基板的制作方法，其特征在于，包括：
形成IGZO膜层；
在所述IGZO膜层之上形成栅极绝缘层，并在所述栅极绝缘层上形成至少两个通孔；
在所述栅极绝缘层之上形成栅极层，在所述栅极层的与所述IGZO膜层重叠的位置断线形成第一栅线和第二栅线，所述第一栅线贯穿至少一个所述通孔与所述IGZO膜层连接，所述第二栅线贯穿另外的至少一个所述通孔与所述IGZO膜层连接。
6.根据权利要求5所述的阵列基板的制作方法，其特征在于，在所述栅极绝缘层上形成至少两个通孔之后，所述制作方法还包括：
对所述IGZO膜层进行导体化处理。
7.一种阵列基板的制作方法，其特征在于，包括：
形成栅极层，对所述栅极层进行刻蚀处理使其断线形成第一栅线和第二栅线；
在所述栅极层之上形成栅极绝缘层，并在所述栅极绝缘层上形成连通至所述第一栅线的至少一个第一通孔以及连通至所述第二栅线的至少一个第二通孔；
在所述栅极绝缘层之上形成IGZO膜层，所述IGZO膜层贯穿所述第一通孔以及所述第二通孔与所述栅极层连接。
8.根据权利要求7所述的阵列基板的制作方法，其特征在于，所述制作方法还包括：
对所述IGZO膜层进行导体化处理。
9.一种显示面板，其特征在于，包括：
权利要求1～4任意一项所述的阵列基板。
10.一种显示装置，其特征在于，包括：
权利要求9所述的显示面板。
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CN108198819A (zh) * 2017-12-21 2018-06-22 深圳市华星光电技术有限公司 一种阵列基板及其制备方法

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