CN108511427A - Twin-core chip package - Google Patents
Twin-core chip package Download PDFInfo
- Publication number
- CN108511427A CN108511427A CN201710102251.4A CN201710102251A CN108511427A CN 108511427 A CN108511427 A CN 108511427A CN 201710102251 A CN201710102251 A CN 201710102251A CN 108511427 A CN108511427 A CN 108511427A
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- gasket
- chip
- routing
- pin
- twin
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Abstract
The present invention provides a kind of twin-core chip package, by the way that exposed pad is arranged using as ground terminal, the GND routing gaskets of two chips in encapsulating structure are electrically coupled to the exposed pad, enabling the lead frame tool, there are two CS pins with the CS routing gaskets of the described two chips of electric property coupling respectively, so as to make encapsulating structure under the premise of eight pins, avoid the device conflict problem between two chips, thereby the present invention provides a kind of twin-core chip package of low pin count amount, can effectively reduce cost.
Description
Technical field
The present invention relates to a kind of semiconductor packages, in more detail, refer to a kind of twin-core chip package.
Background technology
As the application of microminiature electronic equipment is more and more common (such as wearable electronic equipment), low pin count package and
More storage chips also increasingly flow on the market therewith because it has many advantages, such as that small product size is smaller and manufacturing cost is relatively low
Row, for example, serial peripheral interface flash memory (SPI Flash) and static random access memory (SPI SRAM).In addition, eight are drawn
The encapsulating structure of foot is also to be currently manufactured as a kind of this encapsulating structure the most economic and volume minimum.
MCP (multi-chip package Multi Chip Package) is that a kind of encapsulation of semiconductor system grade and multi-chip package are new
A variety of memories are included NOR Flash, NAND Flash, Low Power SRAM and Pseudo by the extension of technology, design
The chips such as SRAM, storehouse are packaged into 1 MCP chip (such as：16MB Flash+2MB SRAM or 256MB DRAM+64MB
Flash), it is applicable to all kinds of hand-helds and miniaturized electronic product, such as intelligent wearable device, digital camera, digital photography
Machine, smartphone, satellite navigation system and tablet computer etc..
If however, more than two SPI memory chips are integrated directly into same encapsulating structure, can be because can not judge often
Which SPI memory chip is executing access operation, and the device conflict of chip chamber occurs, and therefore, there are two SPI memory cores for tool
Tool is needed in the encapsulating structure of piece, and there are two CS pins, judge it is which SPI memory chip is executing access operation to provide.
Specifically, please refer to Fig. 1 and Fig. 2, Fig. 1 is the pin of the single die package of SPI memory chips 320
Setting figure, Fig. 2 are the pin setting figure of the twin-core chip package of known SPI memory chips 420.As shown in Figure 1, SPI memories
The single die package of chip 320 has 8 pins, and which includes a CS pins 321 and a GND pins 322.Please after
It is continuous referring to Fig.2, in order to avoid the device conflict between difference SPI memory chips in same encapsulating structure, known SPI memory chips
In 420 twin-core chip package, in addition to equally having a GND pin 422, SPI memory chips 420 further include that there are two CS
Pin 421a and 421b (i.e. CS1 and CS2) use the control signal for distinguishing two difference SPI memory chips in encapsulating structure, therefore
And ten pins (including a sky pin NC) need to be arranged in the twin-core chip package of the SPI memory chips 420 of this type altogether, nothing
The package dimension of chip can be increased by doubting, and can improve its manufacturing cost.
In conclusion how to realize in the encapsulating structure of the lead frame with eight pins, dual chip encapsulation knot is solved
Device conflict problem in structure between difference SPI memory chips, as this case technical task to be solved.
Invention content
In view of the variety of problems of above-mentioned prior art, the main purpose of the present invention is to provide a kind of encapsulation of dual chip to tie
Structure, can be under the premise of not increasing pin number, merely with the lead frame of eight pins to avoid in twin-core chip package
Device conflict between two chips.
Another object of the present invention is to provide a kind of twin-core chip packages of low pin count, can effectively reduce and be manufactured into
This simultaneously reduces encapsulation volume.
In order to achieve the above objectives and other purposes, the present invention provide a kind of twin-core chip package, are set to a printing
Circuit board, the printed circuit board have one to be grounded cooling pad, and the twin-core chip package includes and the ground connection cooling pad
The exposed pad of one of electric property coupling；Two chips being set on the exposed pad, each chip are respectively provided with a CS wire pads
Piece, a GND routings gasket, one first routing gasket, one second routing gasket, a third routing gasket, one the 4th routing gasket,
One the 5th routing gasket and one the 6th routing gasket；Equipped with one of eight pins lead frame, eight pins include two CS
Pin, one first pin, a second pin, a third pin, one the 4th pin, one the 5th pin and one the 6th pin；Two
CS conducting wires, two of CS routings gasket and the lead frame of both ends difference each chip of electric property coupling of each CS conducting wires
The one of which of CS pins；The GND of two GND conducting wires, both ends difference each chip of electric property coupling of each GND conducting wires is beaten
Line gasket and the exposed pad；Two first conducting wires, both ends difference each chip of electric property coupling of each first conducting wire
First pin of the first routing gasket and the lead frame；The both ends difference of two second conducting wires, each second conducting wire is electrical
Couple the second pin of the second routing gasket and the lead frame of each chip；Two privates, each third are led
The third pin of the third routing gasket and the lead frame of both ends difference each chip of electric property coupling of line；Two article the 4th is led
Line, the 4th routing gasket and the 4th of the lead frame of both ends difference each chip of electric property coupling of each privates
Pin；Two article of the 5th conducting wire, each 5th conducting wire both ends difference each chip of electric property coupling the 5th routing gasket with
5th pin of the lead frame；And two article of the 6th conducting wire, the both ends difference electric property coupling of each 6th conducting wire are each described
6th pin of the 6th routing gasket and the lead frame of chip.
Preferably, in above-mentioned twin-core chip package, described two chips be SPI chips, Dual-SPI chips or
Quad-SPI chips.
Preferably, in above-mentioned twin-core chip package, the twin-core chip package for Serial Flash,
The combination of Serial SRAM or the two kinds of difference interfaces Serial memories.
Preferably, in above-mentioned twin-core chip package, the first to the 6th routing gasket of described two chips is respectively
DO (IO1) routings gasket, WP (IO2) routings gasket, DI (IO0) routings gasket, CLK routings gasket, HOLD (IO3) wire pad
First to the 6th pin of piece, VCC routing gaskets, the lead frame corresponds to DO (IO1) pin, WP (IO2) pin, DI respectively
(IO0) pin, CLK pin, HOLD (IO3) pin, VCC pin.
Preferably further includes a separation layer in above-mentioned twin-core chip package, is set between described two chips,
Enable described two chips that can be set on the exposed pad with stacked manner.
Furthermore the present invention also provides a kind of twin-core chip packages, are set to a printed circuit board, the printed circuit board
With a ground connection cooling pad, the twin-core chip package includes and one of the ground connection cooling pad electric property coupling exposed pad；Tool
There is the first chip of one of one the oneth CS routings gasket and one the oneth GND routing gaskets；With one the 2nd CS routings gasket and one
The second chip of one of two GND routing gaskets；And with one of one the oneth CS pins and one the 2nd CS pins lead frame；Its
In, the first GND routings gasket of first chip and the 2nd GND routing gaskets difference electric property coupling institute of second chip
State exposed pad, the first CS pins of lead frame described in the first CS routing gasket electric property couplings of first chip, described second
2nd CS pins of lead frame described in 2nd CS routing gasket electric property couplings of chip.
Preferably, in above-mentioned twin-core chip package, first chip and the second chip are at least eight dozens
SPI chips, Dual-SPI chips or the Quad-SPI chips of line gasket.
Preferably, in above-mentioned twin-core chip package, the lead frame has eight pins.
Preferably further includes an insulating layer in above-mentioned twin-core chip package, be set to first chip with it is described
Between second chip, enable first chip that can be set on the exposed pad with stacked manner with second chip.
Preferably, in above-mentioned twin-core chip package, the first CS routings gasket and the 2nd CS routing gaskets
Start for low level；The first CS pins start with the 2nd CS pins for low level.
In conclusion the twin-core chip package of the present invention is by being arranged exposed pad with the electrical coupling as ground terminal
The GND routing gaskets for connecing two chips in encapsulating structure make the GND routing gaskets of described two chips be grounded, and enable conducting wire
Frame can have a spare pin, so that the CS pins on the lead frame are increased as two by original one with electricity respectively
Property coupling two chips CS routing gaskets.Therefore, twin-core chip package of the invention can be before not increasing pin number
It puts, provides two CS pins to avoid the device conflict problem between two chips, and have pin number few and manufacture
Advantage at low cost.
Description of the drawings
Fig. 1 is the top view and pin setting figure for the single die package for illustrating SPI memory chips；
Fig. 2 is the top view and pin setting figure for the twin-core chip package for illustrating known SPI memory chips；
Fig. 3 A are the side view of the twin-core chip package of the first embodiment of the present invention；
Fig. 3 B and Fig. 3 C are the packaging and routing schematic diagram of the twin-core chip package shown in Fig. 3 A；
Fig. 4 A are the side view of the twin-core chip package of the second embodiment of the present invention；
Fig. 4 B and Fig. 4 C are the packaging and routing schematic diagram of twin-core chip package shown in Fig. 4 A；And
Fig. 5 is the top view and pin setting figure of the twin-core chip package of the present invention.
【Symbol description】
100 twin-core chip packages (first embodiment)
110 exposed pads
120a, 120b chip
121a, 121b CS routing gaskets
122a, 122b GND routing gaskets
First, second, third and fourth, five, six routing gasket of 123a, 123b
130 lead frames
131a, 131b CS pins
133 first, second, third and fourth, five, six pins
141a, 141b CS conducting wires
142a, 142b GND conducting wires
First, second, third and fourth, five, six conducting wire of 143a, 143b
150 separation layers
11 printed circuit boards (PCB)
12 ground connection cooling pads
13 scolding tin
200 twin-core chip packages (second embodiment)
210 exposed pads
The first chips of 220a
The first CS routing gaskets of 221a
The first GND routing gaskets of 222a
The second chips of 220b
The 2nd CS routing gaskets of 221b
The 2nd GND routing gaskets of 222b
230 lead frames
The first CS pins of 231a
The 2nd CS pins of 231b
241a, 241b CS conducting wires
242a, 242b GND conducting wires
250 separation layers
21 printed circuit boards (PCB)
22 ground connection cooling pads
23 scolding tin
The single die package of 320 SPI memory chips
321 CS pins
322 GND pins
The twin-core chip package of 420 known SPI memory chips
421a, 421b CS pins
422 GND pins
Specific implementation mode
The following contents will arrange in pairs or groups schema, and the technology contents of the present invention are illustrated by particular specific embodiment, are familiar with this skill
The personage of art can be understood other advantages and effect of the present invention easily by content disclosed in the present specification.The present invention also can be by
It is implemented or is applied by other different specific embodiments.The various details in this specification can also be based on different viewpoints and answer
With, under without departing from the spirit of the present invention, the various modifications of progress and change.Especially, the ratio of various components is closed in schema
System and relative position only have exemplary use, not represent the actual state that the present invention is implemented.
Please refer to the dual chip encapsulation knot that Fig. 3 A and Fig. 3 B and Fig. 3 C, wherein Fig. 3 A are the first embodiment of the present invention
The side view of structure 100；Fig. 3 B and Fig. 3 C are the packaging and routing schematic diagram of the twin-core chip package 100 shown in Fig. 3 A.Wherein, originally
The twin-core chip package 100 of invention is suitable for Serial Flash, Serial SRAM or the two kinds of difference interfaces Serial memories
Combination.
As shown in Figure 3A, in first embodiment, twin-core chip package 100 is set on a printed circuit board 11, print
Printed circuit board 11 has a ground connection cooling pad 12, specifically, ground connection cooling pad 12 is set on printed circuit board 11 simultaneously electrically
The ground terminal (being unillustrated) of printed circuit board 12 is coupled to be grounded.Wherein, twin-core chip package 100 includes an exposed pad
110, two chips 120a and 120b, a lead frame 130, two CS conducting wires 141a, 141b, two GND conducting wires 142a, 142b,
And first to the 6th conducting wire each two articles of 143a, 143b.
Exposed pad (exposed pad) 110 and ground connection 12 electric property coupling of cooling pad, specifically, as shown in Figure 3A, it is exposed
Pad 110 is placed on ground connection cooling pad 12 by scolding tin 13 to be grounded.
Two chip 120a, 120b are set on exposed pad 110, wherein chip 120a and chip 120b be SPI chips,
Dual-SPI chips or Quad-SPI chips, and there is a separation layer 150 between chip 120a and chip 120b, enable chip
120a and chip 120b can be set to stacked manner on exposed pad 110, to reduce overall package volume.Each chip 120a, 120b
It is respectively provided with CS routing gaskets 121a, a 121b, GND routing gaskets 122a, a 122b, one first routing gasket, one second dozen
Line gasket, a third routing gasket, one the 4th routing gasket, one the 5th routing gasket and one the 6th routing gasket are (for simplification figure
Target label symbol, in this case, first, second, third and fourth, five, the six routing gaskets of two chips 120a, 120b respectively with
123a and 123b gives unifying identifier), wherein first, second, third and fourth, five, six routing gasket 123a, 123b are respectively DO
(IO1) routing gasket, WP (IO2) routings gasket, DI (IO0) routings gasket, CLK routings gasket, HOLD (IO3) routings gasket,
VCC routing gaskets, the setting title of right routing gasket and setting sequence be not limited thereto, visual actual demand change with
And adjustment.
Lead frame 130 is equipped with eight pins, wherein comprising there are two CS pins 131a, 131b and one first pin, one
Second pin, a third pin, one the 4th pin, one the 5th pin and one the 6th pin (for the label symbol of simplified, in
In this case, first, second, third and fourth, five, six pin above-mentioned gives unifying identifier with 133), wherein first, second, third and fourth, five,
Six pins 133 are set corresponding to the type of first, second, third and fourth, five, six routing the gasket 123a, 123b of chip 120a, 120b
It sets, respectively DO (IO1) pin, WP (IO2) pin, DI (IO0) pin, CLK pin, HOLD (IO3) pin, VCC pin.It needs
Illustrate, the setting title of pin 133 and setting sequence are not limited thereto, and visual actual demand is changed and adjusted
It is whole.
Furthermore in practical application, CS routings gasket 121a, 121b above-mentioned are that low level starts, on lead frame 130 it
Two CS pins 121a, 121b are also that low level starts.
Please refer to routing schematic diagram shown in Fig. 3 B and Fig. 3 C, wherein distinguish electric property coupling core in the both ends of GND conducting wires 142a
The GND routing gasket 122a of piece 120a with exposed pad 110 so that the GND routing gaskets of chip 120a are grounded, and GND conducting wires 142b
Both ends difference electric property coupling chip 120b GND routing gasket 122b with exposed pad 110 so that the GND wire pads of chip 120b
Piece is grounded.Thereby, the present invention is used and is vacated on original lead frame 130 it is not necessary that GND pin is specially arranged on lead frame 130
GND pin to realize under the premise of not increasing pin number (i.e. totally 8 pins) as the 2nd CS pins to enable conducting wire
CS pin numbers on frame 130 increase to two (i.e. the CS1 pins of twin-core chip package shown in Fig. 5 and CS2 pins), to divide
The CS routing gaskets of other electric property coupling two chips 120a, 120b.
Specifically, twin-core chip package 100 includes two CS conducting wires 141a, 141b, wherein CS conducting wires 141a's
Distinguish the CS routing gasket 121a's of electric property coupling chip 120a and CS1 pins 131a, the CS conducting wire 141b of lead frame 130 in both ends
The CS2 pin 131b of the CS routing gasket 121b and lead frame 130 of electric property coupling chip 120b are distinguished at both ends, it should be noted that,
Both CS1 pins 131a and CS2 pins 131b of lead frame 130 are interchangeable, also that is, by the CS routing gaskets 121a of chip 120a
The CS2 pin 131b of lead frame 130 are electrically coupled to, and the CS routing gaskets 121b of chip 120b is electrically coupled to lead frame
130 CS1 pins 131a, the specific practice is depending on actual demand.By by two CS wire pads of two chips 120a, 120b
Piece 121a, 121b are electrically coupled to two different CS pins 131a, 131b to carry out signal differentiation, so as to avoid core respectively
Device conflict between piece 120a and chip 120b.
Furthermore please continue to refer to Fig. 3 B and Fig. 3 C, in two first conducting wires 143a, 143b, the two of the first conducting wire 143a
The first pin 133 of the first routing gasket 123a and lead frame 130 of end difference electric property coupling chip 120a, the first conducting wire 143b
Both ends difference electric property coupling chip 120b the first routing gasket 123b and lead frame 130 the first pin 133, also that is, core
Two routing gaskets with same names, i.e. DO (IO1) routing gasket are electrically coupled to and lead on piece 120a and chip 120b
DI (IO0) pin on coil holder 130.It is same as above, the second of the both ends difference electric property coupling chip 120a of the second conducting wire 143a
The second pin 133 of routing gasket 123a and lead frame 130, the both ends difference electric property coupling chip 120b's of the second conducting wire 143b
The second pin 133 of second routing gasket 123b and lead frame 130, i.e. chip 120a and two WP (IO2) on chip 120b
Routing gasket is electrically coupled to WP (IO2) pin on lead frame 130；Distinguish electric property coupling core in the both ends of privates 143a
Distinguish electrical coupling in the both ends of the third pin 133 of the third routing gasket 123a and lead frame 130 of piece 120a, privates 143b
Connect the third pin 133 of the third routing gasket 123b and lead frame 130 of chip 120b, i.e. on chip 120a and chip 120b
Two DI (IO0) routing gaskets are electrically coupled to DI (IO0) pin on lead frame 130；The both ends of privates 143a point
The 4th pin 133 of the 4th routing gasket 123a and lead frame 130 of other electric property coupling chip 120a, the two of privates 143b
The 4th pin 133 of end the 4th routing gasket 123b and lead frame 130 of electric property coupling chip 120b respectively, i.e. chip 120a and
Two CLK routings gaskets on chip 120b are electrically coupled to the CLK pin on lead frame 130；The two of 5th conducting wire 143a
The 5th pin 133 of the 5th routing gasket 123a and lead frame 130 of end difference electric property coupling chip 120a, the 5th conducting wire 143b
Both ends difference electric property coupling chip 120b the 5th routing gasket 123b and lead frame 130 the 5th pin 133, i.e. chip
The HOLD (IO3) that 120a is electrically coupled to two HOLD (IO3) routing gaskets on chip 120b on lead frame 130 draws
Foot；And the of the 6th routing gasket 123a of the both ends difference electric property coupling chip 120a of the 6th conducting wire 143a and lead frame 130
Six pins 133, the 6th routing gasket 123b and lead frame 130 of the both ends difference electric property coupling chip 120b of the 6th conducting wire 143b
The 6th pin 133, i.e. two VCC routings gaskets on chip 120a and chip 120b are electrically coupled on lead frame 130
VCC pin.
Therefore, the twin-core chip package 100 that the first embodiment of the present invention is provided can not increase pin number
Under the premise of, CS pins are increased as two by one with two chips of electric property coupling are to carry out signal differentiation respectively, to avoid
Device conflict between two chips.
Please continue to refer to Fig. 4 A and Fig. 4 B and Fig. 4 C, wherein Fig. 4 A are that the dual chip of the second embodiment of the present invention encapsulates
The side view of structure 200；Fig. 4 B and Fig. 4 C are the packaging and routing schematic diagram of the twin-core chip package 200 shown in Fig. 4 A.With
One embodiment is identical, and the twin-core chip package 200 of the present embodiment is similarly provided on a printed circuit board 21, and printed circuit
There is plate 21 a ground connection cooling pad 22, specific set-up mode to please refer to the description of first embodiment.The twin-core of the present embodiment
Chip package 200 mainly includes an exposed pad 210, one first chip 220a, one second chip 220b and a lead frame
230。
Exposed pad 210 and ground connection 22 electric property coupling of cooling pad, as shown in Figure 4 A, the exposed pad 210 of the present embodiment is equally logical
Scolding tin 23 is crossed to be placed on ground connection cooling pad 22 with ground connection.
First chip 220a has one the oneth CS routing gasket 221a and one the oneth GND routing gaskets 222a；Second chip
220b has one the 2nd CS routing gasket 221b and one the 2nd GND routing gaskets 222b, wherein in the first chip 220a and second
An insulating layer 250 (as shown in Figure 4 A) is provided between chip 220b again, enables the first chip 220a and the second chip 220b can be with
Stacked manner is set on exposed pad 210, to reduce the volume of overall package.In practical application, the first chip 220a and second
Chip 220b can be SPI chips, Dual-SPI chips or Quad-SPI chips at least eight routing gaskets
Furthermore lead frame 230 has one the oneth CS pins 231a and one the 2nd CS pin 231b, in an embodiment application
In, the lead frame 230 of twin-core chip package has eight pins (please referring to Fig. 5) altogether.
Incorporated by reference to reference to figure 4B and Fig. 4 C, in twin-core chip package 200, the first GND routings of the first chip 220a
The 2nd GND routing gaskets 222b of gasket 222a and the second chip 220b is respectively by GND conducting wire 242a and GND conducting wires 242b electricity
Property coupling exposed pad 210 with ground connection, and the first CS routing gasket 221a of the first chip 220a pass through the electrical couplings of CS conducting wires 241a
The 2nd CS routing gasket 221b for meeting the first CS pin 231a, the second chip 220b of lead frame 230 pass through CS conducting wires 241b electricity
Property coupling lead frame 230 the 2nd CS pins 231b.When practical operation, the first CS routing gasket 221a and the 2nd CS wire pads
Piece 221b starts for low level, and the first CS pins 231a and the 2nd CS pins 231b is also that low level starts.It only, can be according to reality
Border demand and design the first CS routing gaskets 221a, the 2nd CS routing gaskets 221b, the first CS pins 231a and the 2nd CS
Pin 231b starts for high levle.
From the foregoing, it will be observed that the twin-core chip package 200 that the second embodiment of the present invention is provided can also not increase pin
Under the premise of quantity, it is that two (i.e. the first CS pins and one the 2nd CS pins) is electrical with difference that CS pins are increased by one
The first chip and the second chip are coupled to carry out signal differentiation, so as to avoid the device conflict between two chips.
In summary, twin-core chip package of the invention will be sealed by the way that exposed pad is arranged, and as ground terminal
The GND routing gaskets of two chips in assembling structure are electrically coupled to the exposed pad to be grounded, and vacate the original GND of lead frame
Pin and as the 2nd CS pins so that it is two that the CS pins on the lead frame are increased by original one, with point
The CS routings gasket of the other described two chips of electric property coupling is distinguished with the signal for two chips, so as to make encapsulation tie
Structure avoids the device conflict between two chips under the premise of eight pins, and has pin number few and be manufactured into
This low advantage.
The principle of the present invention and effect is only illustrated in above-described embodiment, and is not intended to limit the present invention.It is any to be familiar with
The personage of technique can be without prejudice under spirit and scope of the invention, and modifications and changes are made to the above embodiments.Cause
This, the rights protection scope of the present invention should be as listed by scope of the present invention patent.
Claims (10)
1. a kind of twin-core chip package is set to a printed circuit board, the printed circuit board has a ground connection cooling pad,
It is characterized in that：The twin-core chip package includes：
One exposed pad, the exposed pad and the ground connection cooling pad electric property coupling；
Two chips, described two chips are set on the exposed pad, and each chip is respectively provided with a CS routings gasket, one
GND routings gasket, one first routing gasket, one second routing gasket, a third routing gasket, one the 4th routing gasket, one
Five routing gaskets and one the 6th routing gasket；
One lead frame, the lead frame are equipped with eight pins, and eight pins include two CS pins, one first pin, one
Second pin, a third pin, one the 4th pin, one the 5th pin and one the 6th pin；
Two CS conducting wires, the CS routings gasket and the conducting wire of both ends difference each chip of electric property coupling of each CS conducting wires
One of two CS pins of frame；
Two GND conducting wires, each GND conducting wires both ends difference each chip of electric property coupling GND routings gasket with it is described
Exposed pad；
Two first conducting wires, the first routing gasket of both ends difference each chip of electric property coupling of each first conducting wire and institute
State the first pin of lead frame；
Two second conducting wires, the second routing gasket of both ends difference each chip of electric property coupling of each second conducting wire and institute
State the second pin of lead frame；
Two privates, the third routing gasket of both ends difference each chip of electric property coupling of each privates and institute
State the third pin of lead frame；
Two privates, the 4th routing gasket of both ends difference each chip of electric property coupling of each privates and institute
State the 4th pin of lead frame；
Two article of the 5th conducting wire, the 5th routing gasket of both ends difference each chip of electric property coupling of each 5th conducting wire and institute
State the 5th pin of lead frame；And
Two article of the 6th conducting wire, the 6th routing gasket of both ends difference each chip of electric property coupling of each 6th conducting wire and institute
State the 6th pin of lead frame.
2. twin-core chip package as described in claim 1, it is characterised in that：Described two chips are SPI chips, Dual-
SPI chips or Quad-SPI chips.
3. twin-core chip package as claimed in claim 2, it is characterised in that：The twin-core chip package is used for Serial
The combination of Flash, Serial SRAM or the two kinds of difference interfaces Serial memories.
4. twin-core chip package as claimed in claim 3, it is characterised in that：First to the 6th routing of described two chips
Gasket is respectively DO (IO1) routings gasket, WP (IO2) routings gasket, DI (IO0) routings gasket, CLK routings gasket, HOLD
(IO3) the first to the 6th pin of routing gasket, VCC routing gaskets, the lead frame corresponds to DO (IO1) pin, WP respectively
(IO2) pin, DI (IO0) pin, CLK pin, HOLD (IO3) pin, VCC pin.
5. twin-core chip package as claimed in claim 3, it is characterised in that：Further include a separation layer, is set to described two
Between a chip, enable described two chips that can be set on the exposed pad with stacked manner.
6. a kind of twin-core chip package is set to a printed circuit board, the printed circuit board has a ground connection cooling pad,
It is characterized in that：The twin-core chip package includes：
One exposed pad, the exposed pad and the ground connection cooling pad electric property coupling；
One first chip has one the oneth CS routings gasket and one the oneth GND routing gaskets；
One second chip has one the 2nd CS routings gasket and one the 2nd GND routing gaskets；And
One lead frame has one the oneth CS pins and one the 2nd CS pins；Wherein：
First GND routings gasket of first chip distinguishes electric property coupling with the 2nd GND routing gaskets of second chip
The exposed pad, the first CS pins of lead frame described in the first CS routing gasket electric property couplings of first chip, described
2nd CS pins of lead frame described in 2nd CS routing gasket electric property couplings of two chips.
7. twin-core chip package as claimed in claim 6, it is characterised in that：First chip and the second chip be with
SPI chips, Dual-SPI chips or the Quad-SPI chips of at least eight routing gaskets.
8. twin-core chip package as claimed in claim 7, it is characterised in that：The lead frame has eight pins.
9. twin-core chip package as claimed in claim 6, it is characterised in that：Further include an insulating layer, is set to described
Between one chip and second chip, enable first chip and second chip that can be set to stacked manner described exposed
On pad.
10. twin-core chip package as claimed in claim 6, it is characterised in that：The first CS routings gasket and described the
Two CS routing gaskets start for low level；The first CS pins start with the 2nd CS pins for low level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710102251.4A CN108511427A (en) | 2017-02-24 | 2017-02-24 | Twin-core chip package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710102251.4A CN108511427A (en) | 2017-02-24 | 2017-02-24 | Twin-core chip package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108511427A true CN108511427A (en) | 2018-09-07 |
Family
ID=63373626
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710102251.4A Pending CN108511427A (en) | 2017-02-24 | 2017-02-24 | Twin-core chip package |
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| Country | Link |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5703828A (en) * | 1992-10-02 | 1997-12-30 | Samsung Electronics Co Ltd | Semiconductor memory |
| US20120146245A1 (en) * | 2008-09-19 | 2012-06-14 | Renesas Electronics Corporation | Semiconductor device |
| US20130133193A1 (en) * | 2011-11-28 | 2013-05-30 | Mediatek Singapore Pte. Ltd. | Surface mount technology process for advanced quad flat no-lead package process and stencil used therewith |
| US20150332747A1 (en) * | 2014-05-15 | 2015-11-19 | Winbond Electronics Corporation | Methods of and Apparatus for Determining Unique Die Identifiers for Multiple Memory Die Within a Common Package |
-
2017
- 2017-02-24 CN CN201710102251.4A patent/CN108511427A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5703828A (en) * | 1992-10-02 | 1997-12-30 | Samsung Electronics Co Ltd | Semiconductor memory |
| US20120146245A1 (en) * | 2008-09-19 | 2012-06-14 | Renesas Electronics Corporation | Semiconductor device |
| US20130133193A1 (en) * | 2011-11-28 | 2013-05-30 | Mediatek Singapore Pte. Ltd. | Surface mount technology process for advanced quad flat no-lead package process and stencil used therewith |
| US20150332747A1 (en) * | 2014-05-15 | 2015-11-19 | Winbond Electronics Corporation | Methods of and Apparatus for Determining Unique Die Identifiers for Multiple Memory Die Within a Common Package |
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