CN212695148U - Three-dimensional multi-chip parallel packaging structure - Google Patents
Three-dimensional multi-chip parallel packaging structure Download PDFInfo
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- CN212695148U CN212695148U CN202021585598.2U CN202021585598U CN212695148U CN 212695148 U CN212695148 U CN 212695148U CN 202021585598 U CN202021585598 U CN 202021585598U CN 212695148 U CN212695148 U CN 212695148U
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Abstract
Three-dimensional multi-chip parallel packaging structure. Relate to semiconductor device technical field, concretely relates to semiconductor device of many diode chip parallel structure. The three-dimensional multi-chip parallel structure is provided, and the overcurrent capacity of a device is increased while the mounting occupied area is not increased. The wire jumper comprises a frame, chips and wire jumpers and is characterized in that the frame comprises a frame A and a frame B, wherein a chip layer 1 and a chip layer 2 … … are sequentially stacked on the frame B from bottom to top, and n is more than or equal to 2; the polarities of the opposite surfaces of the adjacent chip layers are consistent, and the sum of the jumper Ak and the jumper Bj is consistent with the layer number of the chip layers. n is a number. The utility model discloses it changes into the three-dimensional with the multicore piece by the plane to spread to pile up, changes the multicore piece series connection encapsulation into the parallelly connected encapsulation of multicore piece, reduces the installation area occupied of packaging body from this. In addition, the three-dimensional multi-chip parallel structure can set different overcurrent capacity and voltage resistance capacity, and meets the use requirements of different application scenes.
Description
Technical Field
The utility model relates to a semiconductor device technical field, concretely relates to semiconductor device of parallelly connected structure of multi-diode chip.
Background
With the development of the electronic information industry, products are continuously miniaturized and miniaturized, which has certain requirements on the size of semiconductor device packages. The conventional multi-chip package can only spread chips on a plane and then be connected in series by a jumper wire. The mounting occupation area of the semiconductor device in the product is increased, and a plurality of limitations exist in practical application.
Disclosure of Invention
The utility model discloses to above problem provides one kind when not increasing installation area occupied, increases the three-dimensional multicore piece parallel structure of device ability of overflowing.
The technical scheme of the utility model is that: the three-dimensional multi-chip parallel structure comprises a frame, chips and jumper wires, and is characterized in that the frame comprises a frame A and a frame B, wherein a chip layer 1 and a chip layer 2 … … chip layer n are sequentially stacked on the frame B from bottom to top, and n is not less than 2; the polarity of the opposing faces of adjacent chip layers is the same,
the top surface of the odd layer of the chip layer is provided with a jumper Ak connected with the frame A, wherein k is 1, 3 or 5 … … n;
the top surface of the even layer of the chip layer is provided with a jumper Bj connected with the frame B; j is 2, 4, 6 … … n;
the sum of the jumper Ak and the jumper Bj is consistent with the layer number of the chip layer. n is a number.
M chip monomers are superposed in each chip layer in a series connection mode, and m is more than or equal to 1. m is a number.
The thickness of the tin layer used for connecting the frame, the chip and the jumper wire is 0.05-0.07 mm. The thickness of the tin layer is required to ensure that the frame, the chips and the jumper wire are firmly connected, and the height of the three-dimensional multi-chip parallel structure is ensured to be as small as possible without occupying too much space.
The utility model discloses it changes into the three-dimensional with the multicore piece by the plane to spread to pile up, changes the multicore piece series connection encapsulation into the parallelly connected encapsulation of multicore piece, reduces the installation area occupied of packaging body from this. In addition, the three-dimensional multi-chip parallel structure can set different overcurrent capacity and voltage resistance capacity, and meets the use requirements of different application scenes.
Drawings
Figure 1 is a schematic structural view of the present invention,
figure 2 is a schematic structural view of a first embodiment of the present invention,
figure 3 is a schematic structural view of a second embodiment of the present invention,
figure 4 is a circuit schematic of a first embodiment of the invention,
fig. 5 is a schematic circuit diagram of a second embodiment of the present invention.
In the figure, 1 is a frame, 11 is a frame A, 12 is a frame B, 2 is a chip, 3 is a jumper, and 4 is a tin layer.
Detailed Description
The present invention is further described with reference to fig. 1-5, which includes a frame 1, a chip 2 and a jumper wire 3, wherein the frame includes a frame a11 and a frame B12, the frame B12 is stacked with a chip layer 1 and a chip layer 2 … …, and n is greater than or equal to 2; the polarity of the opposing faces of adjacent chip layers is the same,
the top surface of the odd layer of the chip layer is provided with a jumper Ak connected with the frame A, wherein k is 1, 3 or 5 … … n;
the top surface of the even layer of the chip layer is provided with a jumper Bj connected with the frame B; j is 2, 4, 6 … … n;
the sum of the jumper Ak and the jumper Bj is consistent with the layer number of the chip layer. n is a number.
M chip monomers are superposed in each chip layer according to a series connection mode, and m is more than or equal to 1. m is a number.
The thickness of the tin layer 4 used for connecting the frame 1, the chip 2 and the jumper 3 is 0.05-0.07 mm. The thickness of the tin layer 4 ensures that the frame 1, the chip 2 and the jumper wire 3 are firmly connected, and also ensures that the height of the three-dimensional multi-chip parallel structure is as small as possible and does not occupy too much space.
The present invention is not limited to the above embodiments, and based on the technical solutions disclosed in the present invention, those skilled in the art can make some replacements and transformations for some technical features without creative labor according to the disclosed technical contents, and these replacements and transformations are all within the protection scope of the present invention.
Claims (3)
1. The three-dimensional multi-chip parallel packaging structure comprises a frame, chips and jumper wires, and is characterized in that the frame comprises a frame A and a frame B, wherein a chip layer 1 and a chip layer 2 … …, namely a chip layer n, are sequentially stacked on the frame B from bottom to top, and n is not less than 2; the polarity of the opposing faces of adjacent chip layers is the same,
the top surface of the odd layer of the chip layer is provided with a jumper Ak connected with the frame A, wherein k is 1, 3 or 5 … … n;
the top surface of the even layer of the chip layer is provided with a jumper Bj connected with the frame B; j is 2, 4, 6 … … n;
the sum of the jumper Ak and the jumper Bj is consistent with the layer number of the chip layer.
2. The three-dimensional multi-chip parallel packaging structure of claim 1, wherein m chip monomers are stacked in each chip layer in a series connection manner, wherein m is greater than or equal to 1.
3. The three-dimensional multi-chip parallel package structure according to claim 1, wherein the thickness of the tin layer used for connecting the frame, the chips and the jumper wires is 0.05-0.07 mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021585598.2U CN212695148U (en) | 2020-08-03 | 2020-08-03 | Three-dimensional multi-chip parallel packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021585598.2U CN212695148U (en) | 2020-08-03 | 2020-08-03 | Three-dimensional multi-chip parallel packaging structure |
Publications (1)
| Publication Number | Publication Date |
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| CN212695148U true CN212695148U (en) | 2021-03-12 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202021585598.2U Active CN212695148U (en) | 2020-08-03 | 2020-08-03 | Three-dimensional multi-chip parallel packaging structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111755427A (en) * | 2020-08-03 | 2020-10-09 | 扬州扬杰电子科技股份有限公司 | Three-dimensional multi-chip parallel packaging structure |
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2020
- 2020-08-03 CN CN202021585598.2U patent/CN212695148U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111755427A (en) * | 2020-08-03 | 2020-10-09 | 扬州扬杰电子科技股份有限公司 | Three-dimensional multi-chip parallel packaging structure |
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