CN108447829B - Package structure and method for fabricating the same - Google Patents
Package structure and method for fabricating the same Download PDFInfo
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- CN108447829B CN108447829B CN201710120094.XA CN201710120094A CN108447829B CN 108447829 B CN108447829 B CN 108447829B CN 201710120094 A CN201710120094 A CN 201710120094A CN 108447829 B CN108447829 B CN 108447829B
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- 238000000034 method Methods 0.000 title claims description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 claims abstract description 18
- 238000004806 packaging method and process Methods 0.000 claims abstract description 10
- 238000005253 cladding Methods 0.000 claims description 27
- 239000008393 encapsulating agent Substances 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 9
- 230000017525 heat dissipation Effects 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 36
- 239000004065 semiconductor Substances 0.000 description 15
- 229910000679 solder Inorganic materials 0.000 description 11
- 238000000465 moulding Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000011247 coating layer Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- SZUVGFMDDVSKSI-WIFOCOSTSA-N (1s,2s,3s,5r)-1-(carboxymethyl)-3,5-bis[(4-phenoxyphenyl)methyl-propylcarbamoyl]cyclopentane-1,2-dicarboxylic acid Chemical compound O=C([C@@H]1[C@@H]([C@](CC(O)=O)([C@H](C(=O)N(CCC)CC=2C=CC(OC=3C=CC=CC=3)=CC=2)C1)C(O)=O)C(O)=O)N(CCC)CC(C=C1)=CC=C1OC1=CC=CC=C1 SZUVGFMDDVSKSI-WIFOCOSTSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229940126543 compound 14 Drugs 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
A packaging structure and a manufacturing method thereof are provided, wherein a covering part is connected to a bearing part to cover at least one electronic element on the bearing part, and the bearing part is combined to a metal frame by a plurality of conductive elements, so that the design of the covering part improves the heat dissipation efficiency of the packaging structure and provides an EMI shielding effect for the electronic element.
Description
Technical Field
The present invention relates to a package structure, and more particularly, to a stacked package structure and a method for fabricating the same.
Background
With the rapid development of portable electronic products in recent years, the development of various related products is also oriented to high density, high performance, light weight, thin weight, short weight and small size, and therefore, various integrated multi-chip packaging modes are developed in the industry to meet the requirements of light weight, small size and high density of electronic products.
Fig. 1 is a schematic cross-sectional view of a conventional semiconductor package 1. As shown in fig. 1, in the manufacturing method of the semiconductor package structure 1, the semiconductor element 11 and the passive element 11 'are disposed on the upper side and the lower side of a substrate 10, and then the encapsulant 14 encapsulates the semiconductor element 11 and the passive element 11', and the contact (I/O)100 of the substrate 10 is exposed to the encapsulant 14, and then a plurality of solder balls 13 are formed on the contact 100, so that in the subsequent process, the semiconductor package structure 1 is connected to an electronic device (not shown) such as a circuit board or another circuit board through the solder balls 13.
However, in the conventional semiconductor package 1, since the molding range of the molding compound 14 is reduced to expose the contacts 100, a molding die of a specific size is required depending on the size of the semiconductor package 1, and thus a single molding die cannot be applied to various sizes of the semiconductor package 1, thereby increasing the production cost.
Moreover, the semiconductor devices 11 and the passive devices 11 'are encapsulated in the encapsulant 14, so that the heat dissipation effect of the semiconductor devices 11 and the passive devices 11' is not good.
Therefore, how to overcome the various problems of the prior art has become an issue to be solved.
Disclosure of Invention
In view of the above-mentioned shortcomings in the prior art, the present invention provides a package structure and a method for fabricating the same, which can improve the heat dissipation efficiency of the package structure and provide an EMI shielding effect for the electronic component.
The packaging structure of the invention comprises: a carrier; the electronic component is connected to the bearing piece; a plurality of conductive elements connected to the carrier; a cover member which is disposed on the carrier member and covers the electronic component; and a metal frame including a plurality of electrical contact pads for the plurality of conductive elements to be coupled to the plurality of electrical contact pads.
The invention also provides a manufacturing method of the packaging structure, which comprises the following steps: providing an electronic assembly comprising a bearing member, an electronic element and a plurality of conductive elements, wherein the electronic element and the plurality of conductive elements are connected on the bearing member; placing a cover on the carrier to cover the electronic device; and bonding the electronic component to a metal frame comprising a plurality of electrical contact pads through the conductive element, so that the plurality of conductive elements are connected to the plurality of electrical contact pads.
In the foregoing package structure and the method for fabricating the same, the metal frame is a lead frame.
In the foregoing package structure and the method for fabricating the same, the metal frame further includes a plate body corresponding to the electronic component, and the plurality of electrical contact pads are disposed around the plate body. The plate is bonded to the covering member.
In the package structure and the method for fabricating the same, the shielding member is bonded to the electronic device through an interposer.
In the foregoing package structure and the manufacturing method thereof, a supporting member is further included, and the supporting member is connected to the carrier, so that the covering member abuts against the supporting member. For example, the supporting member is disposed between two electronic components, and the supporting member is grounded.
In the foregoing package structure and the method for fabricating the same, a covering layer is further included, and is formed between the carrier and the metal frame to cover the covering member and the conductive elements, and expose the electrical contact pads out of the covering layer. For example, the covering exposes the coating or does not expose the coating; alternatively, the electrical contact pad is exposed out of the side surface of the coating layer.
In the package structure and the method for manufacturing the same, the carrier has a first side and a second side opposite to each other, and the electronic component includes a first electronic component and a second electronic component respectively attached to the first side and the second side, so that the cover is attached to the second side and covers the second electronic component. For example, the first side of the carrier is formed with a cladding; alternatively, the metal is arranged on the first side and/or the second side of the bearing part.
In addition, in the package structure and the method for manufacturing the same, the covering member is electrically connected to the carrier. The cover covers a plurality of the electronic components. The covering member is disposed between the two electronic components. The covering member is grounded.
In view of the above, the package structure and the manufacturing method thereof of the present invention mainly combine the electronic component with the metal frame including the plurality of electrical contact pads through the plurality of conductive elements, so that the electrical contact pads of the metal frame serve as electrical contacts.
Furthermore, the design of arranging the shielding part for covering the electronic element on the bearing part can improve the heat dissipation efficiency of the packaging structure and provide an EMI shielding effect for the electronic element.
Drawings
FIG. 1 is a cross-sectional view of a conventional semiconductor package structure;
fig. 2A to 2C are schematic cross-sectional views illustrating a method for fabricating a package structure according to the present invention;
FIG. 3A is a schematic cross-sectional view of the subsequent process corresponding to FIG. 2C;
FIG. 3B is a schematic cross-sectional view of another embodiment corresponding to FIG. 3A;
FIG. 3C is a schematic cross-sectional view of another embodiment corresponding to FIG. 3A;
FIG. 4 is a schematic cross-sectional view of another embodiment corresponding to FIG. 2C;
FIG. 5A is a schematic bottom view corresponding to FIG. 2C; and
fig. 5B is a schematic diagram of another embodiment corresponding to fig. 5A.
Description of the symbols:
1 semiconductor package structure
10 base plate
100 contact
11 semiconductor element
11' passive element
13 solder ball
14 packaging adhesive
2,3, 3', 4 packaging structure
2a electronic component
20 load bearing member
20a first side
20b second side
200 circuit layer
21, 21', 41 first electronic component
210,220 conductive bump
22,42 second electronic component
221 primer
23, 23' conductive element
24 first coating
25, 25', 45 metal frame
250 electric contact pad
251 board body
26 second coating layer
26a first surface
26b second surface
26c side surface
27,47 support
28 cover member
280,29 interposer.
Detailed Description
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein.
It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for understanding and reading the contents disclosed in the specification, and are not used for limiting the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modifications, ratio relationship changes or size adjustments should still fall within the scope of the technical contents disclosed in the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "above", "first", "second", and "a" as used herein are for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship may be made without substantial technical changes.
Fig. 2A to fig. 2C are schematic cross-sectional views illustrating a manufacturing method of the package structure 2 according to the present invention.
As shown in fig. 2A, an electronic assembly 2A is provided, which includes a carrier 20, and first electronic components 21, 21', a second electronic component 22, a conductive component 23 and a supporting member 27 disposed on the carrier 20.
In the present embodiment, the carrier 20 is, for example, a package substrate (substrate) having a core layer and a circuit structure or a coreless (circuit) structure, and the carrier 20 has a plurality of circuit layers 200, such as a fan-out (fan out) redistribution layer (RD L), it should be understood that the carrier 20 may also be other carrier units for carrying electronic components such as chips, for example, a lead frame (leadframe), and the invention is not limited thereto.
The first electronic component 21, 21' is disposed on the first side 20a of the carrier 20. In the present embodiment, the first electronic component 21,21 ' is an active component (e.g. 21 '), a passive component (e.g. 21 '), or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, or an inductor. For example, the first electronic component 21 is disposed on the circuit layer 200 in a flip-chip manner through a plurality of conductive bumps 210 such as solder material and electrically connected to the circuit layer 200; alternatively, the first electronic component 21 can be electrically connected to the circuit layer 200 by wire bonding via a plurality of bonding wires (not shown); alternatively, the first electronic component 21' may directly contact the circuit layer 200. However, the manner of electrically connecting the first electronic components 21, 21' to the carrier 20 is not limited to the above.
After the first electronic component 21,21 'is disposed on the carrier 20, a first coating layer 24 for coating the first electronic component 21, 21' may be further formed. In the present embodiment, the first cladding layer 24 is formed of Polyimide (PI), dry film (dry film), epoxy resin (epoxy), or molding compound (molding compound). In other embodiments, the electronic component 2a may not form the first cladding layer 24.
After the first cladding layer 24 is formed, the second electronic element 22, the conductive element 23 and the supporting element 27 may be disposed on the carrier 20.
The second electronic component 22 is disposed on the second side 20b of the carrier 20. In the present embodiment, the second electronic component 22 is an active component, such as a semiconductor chip, a passive component, such as a resistor, a capacitor, or an inductor, or a combination thereof. For example, the second electronic component 22 is flip-chip mounted on the circuit layer 200 via a plurality of conductive bumps 220, such as solder material; alternatively, the second electronic component 22 can be electrically connected to the circuit layer 200 by wire bonding (not shown). However, the manner of electrically connecting the second electronic component 22 to the carrier 20 is not limited to the above.
The conductive elements 23 are disposed on the circuit layer 200 on the second side 20b of the carrier 20. In the present embodiment, the conductive element 23 is a solder ball (solder ball), but is not limited to the above.
The supporting member 27 is disposed on the second side 20b of the supporting member 20 and is located around the second electronic component 22. In the present embodiment, the supporting member 27 is a metal frame (or other frame) and is electrically connected (e.g., grounded) to the carrier 20, and the conductive element 23 is located outside the supporting member 27.
As shown in fig. 2B, an underfill 221 is formed between the second electronic component 22 and the second side 20B of the carrier 20 to encapsulate the conductive bumps 220. Then, a cover 28 is disposed on the second side 20b of the carrier 20 to cover the second electronic component 22.
In the present embodiment, the covering member 28 is a metal cover that abuts against the supporting member 27 to facilitate mounting and electrical connection (e.g., grounding) of the carrier 20, and is bonded to the second electronic component 22 through an interposer 280. For example, the interposer 280 may be a film (film), epoxy (epoxy), or Thermal Interface Material (TIM).
As shown in fig. 2C, the electronic component 2a is bonded to a metal frame 25 by the conductive element 23, and the covering member 28 is also bonded to the metal frame 25, so as to form a package structure 2.
In the embodiment, the metal frame 25 is, for example, a lead frame (leadframe), and includes a board body 251 and a plurality of spaced apart electrical contact pads 250 located around the board body 251, and the electrical contact pads 250 are coupled to the conductive elements 23, and the board body 251 corresponds to the position of the second electronic element 22, so that the covering member 28 is coupled to the board body 251 through another interposer 29. Specifically, the board body 251 is separated from the electrical contact pads 250, and as shown in fig. 5A, the electrical contact pads 250 surround the board body 251. It should be understood that the plate 251 may be surrounded by a plurality of turns of the electrical contact pads 250, such as two rings as shown in fig. 5B.
In addition, in a subsequent process, a solder material (not shown) such as solder balls may be formed on the electrical contact pads 250 for mounting an electronic device such as a circuit board or another circuit board.
Therefore, the manufacturing method of the package structure of the present invention can provide an Electromagnetic Interference (EMI) shielding (shielding) effect for the second electronic component 22 by the design of grounding the cover 28.
In addition, the package structure 2 can conduct the heat of the second electronic component 22 through the board 251 to improve the heat dissipation effect.
In other embodiments, as shown in fig. 3A, a second cladding layer 26 may be selectively formed between the second side 20b of the carrier 20 and the metal frame 25 in the subsequent process, so that the second cladding layer 26 covers the covering member 28 and the conductive elements 23.
In the present embodiment, the second cladding layer 26 is formed by Polyimide (PI), epoxy resin (epoxy) or packaging material (molding compound), and the second cladding layer 26 has a first surface 26a and a second surface 26b opposite to each other, so that the second cladding layer 26 is combined with the second side 20b of the carrier 20 by the second surface 26b thereof, and the metal frame 25 is embedded in the first surface 26a of the second cladding layer 26, and the electrical contact pads 250 are exposed from the first surface 26a of the second cladding layer 26 (for example, the lower surfaces of the electrical contact pads 250 are flush with the first surface 26a of the second cladding layer 26), so as to form solder material (not shown) such as solder balls on the exposed surfaces of the electrical contact pads 250, so as to mount an electronic device such as a circuit board or another circuit board.
It should be understood that the material of the second cladding layer 26 and the material of the first cladding layer 24 may be the same or different.
Furthermore, if the first cladding layer 24 is not formed on the electronic component 2A in the process of fig. 2A, the second cladding layer 26 also encapsulates the first electronic elements 21,21 'when forming the second cladding layer 26, as shown in fig. 3B, so as to form another package structure 3'.
As shown in fig. 3C, the conductive elements 23', 23 ″ disposed on the carrier 20 may be copper core balls (copper balls), passive elements, or metal elements (such as columns, blocks, or needles). Specifically, the conductive element 23' on the left side is a copper core ball, and the conductive element 23 ″ on the right side is a passive element, such as a resistor, a capacitor, and an inductor, for example, a decoupling capacitor (decoupling capacitor).
In addition, the conductive elements 23 may also be formed on the circuit layer 200 on the first side 20a of the carrier 20, as shown in fig. 3C, and bonded to another metal frame 25 ″.
In another embodiment, the supporting member 27 can be omitted, and the covering member 28 can be bonded to the second electronic element 22, as shown in fig. 3C.
Therefore, the manufacturing method of the package structure of the present invention uses the metal frame 25 as an electrical contact, so that it is not necessary to use a molding die with a specific size in accordance with the size of the package structure 2,3, 3', 3 ″, i.e., the second cladding layer 26 can be formed by a general molding die, thereby reducing the production cost.
In other embodiments, the supporting member 27 (or the covering member 28) may surround (cover) a plurality of second electronic components 42, as shown in fig. 4, a supporting member 47 (or the covering member 28) may be disposed between two second electronic components 42, and the supporting member 47 (or the covering member 28) may be grounded to provide an EMI shielding effect between the second electronic components 42.
In addition, the metal frame 45 may not have the plate 251, so that the covering member 28 exposes the second cladding layer 26 (not shown) or does not expose the second cladding layer 26 (shown in fig. 4).
The electrical contact pads 250 may also be exposed on the side surface 26c of the second cladding layer 26, as shown in fig. 4 or fig. 5, so as to form a Quad Flat No-leads (QFN) structure.
The invention also provides a package structure 2,3, 3', 3 ", 4 comprising: a carrier 20, a first electronic component 21,21 ', a second electronic component 22,42, a plurality of conductive elements 23, 23', 23 ", at least one metal frame 25, 25", 45 and a cover 28.
The carrier 20 has a first side 20a and a second side 20b opposite to each other.
The first electronic component 21, 21' is attached to the first side 20a of the carrier 20. The second electronic component 22,42 is attached to the second side 20b of the carrier 20.
The conductive elements 23, 23', 23 ″ are attached to the first side 20a and/or the second side 20b of the carrier 20.
The metal frames 25,25 ", 45 include a plurality of electrical contact pads 250 coupled to the conductive elements 23.
The cover 28 is attached to the second side 20b of the carrier 20 and covers the second electronic component 22, 42.
In one embodiment, the metal frame 25,25 ", 45 is a lead frame.
In one embodiment, the metal frame 25 further includes a plate 251 corresponding to the position of the second electronic component 22. For example, the electrical contact pads 250 are separated from the board body 251. Alternatively, the board 251 is bonded to the cover 28, for example, the board 251 is bonded to the cover 28 through an interposer 29.
In one embodiment, the cover 28 is bonded to the second electronic component 22 through an interposer 280.
In one embodiment, as can be inferred from fig. 4, the cover 28 covers the plurality of second electronic components 42.
In one embodiment, the package structure 2,3, 3', 4 further includes a supporting member 27,47, which is disposed on the second side 20b of the carrier 20, such that the covering member 28 abuts against the supporting member 27. For example, the supporting member 47 is located between at least two of the second electronic elements 42.
In one embodiment, the package structure 3,3 ', 3 ", 4 further includes a second cladding layer 26 formed between the carrier 20 and the metal frames 25,45 to clad the cover 28 and the conductive elements 23, 23', 23". For example, the electrical contact pads 250 are exposed at the first surface 26a (and the side surface 26c) of the second cladding layer 26.
In summary, the package structure and the manufacturing method thereof of the present invention use the metal frame as the electrical contact, so that the second cladding layer can be formed by using a general molding die, thereby reducing the production cost.
Furthermore, the supporting member (or the shielding member) can improve the heat dissipation efficiency of the electronic component and provide the EMI shielding effect of the electronic component.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications to the above-described embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and the contents of the above-described embodiments may be combined with each other and used. Therefore, the scope of the invention should be determined from the following claims.
Claims (32)
1. A package structure, characterized in that it comprises:
a carrier;
the electronic component is connected to the bearing piece;
a plurality of conductive elements connected to the carrier;
a cover member which is disposed on the carrier member and covers the electronic component;
a metal frame including a plurality of electrical contact pads for the plurality of conductive elements to be coupled to the plurality of electrical contact pads; and
and the covering layer is formed between the bearing piece and the metal frame to cover the covering piece and the plurality of conductive elements, and the electric contact pad is exposed out of the side surface of the covering layer.
2. The package structure of claim 1, wherein the metal frame is a leadframe.
3. The package structure of claim 1, wherein the metal frame further comprises a plate body corresponding to the position of the electronic component, and the plurality of electrical contact pads are disposed around the plate body.
4. The packaging structure according to claim 3, wherein the plate body is bonded to the covering member.
5. The package structure of claim 1, wherein the cover is bonded to the electronic component through an interposer.
6. The package structure of claim 1, further comprising a support member attached to the carrier member, and wherein the cover member abuts against the support member.
7. The package structure of claim 6, wherein the support member is disposed between two of the electronic components.
8. The package structure of claim 6, wherein the support member is grounded.
9. The package structure of claim 1, wherein the cover exposes or does not expose the cover.
10. The package structure of claim 1, wherein the carrier has a first side and a second side opposite to each other, and the electronic component includes a first electronic component and a second electronic component respectively disposed on the first side and the second side, so that the cover is disposed on the second side and covers the second electronic component.
11. The package arrangement according to claim 10, wherein the first side of the carrier is formed with the or a further cladding.
12. The package structure of claim 10, wherein the metal is mounted on the first side and/or the second side of the carrier.
13. The package structure of claim 1, wherein the cover is electrically connected to the carrier.
14. The packaging structure according to claim 1, wherein the covering member covers a plurality of the electronic components.
15. The package structure according to claim 1, wherein the covering member is provided between the two electronic components.
16. The package according to claim 1, wherein the cover is grounded.
17. A method for fabricating a package structure, the method comprising:
providing an electronic assembly comprising a bearing member, an electronic element and a plurality of conductive elements, wherein the electronic element and the plurality of conductive elements are connected on the bearing member;
placing a cover on the carrier to cover the electronic device;
bonding the electronic assembly to a metal frame comprising a plurality of electrical contact pads through the plurality of conductive elements so that the plurality of conductive elements are connected to the plurality of electrical contact pads; and
a covering layer is formed between the bearing element and the metal frame and covers the covering element and the conductive elements, and the side surface of the covering layer is exposed outside the electric contact pad.
18. The method of claim 17, wherein the metal frame is a leadframe.
19. The method of claim 17, wherein the metal frame further comprises a plate corresponding to the electronic component, and the plurality of electrical contact pads are disposed around the plate.
20. The method of fabricating a package according to claim 19, wherein the plate is bonded to the covering member.
21. The method of claim 17, wherein the cover is bonded to the electronic component through an interposer.
22. The method of claim 17, further comprising attaching a support to the carrier such that the cover abuts against the support.
23. The method of claim 22, wherein the supporting member is disposed between two electronic components.
24. The method of claim 22, wherein the support member is grounded.
25. The method of claim 17, wherein the cover exposes or does not expose the encapsulant.
26. The method of claim 17, wherein the carrier has a first side and a second side opposite to each other, and the electronic components include a first electronic component and a second electronic component respectively disposed on the first side and the second side, so that the cover is disposed on the second side and covers the second electronic component.
27. The method of claim 26, wherein the first side of the carrier is formed with the cladding layer or another cladding layer.
28. The method of claim 26, wherein the metal is disposed on the first side and/or the second side of the carrier.
29. The method of claim 17, wherein the cover is electrically connected to the carrier.
30. The method for manufacturing a package structure according to claim 17, wherein the covering member covers a plurality of the electronic components.
31. The method for manufacturing a package structure according to claim 17, wherein the covering member is disposed between two electronic components.
32. The method of fabricating a package according to claim 17, wherein the cover is grounded.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106105041A TWI645518B (en) | 2017-02-16 | 2017-02-16 | Package structure and the manufacture thereof |
| TW106105041 | 2017-02-16 |
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| Publication Number | Publication Date |
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| CN108447829A CN108447829A (en) | 2018-08-24 |
| CN108447829B true CN108447829B (en) | 2020-07-17 |
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| CN201710120094.XA Active CN108447829B (en) | 2017-02-16 | 2017-03-02 | Package structure and method for fabricating the same |
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| CN (1) | CN108447829B (en) |
| TW (1) | TWI645518B (en) |
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| TWI714269B (en) * | 2019-09-19 | 2020-12-21 | 矽品精密工業股份有限公司 | Electronic package and method for manufacturing the same |
| TWI732509B (en) * | 2020-04-01 | 2021-07-01 | 矽品精密工業股份有限公司 | Electronic package |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104733419A (en) * | 2013-12-20 | 2015-06-24 | 乾坤科技股份有限公司 | Three-dimensional Package Structure And The Method To Fabricate Thereof |
| CN105552059A (en) * | 2014-10-22 | 2016-05-04 | 日月光半导体制造股份有限公司 | Semiconductor package structure and semiconductor process |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201123396A (en) * | 2009-12-24 | 2011-07-01 | Chipsip Technology Co Ltd | Package structure with shielding |
| TWI581380B (en) * | 2015-07-20 | 2017-05-01 | 矽品精密工業股份有限公司 | Package structure and shielding member and method for fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104733419A (en) * | 2013-12-20 | 2015-06-24 | 乾坤科技股份有限公司 | Three-dimensional Package Structure And The Method To Fabricate Thereof |
| CN105552059A (en) * | 2014-10-22 | 2016-05-04 | 日月光半导体制造股份有限公司 | Semiconductor package structure and semiconductor process |
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| TWI645518B (en) | 2018-12-21 |
| TW201832324A (en) | 2018-09-01 |
| CN108447829A (en) | 2018-08-24 |
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