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CN108074883A - 半导体封装件、其制造方法以及使用其的电子元件模块 - Google Patents

半导体封装件、其制造方法以及使用其的电子元件模块 Download PDF

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Publication number
CN108074883A
CN108074883A CN201710742374.4A CN201710742374A CN108074883A CN 108074883 A CN108074883 A CN 108074883A CN 201710742374 A CN201710742374 A CN 201710742374A CN 108074883 A CN108074883 A CN 108074883A
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CN
China
Prior art keywords
electronic component
semiconductor package
package part
layer
lamination
Prior art date
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Granted
Application number
CN201710742374.4A
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English (en)
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CN108074883B (zh
Inventor
金泰贤
康昌寿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electro Mechanics Co Ltd
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Priority claimed from KR1020170026215A external-priority patent/KR20180052062A/ko
Application filed by Samsung Electro Mechanics Co Ltd filed Critical Samsung Electro Mechanics Co Ltd
Publication of CN108074883A publication Critical patent/CN108074883A/zh
Application granted granted Critical
Publication of CN108074883B publication Critical patent/CN108074883B/zh
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Abstract

本发明提供一种半导体封装件、其制造方法以及使用其的电子元件模块。所述半导体封装件包括：板部件，所述板部件包括其中设置有元件容纳区域的芯层以及设置在所述芯层的顶表面和底表面上的积层；电子元件，设置在所述元件容纳区域中；及块状导体，设置在所述积层内并且电连接到所述电子元件的端子。

Description

半导体封装件、其制造方法以及使用其的电子元件模块
本申请要求于2016年11月9日和于2017年2月28日在韩国知识产权局提交的第10-2016-0149122号和第10-2017-0026215号韩国专利申请的优先权和权益，所述两个韩国专利申请的全部公开内容出于所有目的通过引用被包含于此。
技术领域
下面的描述涉及一种半导体封装件、其制造方法以及使用其的电子元件模块。
背景技术
关于半导体芯片的技术发展的近来主要趋势之一是减小组件的尺寸。为了减小半导体芯片的尺寸，在封装领域，已需要实现具有小尺寸的多个鳍(fin)。
为了满足上述要求而提出的封装技术之一是扇出型半导体封装件。扇出型半导体封装件使连接端子重新布线到其上设置有半导体芯片的区域的外部，以能够实现多个鳍同时具有小尺寸。
发明内容
提供本发明内容以通过简化形式介绍将在下面的具体实施方式中进一步描述的选择的构思。本发明内容既不意在确定所要求保护主题的关键特征或必要特征，也不意在用于帮助确定所要求保护的主题的范围。
在一个总体方面，一种半导体封装件包括板部件，所述板部件包括：芯层，所述芯层具有设置在所述芯层中的元件容纳区域；及积层，设置在所述芯层的顶表面和底表面上。所述半导体封装件还包括：电子元件，设置在所述元件容纳区域中；及块状导体，设置在所述积层内并且电连接到所述电子元件的端子。
所述块状导体可通过镀覆方法直接形成在所述电子元件的所述端子上。
重新布线层可设置在所述电子元件的所述端子上，并且所述块状导体可设置在设置于所述重新布线层上的布线层上。
所述重新布线层可设置在所述元件容纳区域内。
所述半导体封装件还可包括设置在所述积层上的绝缘保护层，所述保护绝缘层可包括部分暴露所述块状导体的一个或更多个开口。
所述电子元件可以为功率放大器，并且所述端子可包括多个电力端子和多个接地端子。
所述块状导体可包括：第一块状导体，连接到所述多个电力端子；及第二块状导体，连接到所述多个接地端子。
所述块状导体和所述积层可具有大体相同的厚度。
所述块状导体可设置在所述电子元件的有效表面上。
所述电子元件的所述端子可形成为具有与所述块状导体的面积对应的尺寸的焊盘，并且所述块状导体可通过镀覆方法从所述端子生长导电材料而形成。
在另一总体方面，一种制造半导体封装件的方法包括：将电子元件设置在芯层的元件容纳区域中；及通过在所述芯层的顶表面和底表面上形成绝缘层和布线层来形成积层，其中，形成所述积层的步骤包括在所述绝缘层中形成电连接到所述电子元件的端子的一个或更多个块状导体。
将所述电子元件设置在所述元件容纳区域中的步骤可包括在所述芯层中形成通孔，以获得所述元件容纳区域。
形成所述块状导体的步骤可包括：在所述芯层上形成所述绝缘层；在所述绝缘层中形成腔；及通过将导电材料填充到所述腔中来形成所述块状导体。
形成所述腔的步骤可包括曝光操作和蚀刻操作。
所述方法在形成所述积层后还可包括：在所述积层上形成绝缘保护层。
在另一总体方面，一种电子元件模块包括：半导体封装件，包括设置在芯层内的电子元件、层叠在所述芯层上的积层以及设置在所述积层内以排放所述电子元件的热的一个或更多个块状导体；及至少一个电子组件，安装在所述半导体封装件上。
所述电子元件模块还可包括金属层，所述金属层沿着所述半导体封装件和所述电子组件的外表面设置，以阻截电磁波。
在另一总体方面，一种半导体封装件包括：电子元件，设置在芯层内，所述电子元件的端子通过所述芯层的开口被暴露；积层，覆盖所述芯层的所述开口；及块状导体，设置在所述积层内并且电连接到所述端子。
所述积层可接触所述电子元件。
一个或更多个块状导体可设置在所述积层内，并且所述一个或更多个块状导体和所述积层可覆盖所述开口，所述电子元件的所述端子从所述芯层通过所述开口被暴露。
其他特征和方面将通过下面的具体实施方式、附图和权利要求而显而易见。
附图说明
图1是示意性地示出半导体封装件的示例的截面图。
图2是图1中所示的半导体封装件的示例的A部分的放大截面图。
图3A至图3E是示出块状导体的另外的示例的示图。
图4A至图6C是示出制造如图1所示的半导体封装件的方法的示例的示图。
图7是示意性地示出半导体封装件的另一示例的截面图。
图8是示意性地示出电子元件模块的示例的截面图。
图9是示意性地示出电子元件模块的另一示例的截面图。
图10是示意性地示出根据本说明书的电子元件模块的另一示例的截面图。
在所有的附图和具体实施方式中，相同的标号指示相同的元件。为了清楚、说明及方便起见，附图可不按照比例绘制，并且可夸大附图中的元件的相对尺寸、比例和描绘。
具体实施方式
提供以下具体实施方式以帮助读者获得对这里所描述的方法、设备和/或系统的全面理解。然而，对本领域的普通技术人员来讲，这里所描述的方法、设备和/或系统的各种变换、修改及等同物将是显而易见的。这里所描述的操作的顺序仅仅是示例，并不限于这里所阐述的顺序，而是除了必须以特定顺序发生的操作之外，可做出对本领域的普通技术人员将是显而易见的改变。此外，为了提高清楚性和简洁性，可省略本领域的普通技术人员众所周知的功能和构造的描述。
这里所描述的特征可以以不同的形式实施，并且不被解释为局限于这里所描述的示例。更确切的说，已提供这里所描述的示例，以使本公开将是彻底的和完整的，并且将本公开的全部范围传达给本领域的普通技术人员。
在下文中，将参照附图详细地描述本公开的各种示例。
图1是示意性地示出半导体封装件的实施例的截面图，图2是图1中所示的半导体封装件的实施例的A部分的放大截面图。
参照图1和图2，半导体封装件100包括板部件40和嵌在板部件40内的至少一个电子元件1。
板部件40包括重复层叠的多个绝缘层L1、L2、L3和L4以及布线层41、42、43、44和45，并且包括设置在绝缘层L1至L4中的一个绝缘层内的元件容纳区域49。
板部件40可分为：芯层10；一个或更多个积层20，层叠在芯层10的外表面上；一个或更多个绝缘保护层30，层叠在积层20的外表面上；及重新布线层15，设置在芯层10内。
板部件40的绝缘层L1至L4可由具有绝缘性质的树脂材料形成。可使用诸如环氧树脂的热固性树脂、诸如聚酰亚胺的热塑性树脂、其中含有诸如玻璃纤维或无机填料的增强材料的树脂(诸如半固化片)作为用于形成绝缘层L1至L4的材料。然而，用于形成绝缘层的材料不限于此。
芯层10的绝缘层L1、积层20的绝缘层L2和L3以及重新布线层15的绝缘层L4可由彼此不同的材料形成，或者可部分由相同的材料形成。例如，芯层10的绝缘层L1可由聚合物材料形成，积层20的绝缘层L2和L3以及重新布线层15的绝缘层L4可由环氧树脂材料形成，或者积层20的绝缘层L2和L3以及重新布线层15的绝缘层L4可由聚合物材料形成，芯层10的绝缘层L1可由环氧树脂材料形成。基于半导体封装件100的应用，各种另外的修改是可行的。在另一示例中，绝缘层L1至L4中的所有绝缘层可由相同的材料形成。
布线层41至45可分别设置在绝缘层L1至L4的顶表面和底表面中的一个表面或顶表面和底表面二者上。
在图1中示出的示例中，布线层43和44被设置为构成板部件40的布线层41至45中的最外边的层，并且布线层43和44部分暴露于外部，以用作连接焊盘50。
层间连接导体48分别设置为贯穿绝缘层L1至L4，以穿过绝缘层L1至L4。层间连接导体48可电连接到连接焊盘50或可将布线层41至45彼此连接。
布线层41至45以及层间连接导体48可通过光刻方法形成。例如，布线层41至45可通过使诸如铜(Cu)箔的金属层图案化而形成。此外，层间连接导体48可通过在绝缘层L1至L3中形成通路孔然后在通路孔中填充导电材料而获得。然而，本公开的构造不限于此。
在图1中，芯层10设置在板部件40的中央中并且形成为单层。然而，芯层10的构造不限于此。在另一示例中，芯层10还可形成为例如多层基板。
在该示例中，元件容纳区域49形成在板部件40内。至少一个电子元件1嵌在元件容纳区域49内。
元件容纳区域49形成在芯层10内并且嵌在芯层10中。在该示例中，元件容纳区域49的部分延伸到积层20并且被积层20围住。然而，元件容纳区域49的构造不限于此。
绝缘构件49a设置在元件容纳区域49内。在该示例中，绝缘构件49a形成在元件容纳区域49内，以填充电子元件1与芯层10之间的空间或间隙。
绝缘构件49a可具有绝缘性质，并且可由可容易填充元件容纳区域49与设置在元件容纳区域49中的电子元件1之间的空间或间隙的材料形成。例如，绝缘构件49a可通过使用B阶段树脂或聚合物填充元件容纳区域49与电子元件1之间的空间或间隙然后使B阶段树脂或聚合物固化而形成。然而，形成绝缘构件49a的方法不限于此。
嵌在元件容纳区域49内的电子元件1可以是在其运行过程中产生大量热的发热元件。例如，电子元件1可以是功率放大器。然而，电子元件1不限于此。例如，电子元件1可从诸如滤波器、集成电路(IC)、开关元件等的多种元件中选择。可使用多种元件来实现电子元件1，电子元件1可产生大量的热并且嵌在板部件40内。
在该示例中，作为从晶圆切割的裸片或裸芯片的电子元件1被容纳在元件容纳区域49中。通过容纳作为裸片或裸芯片的电子元件1，可显著地减小半导体封装件100的整体尺寸。
参照图1，电子元件1包括有效(active)表面和无效(inactive)表面，电子元件1的无效表面和有效表面彼此背对。有效表面上形成有端子，无效表面上没有设置端子。此外，电子元件1的端子包括电力端子1a和接地端子1b。然而，有效表面和无效表面的布局不限于此。
在该示例中，重新布线层15设置在芯层10的元件容纳区域49内，并且形成在电子元件1的有效表面上。重新布线层15将电子元件1的端子1a和1b与下面将描述的块状导体48a和48b电连接。
为此，在该示例中，重新布线层15包括绝缘层L4、设置在绝缘层L4内的多个层间连接导体48以及设置在绝缘层L4上的布线层45。
如上所述，重新布线层15的绝缘层L4可选择性地由诸如环氧树脂的热固性树脂、诸如聚酰亚胺的热塑性树脂和含有诸如玻璃纤维或无机填料的增强材料的树脂中的任何一种形成。然而，绝缘层L4的材料和布局不限于此。
设置在重新布线层15内的布线层45可将设置在电子元件1的有效表面上的电力端子1a彼此电连接。此外，布线层45可将接地端子1b彼此电连接。
因为重新布线层15设置在芯层10的元件容纳区域49内，所以在该示例中，重新布线层15的布线层45与芯层10的布线层41设置在同一平面上。然而，布线层45和重新布线层15的布局不限于此。
在示出的示例中，积层20设置在芯层10的顶表面和底表面二者上。积层20通过积层方法形成在芯层10上。
根据需要，构成积层20的绝缘层L2和L3可由相同的材料形成，或由两种不同的材料形成。此外，积层20可由能够形成如图5C所示的腔26的材料形成，以使块状导体48a和48b设置在通过曝光和蚀刻操作形成的腔26中。
绝缘保护层30可由阻焊剂形成。然而，用于形成绝缘保护层30的材料不限于此。
在该示例中，两个绝缘保护层30设置在相应的积层20的外部。因此，绝缘保护层30形成板部件40的最外面的表面。此外，绝缘保护层30包括将连接焊盘50暴露于外部的多个开口。块状导体48a和48b通过开口暴露于板部件40的外部。然而，绝缘保护层30以及块状导体48a和48b的布局不限于此。
层间连接导体48包括一个或更多个块状导体48a和48b。
块状导体48a和48b具有比其他层间连接导体48相对大的体积和表面面积。也就是说，块状导体48a和48b可具有比用于形成半导体封装件100内的其他层间连接导体48的通路孔的宽度大的宽度。例如，块状导体48a和48b的宽度可以为用于形成半导体封装件100内的其他层间连接导体48的通路孔的宽度两倍或三倍大。在该示例中，块状导体48a和48b不是通过使用导电材料填充通路孔而形成的过孔。块状导体48a和48b可具有其上表面与其下表面大体平行的块体的整体形状。
在图1中，块状导体48a和48b设置在与电子元件1的有效表面相对应的位置上，并且设置在积层20中的一个积层内。块状导体48a和48b的厚度可与积层20的厚度相等或相似。
块状导体48a和48b设置在电子元件1的有效表面之上，以面对电子元件1的有效表面。
块状导体48a和48b电连接到电子元件1的端子1a和1b以及布线层45，以将电子元件1的端子1a和1b以及布线层45彼此电连接。根据本实施例，电子元件1包括电力端子1a和接地端子1b。因此，块状导体48a和48b可单独分为：第一块状导体48a，连接到电力端子1a；第二块状导体48b，连接到接地端子1b。这里，术语“第一”和“第二”仅用于将两种类型的块状导体之间区分开，并不表示固有顺序。
在多个电力端子1a设置在电子元件1上的情况下，如在图2中所示的实施例中，多个电力端子1a可全部连接到第一块状导体48a。相似地，在多个接地端子1b位于电子元件1上的情况下，多个接地端子1b可全部连接到第二块状导体48b。
块状导体48a和48b可通过如下步骤获得：形成绝缘层L2；通过诸如曝光、蚀刻等的操作在绝缘层L2内形成如图5C所示的腔26，由此暴露布线层45；然后通过诸如镀覆等的方法使用导电材料填充腔26。结果，块状导体48a和48b可具有与形成在绝缘层L2内的腔26的形状对应的形状。
图3A至图3E是根据本公开的块状导体48a和48b的不同修改示例的透视图。参照图3A至图3E，块状导体48a和48b可形成为如图3A所示的平行六面体形状。然而，块状导体48a和48b的形状不限于此。例如，如图3B至图3E所示，块状导体48a和48b可形成为与电子元件1的端子1a和1b的布局相对应。块状导体48a和48b可具有彼此平行的下表面和上表面，并且块状导体48a和48b的宽度可大于块状导体48a和48b的竖直高度。
一个或更多个连接焊盘50可设置在块状导体48a和48b的表面上。外连接端子60可结合到连接焊盘50，或电子组件(未示出)可安装在连接焊盘50上。通过将电子组件安装在设置于这样的块状导体48a和48b上的连接焊盘50上，可显著减小电子组件与电子元件1之间的电路径的长度。此外，由于块状导体48a和48b沿着电路径设置，因此可有效地排放电路径中产生的热，从而可显著地减小通过电路径产生的热导致的电力损耗。
可使用本领域公知的各种板来实现具有上述构造的板部件40。例如，可使用印刷电路板、陶瓷基板、玻璃基板、柔性基板等来实现板部件40。
板部件40可以是具有多个布线层41至45的多层板。虽然作为示例以上示出的板部件40的实施例包括五个布线层41至45，但根据需要，根据本公开的另一示例的板部件40可包括更多的布线层或更少的布线层。
在上述的半导体封装件100中，块状导体48a和48b可连接到为发热元件的电子元件1的端子1a和1b。因此，半导体封装件100可有效地排放电子元件1中产生的热。
在电子元件1中产生的热没有被顺利地排放的情况下，热可能会沿着电子元件1的电路径被传递，这导致电路径的温度升高。在这种情况下，温度的升高使电路径的电阻增大，并且产生的电阻增大导致电损耗增大。
电子元件1可具有主电力线，几毫安(mA)至几十安(A)的电流可流经主电力线。然而，在根据现有技术的印刷电路板的情况下，为层间连接导体的过孔可形成为圆形结构并且可强加尺寸限制。然而，模块或封装件可能会需要薄且轻同时保持多功能性的印刷电路板，并且形成为圆形结构的过孔在设计和制造该板时强加限制。
为了消除通过形成过孔带来的设计限制，根据本实施例的半导体封装件100可利用块状导体48a和48b。由于半导体封装件100使通过块状导体48a和48b形成与电子组件的电路径的层间连接导体48的使用以及图案的结构优化，因此可显著地减小IR压降，并且可显著地减小电力损耗。此外，如果减小电力损耗，则可减小电路径中产生的热量，从而，还可显著地减小由热导致的另外的损耗，由此可提高电子元件1的效率。
此外，由于块状导体48a和48b设置在电子元件1的电路径上，因此无需将单独的散热构件添加到电子元件1的无效表面上来排放电子元件1的热。
接下来，将描述制造半导体封装件的方法的示例。
图4A至图6C是示出制造如图1所示的半导体封装件的方法的示例的示图。
首先，如图4A所示，制备层叠件P，使得层叠件P包括绝缘层L1以及形成在绝缘层L1的上表面和下表面上的金属层M1和M2(S01)。根据一个示例，覆铜板(CCL)可用作层叠件P。
接下来，通过使层叠件P的金属层M1和M2图案化来形成布线层41和42(S02)。可通过曝光和蚀刻操作等来执行由金属层M1和M2形成布线层41和42。
同时，可去除金属层M1和M2的预定区域，以随后形成元件容纳区域49。也就是说，在该操作中，为了在绝缘层L1中形成元件容纳区域49，去除金属层M1和M2的与用于元件容纳区域49的开口相对应的区域。因此，金属层M1和M2的与元件容纳区域49的形状和尺寸相对应的区域被去除。
此外，在本操作中，在绝缘层L1中形成层间连接导体48。可通过在绝缘层L1中形成通孔然后将导电材料填充到通孔中来形成层间连接导体48。
接下来，去除绝缘层L1的一部分以形成元件容纳区域49，然后将带T附着到芯层10的一个表面以支撑电子元件1(S03)。
元件容纳区域49形成为具有通孔，并且元件容纳区域49具有与嵌入的电子元件1的尺寸或形状相对应的尺寸或形状。
在该示例中，在将要形成元件容纳区域49的区域上不设置布线层。因此，可使用激光通过去除绝缘层来容易地形成元件容纳区域49。然而，形成元件容纳区域49的方法不限于此，可使用诸如冲压方法和钻孔方法的各种方法，只要这些方法可在芯层10中形成元件容纳区域49即可。
将有效表面上形成有端子1a的电子元件1设置在元件容纳区域49内。在这种情况下，将电子元件1设置为使得其无效表面与带T接触。
当电子元件1设置在元件容纳区域49内时，将绝缘构件49a填充到元件容纳区域49中，然后固化。可将绝缘构件49a引入到元件容纳区域49中，以填充电子元件1与元件容纳区域49之间的空间或间隙，并且将电子元件1固定在适当位置。
通过将液态胶引入到元件容纳区域49中然后使液态胶固化为硬化的绝缘构件49a的工艺来形成绝缘构件49a。
接下来，在去除带T后，在电子元件1的有效表面上形成重新布线层15(S05)。可通过在电子元件1的有效表面上形成绝缘层L4并且通过光刻操作在绝缘层L4上形成布线层45来实现重新布线层15。在这种情况下，在绝缘层L4内形成连接到电子元件1的端子的多个连接导体48。
接下来，形成积层20。
首先，在芯层10的一个表面上层叠绝缘层L2(S06)。在图5B中，例如，首先在芯层10的与电子元件1的有效表面相邻的一个表面上形成积层20。然而，积层20的布局不限于此，在另一示例中，积层20的布局可变。例如，可首先在芯层10的另一表面上形成积层20，或可在芯层10的顶表面和底表面二者上同时形成积层20。
接下来，在绝缘层L2中形成用于形成层间连接导体48的通路孔27和腔26(S07)。
可通过光刻形成层间连接导体48。在本操作中，通过曝光和蚀刻操作在绝缘层L2内形成多个通路孔27和腔26。
在本操作中，腔26设置在电子元件1之上，并且重新布线层15的布线层45通过腔26暴露于外部。
接下来，通过镀覆操作使用导电材料填充通路孔27和腔26，以形成层间连接导体48和布线层43(S08)。在本操作中，填充在腔26中的导电材料最终形成块状导体48a和48b。因此，块状导体48a和48b具有与绝缘层L2的厚度相等或相似的厚度。
同时，由于在本操中形成的布线层43是布线层41至45中的设置在最外部分上的布线层，因此布线层43包括至少一个电极焊盘50。
接下来，在相对应的积层20上形成每个绝缘保护层30后，在绝缘保护层30中的每个绝缘层中形成多个开口，以使电极焊盘50暴露于外部(S09)。绝缘保护层30可由阻焊剂形成。根据一个示例，绝缘保护层30还可根据需要形成为多层形式。
通过对芯层10的每个表面重复执行上述操作(S06至S09)来完成积层20。结果，完成设置在芯层10的顶表面和底表面二者上的积层20，并且电子元件1完全嵌入芯层10和积层20内(S10)。
本实施例描述了仅一个层的积层20层叠在芯层10的顶表面和底表面二者上的示例。然而，本公开的构造不限于此。例如，还可通过在芯层10上层叠多个绝缘层并且在多个绝缘层之间形成一个布线层来形成多层形式的积层20。
接下来，可通过在电极焊盘50上形成外连接端子60来完成半导体封装件100。
在制造根据本实施例的具有如上所述构造的半导体封装件的方法中，块状导体可设置在电子元件1的电力线之上，以有效地排放施加到电力线的热。
在电子元件1为功率放大器的情况下，电力线中会产生非常高的热。因此，根据本公开，由于可减小电力线中的热导致的损耗，因此可提高电子元件1的效率。
此外，当传统地使用激光钻孔方法或机械钻孔方法来形成层间连接导体时，难以形成如本实施例描述的具有宽尺寸的腔。然而，按照根据本实施例的制造半导体封装件的方法，由于通过曝光和蚀刻操作形成腔，因此块状导体可形成为各种尺寸和形状。
同时，根据本公开的半导体封装件不限于上述实施例，而是可进行各种修改。
图7是示意性地示出根据本公开的半导体封装件的另一实施例的截面图。
参照图7，半导体封装件200包括电子元件1，电子元件1包括端子1a和1b，并且端子1a和1b具有焊盘的形状。此外，块状导体48a和48b通过表面接触连接到具有焊盘形状的端子1a和1b。例如，根据本实施例的端子1a和1b可具有与块状导体48a和48b的下表面的面积对应的尺寸和形状。
在这种情况下，由于可显著地增大电子元件1的端子1a和1b与块状导体48a和48b之间的接触面积，因此可提高导热性，从而显著地提高散热效果。
根据本实施例的块状导体48a和48b可通过镀覆方法形成，并且可通过从电子元件1的端子1a和1b生长导电材料而形成。然而，形成块状导体48a和48b的方法不限于此。
同时，在根据本实施例的半导体封装件200中，省略重新布线层，并且电子元件1的端子1a和1b直接连接到块状导体48a和48b。然而，半导体封装件200的构造不限于此。根据另一实施例，半导体封装件200基于电子元件1的尺寸还包括重新布线层。
图8是示意性地示出根据本公开的电子元件模块的示例的截面图。
参照图8，根据本实施例的电子元件模块具有至少一个电子组件300，电子组件300安装在上述的图1中示出的半导体封装件100上。此外，电子组件300被包封部件5包封。
在该实施例中，连接焊盘50设置在半导体封装件100的顶表面和底表面二者上。因此，顶表面和底表面二者中的第二表面可用于安装主基板，顶表面和底表面二者中的第一表面可用于安装单独制造的电子组件300。
可使用公知的有源元件和无源元件中的至少一种作为电子组件300。此外，可使用公知的诸如环氧塑封料(EMC)的包封构件作为包封部件5。
在根据本实施例的半导体封装件100中，连接焊盘50可设置在整个第一表面上。因此，由于多个连接焊盘50可通过第一表面设置，因此多个电子组件300可安装在第一表面上。结果，可实现集成度的提高。
图9是示意性地示出根据本公开的电子元件模块的另一实施例的截面图。
参照图9，根据本实施例的电子元件模块被构造为封装形式的电子组件300a安装在上述的图1中示出的半导体封装件100上的堆叠封装(PoP)形式。
在该实施例中，连接焊盘50设置在半导体封装件100的顶表面和底表面二者上。因此，顶表面和底表面二者中的第二表面可用于安装主基板，顶表面和底表面二者中的第一表面可用于安装单独制造的电子组件300a。
可使用公知的半导体封装件中的任意一种作为电子组件300a。例如，电子组件300a可被构造为使得电子元件8安装在基板7上并且被包封部件5a包封。然而，电子组件300a不限于此，并且可使用所有的电子组件，只要它们可被安装在半导体封装件100的第一表面上即可。
在根据本实施例的半导体封装件100中，连接焊盘50可设置在整个第一表面上。因此，由于多个连接焊盘50可通过第一表面设置，因此具有多个I/O端子的封装件也可安装在第一表面上。此外，可提高与安装在第一表面上的电子组件300a的结合可靠性。
图10是示意性地示出根据本公开的电子元件模块的另一实施例的截面图。参照图10，根据本实施例的电子元件模块被构造为封装形式的电子组件300b安装在半导体封装件100a上的堆叠封装(PoP)形式，半导体封装件100a是上述的图1中示出的半导体封装件100的变型。
半导体封装件100a与图1中示出的半导体封装件100的不同之处仅在于，半导体封装件100a包括多个电子元件1和1′。然而，在其他构造方面，半导体封装件100a可被构造为与图1中示出的半导体封装件100相同。电子元件1和1′可包括功率放大器、滤波器和集成电路(IC)，并且可如上所述地以裸片形式嵌入。
可使用公知的半导体封装件中的任意一种作为电子组件300b。根据该实施例，电子组件300b被构造为使得电子元件8和8′安装在基板7上并且被包封部件5a包封；然而，电子组件300b的构造不限于此。
此外，根据本实施例，金属层70设置在电子元件模块的表面上。
金属层70可被设置为阻截电磁波。因此，金属层70可沿着半导体封装件100a和电子组件300b的外表面形成。在这种情况下，绝缘材料9可填充在半导体封装件100a与电子组件300b之间。
同时，根据本实施例的金属层70不限于上述构造，并且还可根据需要仅形成在半导体封装件100a或电子组件300b的表面上。此外，如图10所示，金属层70可介于电子组件300b中包括的电子元件8和8′之间，以阻截电子元件8和8′之间的干扰。
根据本实施例的具有上述构造的半导体封装件可将裸片形式的电子元件1和1′嵌在其中，并且可具有设置在其顶表面和底表面二者上的连接焊盘50。因此，可显著地减小半导体封装件的尺寸，从而可按照PoP结构来利用半导体封装件。
此外，由于电子元件中产生的热可通过块状导体被有效地排放，因此可抑制半导体封装件在运行过程中温度升高。
此外，根据本实施例的电子元件模块可通过在半导体封装件中安装多种形式的电子组件而制造。结果，可提高集成度。
如上所述，根据本公开的实施例，由于半导体封装件使通过块状导体形成连接到电子元件的电路径的层间连接导体和图案的结构优化，因此可显著地减小IR压降，并且可显著地减小电力损耗。此外，如果减小电力损耗，则可减小电路径中产生的热量，因此，还可显著地减小通过热导致的另外的损耗，由此可提高电子元件的效率。
虽然本公开包括具体示例，但对本领域的普通技术人员将显而易见的是，在不脱离权利要求及其等同物的精神及范围的情况下，可对这些示例作出形式和细节上的各种改变。这里所描述的示例将被理解为仅是描述性的含义，而非限制的目的。每个示例中的特征或方面的描述将被理解为可适用于其他示例中的类似的特征或方面。如果以不同的顺序执行所描述的技术，和/或如果按照不同的方式组合和/或通过其他组件或他们的等同物替换或增补所描述的系统、架构、装置或电路中的组件，则可获得合适的结果。因此，本公开的范围不由具体实施方式来限定，而由权利要求及其等同物来限定，并且在权利要求及其等同物的范围之内的全部变型将被理解为包含于本公开中。

Claims (20)

1.一种半导体封装件，包括：
板部件，包括：芯层，所述芯层具有设置在所述芯层中的元件容纳区域；及积层，设置在所述芯层的顶表面和底表面上；
电子元件，设置在所述元件容纳区域中；及
块状导体，设置在所述积层内并且电连接到所述电子元件的端子。
2.如权利要求1所述的半导体封装件，其中，所述块状导体通过镀覆方法直接形成在所述电子元件的所述端子上。
3.如权利要求1所述的半导体封装件，其中，重新布线层设置在所述电子元件的所述端子上，并且
所述块状导体设置在设置于所述重新布线层上的布线层上。
4.如权利要求3所述的半导体封装件，其中，所述重新布线层设置在所述元件容纳区域内。
5.如权利要求1所述的半导体封装件，所述半导体封装件还包括设置在所述积层上的绝缘保护层，
其中，所述绝缘保护层包括部分暴露所述块状导体的一个或更多个开口。
6.如权利要求1所述的半导体封装件，其中，所述电子元件为功率放大器，并且
所述端子包括多个电力端子和多个接地端子。
7.如权利要求6所述的半导体封装件，其中，所述块状导体包括：第一块状导体，连接到所述多个电力端子；及第二块状导体，连接到所述多个接地端子。
8.如权利要求1所述的半导体封装件，其中，所述块状导体和所述积层具有大体相同的厚度。
9.如权利要求1所述的半导体封装件，其中，所述块状导体设置在所述电子元件的有效表面上。
10.如权利要求1所述的半导体封装件，其中，所述电子元件的所述端子形成为具有与所述块状导体的面积对应的尺寸的焊盘，并且
所述块状导体通过镀覆方法从所述端子生长导电材料而形成。
11.一种制造半导体封装件的方法，所述方法包括：
将电子元件设置在芯层的元件容纳区域中；及
通过在所述芯层的顶表面和底表面上形成绝缘层和布线层来形成积层，
其中，形成所述积层的步骤包括在所述绝缘层中形成电连接到所述电子元件的端子的一个或更多个块状导体。
12.如权利要求11所述的方法，其中，将所述电子元件设置在所述元件容纳区域中的步骤包括在所述芯层中形成通孔，以获得所述元件容纳区域。
13.如权利要求11所述的方法，其中，形成所述块状导体的步骤包括：
在所述芯层上形成所述绝缘层；
在所述绝缘层中形成腔；及
通过将导电材料填充到所述腔中来形成所述块状导体。
14.如权利要求13所述的方法，其中，形成所述腔的步骤包括曝光操作和蚀刻操作。
15.如权利要求11所述的方法，所述方法在形成所述积层后还包括：在所述积层上形成绝缘保护层。
16.一种电子元件模块，包括：
半导体封装件，包括设置在芯层内的电子元件、层叠在所述芯层上的积层以及设置在所述积层内以排放所述电子元件的热的一个或更多个块状导体；及
至少一个电子组件，安装在所述半导体封装件上。
17.如权利要求16所述的电子元件模块，所述电子元件模块还包括金属层，所述金属层沿着所述半导体封装件和所述电子组件的外表面设置，以阻截电磁波。
18.一种半导体封装件，包括：
电子元件，设置在芯层内，所述电子元件的端子通过所述芯层的开口被暴露；
积层，覆盖所述芯层的所述开口；及
块状导体，设置在所述积层内并且电连接到所述端子。
19.如权利要求18所述的半导体封装件，其中，所述积层接触所述电子元件。
20.如权利要求18所述的半导体封装件，其中，一个或更多个块状导体设置在所述积层内，并且所述一个或更多个块状导体和所述积层覆盖所述开口，所述电子元件的所述端子从所述芯层通过所述开口被暴露。
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