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CN107799499B - 半导体封装结构及其制造方法 - Google Patents

半导体封装结构及其制造方法 Download PDF

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Publication number
CN107799499B
CN107799499B CN201710664209.1A CN201710664209A CN107799499B CN 107799499 B CN107799499 B CN 107799499B CN 201710664209 A CN201710664209 A CN 201710664209A CN 107799499 B CN107799499 B CN 107799499B
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chip
redistribution layer
electrically connected
semiconductor package
layer
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CN107799499A (zh
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郑心圃
许峰诚
陈硕懋
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本揭露实施例揭露一种半导体封装结构及其制造方法。其中该半导体封装结构包含重布层RDL、第一芯片、至少一个第二芯片、囊封物及第三芯片。所述重布层具有彼此对置的第一表面及第二表面。所述第一芯片位于所述重布层的所述第一表面上方且电连接到所述重布层。所述第二芯片位于所述重布层的所述第一表面上方。所述第二芯片包含多个通孔结构。所述囊封物位于所述重布层的所述第一表面上方，其中所述囊封物包围所述第一芯片及所述第二芯片。所述第三芯片位于所述囊封物上方且透过所述第二芯片的所述通孔结构及所述重布层电连接到所述第一芯片。

Description

半导体封装结构及其制造方法
技术领域
本揭露实施例涉及半导体封装结构及其制造方法。
背景技术
为试图进一步增大电路密度且减少成本，已开发三维(3D)半导体封装结构。随着半导体技术的演进，半导体装置变得越来越小，同时需要将更多功能集成到半导体装置中。相应地，半导体装置需要使越来越多输入/输出(I/O)端子封装到较小面积中，且I/O端子的密度随时间快速上升。因此，半导体装置的封装变得更困难，其不利地影响封装的成出率。
发明内容
根据本揭露的一实施例，一种半导体封装结构包括：重布层，其具有彼此对置的第一表面及第二表面；第一芯片，其位于所述重布层的所述第一表面上方且电连接到所述重布层；第二芯片，其位于所述重布层的所述第一表面上方，其中所述第二芯片包含多个通孔结构；囊封物，其位于所述重布层的所述第一表面上方，其中所述囊封物包围所述第一芯片及所述第二芯片；及第三芯片，其位于所述囊封物上方且透过所述第二芯片的所述通孔结构及所述重布层电连接到所述第一芯片。
根据本揭露的一实施例，一种半导体封装结构包括：第一重布层，其具有彼此对置的第一表面及第二表面；第一芯片，其位于所述第一重布层的所述第一表面上方；第二芯片，其位于所述第一重布层的所述第一表面上方，其中所述第二芯片包含多个通孔结构，且所述通孔结构的第一端子耦合到所述第一重布层；第一囊封物，其位于所述第一重布层的所述第一表面上方，其中所述第一囊封物包围所述第一芯片及所述第二芯片；第二重布层，其位于所述第一囊封物上方且电连接到所述通孔结构的第二端子，其中所述第二重布层具有彼此对置的第三表面及第四表面，且所述第三表面面向所述第一表面；第三芯片，其位于所述第二重布层的所述第四表面上方且电连接到所述第二重布层；及第二囊封物，其位于所述第二重布层上方。
根据本揭露的一实施例，一种用于制造半导体封装结构的方法包括：形成第一重布层；将第一芯片安置在所述第一重布层上方；将第二芯片安置在所述第一重布层上方，其中所述第二芯片包含多个通孔结构；使囊封物形成在所述第一重布层上方；及将第三芯片安置在所述囊封物上方，其中所述第三芯片及所述第一重布层透过所述第二芯片的所述通孔结构电连接。
附图说明
自结合附图来解读的以下详细描述最佳地理解本揭露的方面。应注意，根据行业标准做法，各种结构未按比例绘制。事实上，为使讨论清楚，可任意增大或减小各种结构的尺寸。
图1是绘示根据本揭露的各种方面的用于制造半导体封装结构的方法的流程图。
图2A、2B、2C、2D、2E、2F、2G、2H、2I、2J及2K是根据本揭露的一或多个实施例的制造半导体封装结构的各种操作的一者中的横截面图。
图3是根据本揭露的一或多个实施例的半导体封装结构的横截面图。
图4A、4B、4C、4D、4E、4F、4G、4H、4I、4J及4K是根据本揭露的一或多个实施例的制造半导体封装结构的各种操作的一者中的横截面图。
图5是根据本揭露的一或多个实施例的半导体封装结构的横截面图。
图6是根据本揭露的一或多个实施例的半导体封装结构的横截面图。
图7是根据本揭露的一或多个实施例的半导体封装结构的横截面图。
图8A、8B、8C、8D、8E、8F、8G、8H及8I是根据本揭露的一或多个实施例的制造半导体封装结构的各种操作的一者中的横截面图。
图9是根据本揭露的一或多个实施例的半导体封装结构的横截面图。
图10是根据本揭露的一或多个实施例的半导体封装结构的横截面图。
具体实施方式
本申请案主张2016年9月2日申请的美国临时申请案第62/382,912号的优先权，所述案的全文以引用的方式并入。
以下揭露提供用于实施所提供的目标的不同特征的诸多不同实施例或实例。下文将描述组件及布置的特定实例以简化本揭露。当然，此类仅为实例且不意在限制。例如，在以下描述中，“使第一构件形成在第二构件上方或第二构件上”可包含其中形成直接接触的所述第一构件及所述第二构件的实施例，且还可包含其中可形成介于所述第一构件与所述第二构件之间的额外构件使得所述第一构件及所述第二构件可不直接接触的实施例。另外，本揭露可在各种实例中重复组件符号及/或字母。此重复是为了简化及清楚且其本身不指示所讨论的各种实施例及/或配置之间的关系。
此外，为便于描述，诸如“下面”、“下方”、“下”、“上方”、“上面”、“上”及其类似者的空间相对术语可在本文中用于描述一组件或构件与另外(若干)组件或(若干)构件的关系，如图中所绘示。空间相对术语除涵盖图中所描绘的定向之外，还旨在涵盖装置在使用或操作中的不同定向。设备可依其它方式定向(旋转90度或依其它定向)且还可相应地解译本文所使用的空间相对描述词。
如本文所使用，诸如“第一”、“第二”及“第三”的术语描述各种组件、组件、区域、层及/或区段，此类组件、组件、区域、层及/或区段应不受限于此类术语。此类术语可仅用于区分一组件、组件、区域、层或区段与另一组件、组件、区域、层或区段。除非内文明确指示，否则本文所使用的诸如“第一”、“第二”及“第三”的术语不隐含序列或顺序。
如本文所使用，术语“近似”、“实质上”、“实质”及“约”用于描述及解释小变动。当所述术语与事件或状况一起使用时，所述术语可涉及其中所述事件或状况精确发生的例项以及其中所述事件或状况非常近似发生的例项。例如，当所述术语与数值一起使用时，所述术语可涉及小于或等于所述数值的±10％的变动范围，诸如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％。例如，如果两个数值之间的差值小于或等于所述值的平均值的±10％(诸如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％)，那么所述值可被视为“实质上”相同或相等。例如，“实质上”平行可涉及小于或等于±10°的相对于0°的角变动范围，诸如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或小于或等于±0.05°。例如，“实质上”垂直可涉及小于或等于±10°的相对于90°的角变动范围，诸如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或小于或等于±0.05°。
如本文所使用，术语“载体衬底”或“暂时衬底”指代经配置为中间衬底以用于上覆层(诸如重布层、芯片、囊封物及其它结构)的制造设施或用于切割的载体。载体衬底或暂时衬底提供暂时支撑及固定功能，且会从上覆结构去除。
如本文所使用，术语“重布层(RDL)”指代由至少一个导电图案及至少一个绝缘层形成且经配置以与两个或多于两个装置电通信的一层堆叠。
如本文所使用，术语“导电凸块”指代经配置以透过其两端使两个导电结构电互连的导体。在一或多个实施例中，导电凸块由可通过低温操作而形成的低熔点材料形成。导电凸块形成在形成包围互连凸块的侧壁的囊封物之前。在一或多个实施例中，导电凸块是焊料凸块、焊料膏或其类似者。
如本文所使用，术语“导电柱”指代通过可实施精细节距的沉积、光刻及蚀刻操作而形成的导体。
如本文所使用，术语“中介层”是互连结构，其经配置以将安置在所述互连结构的两个对置表面上的两个或多于两个电子装置(诸如芯片、重布层或封装)电连接。在一或多个实施例中，中介层是预成形互连结构，其可安置在待互连到另一电子装置的电子装置的一者上。在一或多个实施例中，中介层包含具有精细节距的若干通孔结构，诸如穿硅通孔(TSV)。
如本文所使用，术语“穿绝缘体通孔(TIV)”是贯穿绝缘体且经配置以透过其两端将两个导电结构电连接的导体。
在本揭露的一或多个实施例中，半导体封装结构包含位于囊封物中且介于两个电子装置之间的芯片，且电子装置的各者独立地包含重布层、半导体裸片或封装。在一或多个实施例中，芯片的一部分包含经配置以提供两个电子装置之间的高密度互连的通孔结构(诸如TSV)，而芯片的另一部分无需通孔结构来电连接到电子装置的一者。具有通孔结构的芯片提供用于两个电子装置之间的互连的短信号路径。在一些实施例中，具有通孔结构的芯片是不具有集成在其内的有源装置的中介层。在一些实施例中，具有通孔结构的芯片是包含集成在其内的TSV的有源装置芯片。在一或多个实施例中，穿绝缘体通孔(TIV)可布置在囊封物中以提供两个电子装置之间的额外信号路径来提高选路灵活性。在一或多个实施例中，半导体封装结构是扇出晶片级封装(FOWLP)。
图1是绘示根据本揭露的各种方面的用于制造半导体封装结构的方法的流程图。方法100开始于其中形成第一重布层的操作110。方法100继续到其中将第一芯片安置在所述第一重布层上方的操作120。方法100前进到其中将第二芯片安置在所述第一重布层上方的操作130，其中所述第二芯片包含多个通孔结构。方法100前进到其中使囊封物形成在所述第一重布层上方的操作140。方法100前进到其中将第三芯片安置在所述囊封物上方的操作150，其中所述第三芯片及所述第一重布层透过所述第二芯片的所述通孔结构电连接。
方法100仅为实例，且不旨在限制本揭露超出权利要求书中明确叙述的内容的范围。可在方法100之前、在方法100期间及在方法100之后提供额外操作，且可针对方法的额外实施例替换、消除或移动所描述的一些操作。
图2A、2B、2C、2D、2E、2F、2G、2H、2I、2J及2K是根据本揭露的一或多个实施例的制造半导体封装结构的各种操作的一者中的横截面图。如图2A中所描绘，第一重布层20形成在载体衬底10上方。在一或多个实施例中，载体衬底10经配置为用于形成重布层(诸如第一重布层20)的暂时衬底，且随后会被去除。在一或多个实施例中，载体衬底10是诸如玻璃衬底的绝缘衬底。载体衬底10可包含半导体衬底(诸如硅衬底)、导电衬底(诸如金属衬底)或其它适合衬底。
第一重布层20具有彼此对置的第一表面201及第二表面202。在一些实施例中，第一重布层20的第二表面202面向载体衬底10。第一重布层20由至少一个导电层22及至少一个绝缘层24形成，且经配置以与两个或多于两个芯片电通信。在一或多个实施例中，第一重布层20包含彼此堆叠的若干导电层22及若干绝缘层24。在一些实施例中，(若干)导电层22的材料可包含(但不限于)金属，诸如铜、钛、其类似者或其组合。(若干)绝缘层24的材料可包含(但不限于)无机及/或有机绝缘材料。
在一或多个实施例中，导电层22包含不同图案且彼此电连接。在一或多个实施例中，最上导电层22的一部分从第一重布层20的第一表面201暴露。在一或多个实施例中，若干接合垫26(诸如凸块下金属(UBM))形成在第一重布层20的最上导电层22的暴露部分上方且电连接到第一重布层20的最上导电层22的暴露部分。
如图2B中所描绘，一或多个第一芯片30安置在第一重布层20的第一表面201上方。在一或多个实施例中，第一芯片30电连接到第一重布层20。在一或多个实施例中，第一芯片30包含有源装置芯片及/或无源装置芯片。举例来说，有源装置芯片可包含芯片上系统(SOC)及/或其它芯片。无源装置芯片可包含形成在其内的电阻器、电容器、电感器或其组合。在一些实施例中，无源装置芯片可呈(但不限于)集成电路的形式。第一芯片30可透过表面粘着技术(SMT)或其它适合接合技术安装在第一重布层20上。在一些实施例中，第一芯片30包含若干电端子30P，且第一芯片30通过透过导电材料32(诸如导电膏、导电凸块或其它适合导电材料)将电端子30P接合到接合垫26的一部分而电连接到第一重布层20。
一或多个第二芯片36安置在第一重布层20上方且电连接到第一重布层20。在一或多个实施例中，第二芯片36包含诸如通孔结构36C的若干互连件。举例来说，通孔结构36C是穿硅通孔(TSV)。第二芯片36经配置以使安置在两个对置侧上的第一重布层20及另一装置(诸如第三芯片或第二重布层)互连，且可实施相邻通孔结构36C之间的精细节距。在一些实施例中，第二芯片36是形成为集成电路形式且无有源装置集成在其内的中介层。在一些实施例中，第二芯片36是包含集成在其内的TSV的有源装置芯片，诸如SOC。在一或多个实施例中，第二芯片36可更包含诸如金属-绝缘体-金属(MIM)电容器的嵌入式无源装置。第二芯片36可透过SMT或其它适合接合技术安装在第一重布层20上。在一些实施例中，第二芯片36包含若干接触垫36P，且第二芯片36通过透过导电材料38(诸如导电膏、导电凸块或其它适合导电材料)将接触垫36P接合到接合垫26的另一部分而电连接到第一重布层20。在一或多个实施例中，第二芯片36及第一芯片30具有实质上相同高度且位于实质上相同层级处。在一或多个实施例中，通孔结构36C包含两个端子，其中通孔结构36C的第一端子C1透过(例如)接触垫36P耦合到第一重布层20，且通孔结构36C的第二端子C2经配置以耦合到(若干)第三芯片或待形成的第二重布层。在一或多个实施例中，通孔结构36C的第二端子C2嵌入第二芯片36中，且将在后续操作中被暴露。
如图2C中所描绘，囊封物(诸如第一囊封物40)形成在第一重布层20的第一表面201上方。在一或多个实施例中，第一囊封物40的材料是模塑料。在一些实施例中，底胶填充层42可形成在第一芯片30与第一重布层20之间及形成在第二芯片36与第一重布层20之间。在一些实施例中，第一囊封物40是成型底胶填充(MUF)层且因此可无需额外底胶填充层。在一或多个实施例中，第一囊封物40覆盖第一芯片30及第二芯片36的上表面及侧壁。
如图2D中所描绘，通过(例如)研磨而去除第一囊封物40的一部分以暴露第二芯片36的第二端子C2。在一或多个实施例中，第一囊封物40通过研磨而薄化。
如图2E中所描绘，绝缘层44形成在第一囊封物40上方。在一或多个实施例中，绝缘层44的材料可包含(但不限于)诸如PBO的有机绝缘材料。绝缘层44包含暴露第二芯片36的第二端子C2的若干开口。若干接合垫46形成在绝缘层44上方且透过绝缘层44的开口电连接到第二芯片36的第二端子C2。在一或多个实施例中，接合垫46可包含(但不限于)凸块下金属(UBM)。
如图2F中所描绘，一或多个第三芯片50安置在第一囊封物40上方且电连接到第二芯片36。在一或多个实施例中，第三芯片50包含封装或存储器芯片。举例来说，第三芯片50包含彼此堆叠且电连接的若干DRAM装置52。在一或多个实施例中，DRAM装置52包含通孔结构56且透过诸如微导电凸块的互连件54而彼此电连接。第三芯片50可透过SMT或其它适合接合技术安装在第二芯片36上。在一些实施例中，第三芯片50透过导电材料48(诸如导电膏、导电凸块或其它适合导电材料)电连接到第二芯片36的接合垫46。
如图2G中所描绘，第二囊封物58形成在第一囊封物40上方。在一或多个实施例中，第二囊封物58的材料是模塑料。在一些实施例中，底胶填充层59可形成在第三芯片50与第一囊封物40之间。在一些实施例中，第二囊封物58是成型底胶填充(MUF)层且因此无需额外底胶填充层。在一或多个实施例中，第二囊封物58覆盖第三芯片50的上表面及侧壁。在一些实施例中，第三芯片50可包含光电芯片(诸如CMOS图像传感器芯片)、MEMS芯片、存储器芯片、高功率芯片，且第二囊封物58可(例如)通过研磨而薄化以暴露第三芯片50的上表面。
如图2H中所描绘，第二囊封物58附着到暂时衬底60。在一或多个实施例中，暂时衬底60是柔性膜，诸如固定在框架62上的胶带。在一些实施例中，暂时衬底60可包含其它类型的衬底，诸如刚性衬底。接着，载体衬底10从第一重布层20的第二表面202拆离。
如图2I中所描绘，第一重布层20的一部分从第二表面202去除以暴露经配置为接合垫的最下导电层22。在一或多个实施例中，第一重布层20通过诸如干式蚀刻的蚀刻而去除。
如图2J中所描绘，若干导体64形成在第一重布层20的第二表面202上方且电连接到第一重布层20。在一或多个实施例中，导体64包含(但不限于)导电凸块。在一或多个实施例中，一或多个第四芯片66安置在第一重布层20的第二表面202上方且电连接到第一重布层20。在一或多个实施例中，第四芯片66包含无源装置芯片。举例来说，无源装置芯片可包含形成在其内的电阻器、电容器、电感器或其组合。在一些实施例中，无源装置芯片可呈(但不限于)集成电路的形式。在一或多个实施例中，执行单粒化操作以形成若干半导体封装结构1。接着，半导体封装结构1从暂时衬底60去除，如图2K中所展示。
在半导体封装结构1中，第一芯片30透过面向第一重布层20的电端子30P电连接到第一重布层20。第三芯片50透过具有通孔结构36C(其具有精细节距)的第二芯片36电连接到第一重布层20。第二芯片36提供用于第一芯片30与第三芯片50之间的互连的短信号路径。第二芯片36避免在第一芯片30中形成通孔结构，其有助于改进第一芯片30的成出率。第二芯片36经配置以提供可与具有高I/O密度的芯片(诸如存储器芯片)集成的数目增加I/O计数。
本揭露的半导体封装结构不受限于上文所提及的实施例，而是可具有其它不同实施例。为简化描述且为便于本揭露的实施例的各者之间进行比较，以下实施例的各者中的相同组件使用相同组件符号来标记。为易于比较实施例之间的差异，以下描述将详述不同实施例之间的相异性且将不赘述相同构件。
图3是根据本揭露的一或多个实施例的半导体封装结构的横截面图。如图3中所描绘，半导体封装结构2包含安置在第一重布层20上方且电连接到第三芯片50及第一重布层20的两个或多于两个第二芯片36。
图4A、4B、4C、4D、4E、4F、4G、4H、4I、4J及4K是根据本揭露的一或多个实施例的制造半导体封装结构的各种操作的一者中的横截面图。如图4A中所描绘，第一重布层20形成在载体衬底10上方。第一重布层20具有彼此对置的第一表面201及第二表面202。在一些实施例中，第一重布层20的第二表面202面向载体衬底10。第一重布层20由至少一个导电层22及至少一个绝缘层24形成，且经配置以与两个或多于两个芯片电通信。在一或多个实施例中，最上导电层22的一部分从第一重布层20的第一表面201暴露。在一或多个实施例中，若干接合垫26(诸如凸块下金属(UBM))形成在第一重布层20的最上导电层22的暴露部分上方且电连接到第一重布层20的最上导电层22的暴露部分。
如图4B中所描绘，一或多个第一芯片30安置在第一重布层20的第一表面201上方。在一或多个实施例中，第一芯片30包含背向第一重布层20的第一表面201的若干电端子30P。在一些实施例中，电端子30P覆盖有钝化层33(诸如聚合层)且受钝化层33保护。在一或多个实施例中，第一芯片30透过粘着层31(诸如裸片附着膜(DAF))接合到第一重布层20的第一表面201。一或多个第二芯片36安置在第一重布层20上方且电连接到第一重布层20。
如图4C中所描绘，第一囊封物40形成在第一重布层20的第一表面201上方。在一或多个实施例中，第一囊封物40的材料是模塑料。在一些实施例中，底胶填充层42可形成在第一芯片30与第一重布层20之间及形成在第二芯片36与第一重布层20之间。在一些实施例中，第一囊封物40是成型底胶填充(MUF)层且因此无需额外底胶填充层。在一或多个实施例中，第一囊封物40覆盖第一芯片30及第二芯片36的上表面及侧壁。
如图4D中所描绘，通过(例如)研磨而去除第一囊封物40及钝化层33的一部分以暴露第二芯片36的第二端子C2及第一芯片30的电端子30P。在一或多个实施例中，第一囊封物40及钝化层33通过研磨而薄化。
如图4E中所描绘，绝缘层44形成在第一囊封物40上方。在一或多个实施例中，绝缘层44的材料可包含(但不限于)诸如PBO的有机绝缘材料。绝缘层44包含暴露第二芯片36的第二端子C2及第一芯片30的电端子30P的若干开口。
如图4F中所描绘，第二重布层70形成在第一囊封物40上方。第二重布层70具有彼此对置的第三表面703及第四表面704，且第三表面703面向第一表面201。第二重布层70透过第二端子C2电连接到第二芯片36且透过电端子30P电连接到第一芯片30。在一或多个实施例中，第二重布层70包含彼此堆叠的若干导电层72及若干绝缘层74。在一些实施例中，(若干)导电层72的材料可包含(但不限于)金属，诸如铜、钛、其类似者或其组合。(若干)绝缘层74的材料可包含(但不限于)无机及/或有机绝缘材料。第一芯片30透过第二重布层70电连接到第二芯片36。在一或多个实施例中，最上导电层72的一部分从第二重布层70的第四表面704暴露。在一或多个实施例中，若干接合垫76(诸如凸块下金属(UBM))形成在第二重布层70的最上导电层72的暴露部分上方且电连接到第二重布层70的最上导电层72的暴露部分。
如图4G中所描绘，一或多个第三芯片50安置在第二重布层70上方且电连接到第二重布层70。第三芯片50透过第二重布层70电连接到第一芯片30。在一些实施例中，第一芯片30的电端子30P的一部分透过第二重布层70的一部分电连接到第三芯片50，且第一芯片30的电端子30P的另一部分透过第二重布层70的另一部分电连接到第二芯片36。
如图4H中所描绘，第二囊封物58形成在第二重布层70上方以覆盖第三芯片50。
如图4I中所描绘，第二囊封物58附着到暂时衬底60。接着，载体衬底10从第一重布层20的第二表面202拆离。
如图4J中所描绘，第二重布层70的一部分从第四表面704去除以暴露经配置为接合垫的最下导电层72。在一或多个实施例中，第二重布层70通过诸如干式蚀刻的蚀刻而去除。若干导体64形成在第二重布层70的第四表面704上方且电连接到第二重布层70。在一或多个实施例中，导体64包含(但不限于)导电凸块。在一或多个实施例中，一或多个第四芯片66安置在第一重布层20的第二表面202上方且电连接到第二重布层70。在一或多个实施例中，执行单粒化操作以形成若干半导体封装结构3。接着，半导体封装结构3从暂时衬底60去除，如图4K中所展示。
在半导体封装结构3中，第三芯片50透过第二重布层70电连接到第一芯片30。第一芯片30透过面向第二重布层70的电端子30P电连接到第二重布层70。第一芯片30还透过第二重布层70及具有通孔结构36C(其具有精细节距)的第二芯片36电连接到第一重布层20。第二芯片36避免在第一芯片30中形成通孔结构，其有助于改进第一芯片30的成出率。第二芯片36经配置以提供可与具有高I/O密度的芯片(诸如存储器芯片)集成的数目增加I/O计数。
图5是根据本揭露的一或多个实施例的半导体封装结构的横截面图。如图5中所描绘，半导体封装结构4包含第一重布层20、一或多个第一芯片30、一或多个第二芯片36、第一囊封物40、第二重布层70及一或多个第三芯片50。第一芯片30安置在第一重布层20上方且透过电端子30P电连接到第一重布层20。第二芯片36安置在第一重布层20上方且电连接到第一重布层20及第二重布层70。第一囊封物40安置在第一重布层20上方，且包围第一芯片30及第二芯片36。第二重布层70安置在第一囊封物40上方。第三芯片50安置在第二重布层70上方且电连接到第二重布层70。在一或多个实施例中，半导体封装结构4更包含安置在第二重布层70上方的第二囊封物58及安置在第二囊封物58上方的一或多个第五芯片82。在一或多个实施例中，第五芯片82是诸如存储器封装的封装。在一或多个实施例中，第二囊封物58是成型底胶填充(MUF)层。在一或多个实施例中，第二囊封物58是底胶填充(UF)层。第五芯片82透过第二囊封物58中的第一互连件78电连接到第二重布层70。在一或多个实施例中，第一互连件78是(但不限于)导电凸块。
图6是根据本揭露的一或多个实施例的半导体封装结构的横截面图。如图6中所描绘，不同于半导体封装结构4，半导体封装结构5更包含介于第三芯片50与第二重布层70之间的底胶填充层59。在一或多个实施例中，第二囊封物58经配置为包围底胶填充层59的第二底胶填充层。
图7是根据本揭露的一或多个实施例的半导体封装结构的横截面图。如图7中所描绘，不同于半导体封装结构5，半导体封装结构6的第一互连件78包含导电凸块782及导电柱781，且导电凸块782耦合到导电柱781。在一或多个实施例中，导电凸块782是焊料凸块或焊料膏，其中导电凸块782的一端电连接到第五芯片82，且另一端电连接到各自导电柱781。导电柱781及导电凸块782的制造及材料是不同的。在一或多个实施例中，导电柱781通过沉积、光刻及蚀刻操作而形成，且因此可减小相邻导电柱781之间的节距。相应地，与导电凸块782相关联的导电柱781能够实现第二重布层70与第五芯片82之间的精细节距接合。在一或多个实施例中，第二囊封物58包含模塑料581及位于模塑料581上方的底胶填充层582。模塑料581安置在第二重布层70上方且包围第一芯片30及导电柱781的侧壁。底胶填充层582包围导电凸块782的侧壁。
图8A、8B、8C、8D、8E、8F、8G、8H及8I是根据本揭露的一或多个实施例的制造半导体封装结构的各种操作的一者中的横截面图。如图8A中所描绘，第一重布层20形成在载体衬底10上方。在一或多个实施例中，第二互连件84形成在第一重布层20的第一表面201上方且电连接到第一重布层20的第一表面201。在一些实施例中，第二互连件84是穿绝缘体通孔(TIV)。
如图8B中所描绘，一或多个第一芯片30安置在第一重布层20的第一表面201上方。一或多个第二芯片36安置在第一重布层20上方且电连接到第一重布层20。在一些实施例中，第一芯片30可包含不同类型的芯片且可具有不同厚度。举例来说，一些第一芯片30可包含诸如芯片上系统(SOC)的有源装置芯片，且一些第一芯片30可包含无源装置芯片。
如图8C中所描绘，第一囊封物40形成在第一重布层20的第一表面201上方。在一或多个实施例中，第一囊封物40的材料是模塑料。在一些实施例中，底胶填充层42可形成在第一芯片30与第一重布层20之间及形成在第二芯片36与第一重布层20之间。在一些实施例中，第一囊封物40是成型底胶填充(MUF)层且因此可无需额外底胶填充层。
如图8D中所描绘，通过(例如)研磨而去除第一囊封物40的一部分以暴露第二芯片36的第二端子C2。
如图8E中所描绘，绝缘层44形成在第一囊封物40上方。绝缘层44包含暴露第二芯片36的第二端子C2的开口。第二重布层70形成在第一囊封物40上方。第二重布层70透过第二端子C2电连接到第二芯片36。在一或多个实施例中，第二重布层70包含彼此堆叠的若干导电层72及若干绝缘层74。在一或多个实施例中，最上导电层72的一部分从第二重布层70的第四表面704暴露。在一或多个实施例中，若干接合垫76(诸如凸块下金属(UBM))形成在第二重布层70的最上导电层72的暴露部分上方且电连接到第二重布层70的最上导电层72的暴露部分。
如图8F中所描绘，一或多个第三芯片50安置在第二重布层70上方且电连接到第二重布层70。在一些实施例中，第三芯片50的一部分透过第二重布层70及第一芯片30电连接到第一重布层20。在一些实施例中，第三芯片50的另一部分透过第二重布层70及第二互连件84电连接到第一重布层20。在一些实施例中，第三芯片50的一部分经由接合线51(诸如金线)电连接到第二重布层70。在一或多个实施例中，第三芯片50包含存储器芯片、光电芯片、MEMS芯片、无源芯片或其组合。
如图8G中所描绘，第二囊封物58形成在第二重布层70上方以覆盖第三芯片50。
如图8H中所描绘，第二囊封物58附着到暂时衬底60。接着，载体衬底10从第一重布层20的第二表面202拆离。在一些实施例中，第二重布层70的一部分从第四表面704去除以暴露经配置为接合垫的最下导电层72。在一或多个实施例中，第二重布层70通过诸如干式蚀刻的蚀刻而去除。若干导体64形成在第二重布层70的第四表面704上方且电连接到第二重布层70。在一或多个实施例中，导体64包含(但不限于)导电凸块。在一或多个实施例中，一或多个第四芯片66安置在第一重布层20的第二表面202上方且电连接到第二重布层70。在一或多个实施例中，执行单粒化操作以形成若干半导体封装结构7。接着，半导体封装结构7从暂时衬底60去除，如图8I中所展示。
图9是根据本揭露的一或多个实施例的半导体封装结构的横截面图。如图9中所描绘，半导体封装结构8的一或多个第三芯片50的上表面50U从第二囊封物58暴露，使得第三芯片50能够建立外部通信。在一些实施例中，第三芯片50可包含光电芯片(诸如CMOS图像传感器芯片)、MEMS芯片及高功率芯片。
图10是根据本揭露的一或多个实施例的半导体封装结构的横截面图。如图10中所描绘，半导体封装结构9更包含第二囊封物58及第三芯片50上方的散热器90。散热器90由具有高导热性的材料(诸如金属)形成且经配置以改进第三芯片50的散热性。在一些实施例中，第三芯片50可包含光电芯片(诸如CMOS图像传感器芯片)、MEMS芯片、存储器芯片、高功率芯片、在操作期间产生热的其它芯片或其它热敏芯片。
在一或多个实施例中，半导体封装结构包含诸如芯片的若干堆叠电子装置。包含通孔结构的第二芯片经安置以提供两个电子装置之间的高密度互连及高选路灵活性。第二芯片提供用于芯片之间的互连的短信号路径。在一或多个实施例中，半导体封装结构是扇出晶片级封装(FOWLP)。在一或多个实施例中，半导体封装结构与具有小外型尺寸的多层堆叠芯片兼容。在一或多个实施例中，半导体封装结构与异质集成设计(其中可集成具有不同大小及厚度的不同电子装置，诸如半导体裸片、芯片、封装及中介层)兼容。在一或多个实施例中，半导体封装结构与散热器兼容以增强散热能力。
在一例示性方面中，一种半导体封装结构包含重布层(RDL)、第一芯片、第二芯片、囊封物及第三芯片。所述重布层具有彼此对置的第一表面及第二表面。所述第一芯片位于所述重布层的所述第一表面上方且电连接到所述重布层。所述第二芯片位于所述重布层的所述第一表面上方且电连接到所述重布层。所述第二芯片包含多个通孔结构。所述囊封物位于所述重布层的所述第一表面上方，其中所述囊封物包围所述第一芯片及所述第二芯片。所述第三芯片位于所述囊封物上方且透过所述第二芯片的所述通孔结构及所述重布层电连接到所述第一芯片。
在另一例示性方面中，一种半导体封装结构包含第一重布层(RDL)、第一芯片、第二芯片、第一囊封物、第二重布层、第三芯片及第二囊封物。所述第一重布层具有彼此对置的第一表面及第二表面。所述第一芯片位于所述第一重布层的所述第一表面上方。所述第二芯片位于所述第一重布层的所述第一表面上方。所述第二芯片包含多个通孔结构，且所述通孔结构的第一端子耦合到所述第一重布层。所述第一囊封物位于所述第一重布层的所述第一表面上方，其中所述第一囊封物包围所述第一芯片及所述第二芯片。所述第二重布层位于所述第一囊封物上方且电连接到所述通孔结构的第二端子。所述第二重布层具有彼此对置的第三表面及第四表面，且所述第三表面面向所述第一表面。所述第三芯片位于所述第二重布层的所述第四表面上方且电连接到所述第二重布层。所述第二囊封物位于所述第二重布层上方。
在又一方面中，一种用于制造半导体封装结构的方法包含以下操作。形成第一重布层。将第一芯片安置在所述第一重布层上方。将第二芯片安置在所述第一重布层上方，其中所述第二芯片包含多个通孔结构。使囊封物形成在所述第一重布层上方。使第三芯片形成在所述囊封物上方，其中所述第三芯片及所述第一重布层透过所述第二芯片的所述通孔结构电连接。
上文已概述若干实施例的结构，使得所属领域的技术人员可较佳理解本揭露的方面。所属领域的技术人员应了解，其可容易地使用本揭露作为设计或修改用于实施相同目的及/或达成本文所引入的实施例的相同优点的其它制程及结构的基础。所属领域的技术人员还应认识到，此类等效构造不应背离本揭露的精神及范围，且其可在不背离本揭露的精神及范围的情况下对本文作出各种改变、取代及更改。
符号说明
1 半导体封装结构
2 半导体封装结构
3 半导体封装结构
4 半导体封装结构
5 半导体封装结构
6 半导体封装结构
7 半导体封装结构
8 半导体封装结构
9 半导体封装结构
10 载体衬底
20 第一重布层
22 导电层
24 绝缘层
26 接合垫
30 第一芯片
30P 电端子
31 粘着层
32 导电材料
33 钝化层
36 第二芯片
36C 通孔结构
36P 接触垫
38 导电材料
40 第一囊封物
42 底胶填充层
44 绝缘层
46 接合垫
48 导电材料
50 第三芯片
50U 上表面
51 接合线
52 DRAM装置
54 互连件
56 通孔结构
58 第二囊封物
59 底胶填充层
60 暂时衬底
62 框架
64 导体
66 第四芯片
70 第二重布层
72 导电层
74 绝缘层
76 接合垫
78 第一互连件
82 第五芯片
84 第二互连件
90 散热器
100 方法
110 操作
120 操作
130 操作
140 操作
150 操作
201 第一表面
202 第二表面
581 模塑料
582 底胶填充层
703 第三表面
704 第四表面
781 导电柱
782 导电凸块
C1 第一端子
C2 第二端子

Claims (20)

1.一种半导体封装结构，其包括：
重布层，其具有彼此对置的第一表面及第二表面；
第一芯片，其位于所述重布层的所述第一表面上方且电连接到所述重布层；
第二芯片，其位于所述重布层的所述第一表面上方，其中所述第二芯片包含多个通孔结构；
囊封物，其位于所述重布层的所述第一表面上方，其中所述囊封物包围所述第一芯片及所述第二芯片；
第三芯片，其位于所述囊封物上方且透过所述第二芯片的所述通孔结构及所述重布层电连接到所述第一芯片；
第四芯片，其位于所述重布层的所述第二表面上方且电连接到所述重布层；以及
多个导体，其安置在所述重布层的所述第二表面上方且电连接到所述重布层，其中所述第四芯片和所述多个导体在所述第二表面上方基本上安置在同一水平面上。
2.根据权利要求1所述的半导体封装结构，其中所述第一芯片包含多个电端子，所述多个电端子面向所述重布层的所述第一表面且电连接到所述重布层。
3.根据权利要求1所述的半导体封装结构，其中所述通孔结构的第一端子耦合到所述重布层，且所述通孔结构的第二端子耦合到所述第三芯片。
4.根据权利要求1所述的半导体封装结构，其中所述第一芯片和所述第二芯片在电路层上方处于基本上相同的水平。
5.根据权利要求1所述的半导体封装结构，其中所述第四芯片的高度小于所述多个导体的高度。
6.一种半导体封装结构，其包括：
第一重布层，其具有彼此对置的第一表面和第二表面；
第一芯片，其位于所述第一重布层的所述第一表面上方；
第二芯片，其位于所述第一重布层的所述第一表面上方，其中所述第二芯片包含多个通孔结构，且所述通孔结构的第一端子耦合到所述第一重布层；
第一囊封物，其位于所述第一重布层的所述第一表面上方，其中所述第一囊封物包围所述第一芯片和所述第二芯片；
第二重布层，其位于所述第一囊封物上方且电连接到所述通孔结构的第二端子，其中所述第二重布层具有彼此对置的第三表面和第四表面，且所述第三表面面向所述第一表面；
第三芯片，其位于所述第二重布层的所述第四表面上方且电连接到所述第二重布层；
第二囊封物，其位于所述第二重布层上方；
第四芯片，其位于所述第一重布层的所述第二表面上方且电连接到所述第一重布层；以及
多个导体，其安置在所述第一重布层的所述第二表面上方且电连接到所述第一重布层，其中所述第四芯片和所述多个导体在所述第二表面上方基本上安置在同一水平面上。
7.根据权利要求6所述的半导体封装结构，其中所述第一芯片包含多个电端子，所述多个电端子面向并电连接到所述第二重布层的所述第三表面，所述第一芯片的所述电端子的部分通过所述第二重布层的部分电连接到所述第三芯片，且所述第一芯片的所述电端子的另一部分通过所述第二重布层的另一部分电连接到所述第二芯片。
8.根据权利要求6所述的半导体封装结构，其进一步包括多个互连器，所述多个互连器位于所述第一囊封物中且电连接到所述第一重布层和所述第二重布层。
9.根据权利要求8所述的半导体封装结构，其中所述互连器穿过绝缘体通孔。
10.根据权利要求6所述的半导体封装结构，其中所述第二囊封物暴露所述第三芯片的上表面。
11.根据权利要求6所述的半导体封装结构，其中所述第四芯片的高度小于所述多个导体的高度。
12.一种半导体封装结构，其包括：
第一芯片和第二芯片，所述第一芯片和所述第二芯片位于电路层的第一表面上方；
多个通孔结构，其位于所述第二芯片内；
第三芯片，其位于所述第一芯片和所述第二芯片上方，且通过所述通孔结构和所述电路层电连接到所述第一芯片；
囊封物，其位于所述电路层的所述第一表面上方；
第二电路层，其位于所述囊封物上方，所述第二电路层具有面向所述电路层的所述第一表面的表面，其中所述第一芯片包含多个电端子，所述多个电端子面向并电连接到所述第二电路层的所述表面，所述第一芯片的所述电端子的部分通过所述第二电路层的部分电连接到所述第三芯片，且所述第一芯片的所述电端子的另一部分通过所述第二电路层的另一部分电连接到所述第二芯片；
第四芯片，其位于所述电路层的第二表面上方且电连接到所述电路层；以及
多个导体，其安置在所述电路层的所述第二表面上方且电连接到所述电路层，其中所述第四芯片和所述多个导体在所述第二表面上方基本上安置在同一水平面上。
13.根据权利要求12所述的半导体封装结构，其中所述第一芯片和所述第二芯片在电路层上方处于基本上相同的水平。
14.根据权利要求12所述的半导体封装结构，其中所述第一芯片和所述第二芯片具有基本上相同的高度。
15.根据权利要求12所述的半导体封装结构，其中所述第四芯片的高度小于所述多个导体的高度。
16.根据权利要求12所述的半导体封装结构，其进一步包括第二囊封物，所述第二囊封物位于所述第二电路层上方。
17.根据权利要求16所述的半导体封装结构，其进一步包括第五芯片，所述第五芯片位于所述第二囊封物上方。
18.根据权利要求17所述的半导体封装结构，其进一步包括多个互连器，所述多个互连器位于所述第二囊封物中且电连接到所述第二电路层。
19.根据权利要求18所述的半导体封装结构，其中所述互连器包括导电凸块。
20.根据权利要求18所述的半导体封装结构，其中所述互连器包括导电柱和堆叠在所述导电柱上的导电凸块。
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