CN107769784A - Oversampling type Pipeline SAR-ADC system - Google Patents
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Abstract
The invention discloses an oversampling Pipeline SAR-ADC system which comprises an oversampling switch, an analog-digital conversion system and a digital bit expansion system which are sequentially connected, wherein the analog-digital conversion system comprises successive approximation type analog-digital conversion modules and a register, the number of the successive approximation type analog-digital conversion modules is N, N is a positive integer greater than or equal to 2, the N successive approximation type analog-digital conversion modules are sequentially connected to form N orders, the order of each successive approximation type analog-digital conversion module corresponds to the order of signals input in all the successive approximation type analog-digital conversion modules, and the digital output end of each successive approximation type analog-digital conversion module is connected with the input end of the register. The digital bit expansion system comprises a digital bit increasing module and a clock control module, wherein the digital bit increasing module comprises a cascade integral comb filter and a moving average filter connected with the cascade integral comb filter. The invention has the advantages of less used components, convenient realization, low cost and capability of improving the output rate and the resolution ratio during application.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an oversampling Pipeline SAR-ADC system.
Background
An analog-to-digital converter (ADC) is a key device for converting an analog signal into a digital signal, and plays a crucial role in the fields of aerospace and defense, automotive applications, software radio, consumer electronics, video monitoring and image acquisition, radar communication, and the like. With the continuous development of modern technology, the requirements of the fields on speed and resolution are continuously increased, and the requirements on the analog-digital converter are higher and higher.
The traditional analog-to-digital converter often adopts a Pipeline-ADC structure and an SAR-ADC structure, wherein the Pipeline-ADC structure has the following defects when being applied: first, the Pipeline-ADC is greatly affected by capacitance mismatch, which results in a great limitation on the Pipeline-ADC resolution; secondly, the Pipeline-ADC needs to be equipped with an error correction module, which increases the power consumption and area of the ADC, and limits its application in the fields of industrial control and the like. The SAR-ADC structure has the following disadvantages when applied: the SAR-ADC adopts a gradual approximation type voltage comparison method, so that the SAR-ADC cannot be applied to a high-speed environment, namely the sampling rate of the SAR-ADC is low.
Disclosure of Invention
The invention aims to solve the problems of low resolution and low sampling rate of the traditional analog-to-digital converter, and provides an oversampling type Pipeline SAR-ADC system which has the advantage of structural combination of Pipeline and SAR-ADC and can improve the output rate and resolution.
The invention mainly solves the problems by the following technical scheme: an oversampling-type Pipeline SAR-ADC system comprises an oversampling switch, an analog-to-digital conversion system and a digital bit-expanding system which are sequentially connected, wherein the analog-to-digital conversion system comprises successive approximation type analog-to-digital conversion modules and a register, the number of the successive approximation type analog-to-digital conversion modules is N, N is a positive integer greater than or equal to 2, the N successive approximation type analog-to-digital conversion modules are sequentially connected to form N orders, the order of each successive approximation type analog-to-digital conversion module corresponds to the order of signals input in all the successive approximation type analog-to-digital conversion modules, and the digital output end of each successive approximation type analog-to-digital conversion module is connected with the input end of the register; the digital bit-expanding system comprises a digital bit increasing module and a clock control module, wherein the digital bit increasing module comprises a cascade integral comb filter and a moving average filter connected with the cascade integral comb filter; wherein,
the over-sampling switch is used for inputting an analog signal, sampling and outputting the analog signal;
the successive approximation type analog-to-digital conversion module is used for converting an analog signal input into the successive approximation type analog-to-digital conversion module into a digital signal and sending the digital signal to the register, wherein the signal input by the first-order successive approximation type analog-to-digital conversion module is a signal output by the oversampling switch;
the register is used for receiving the digital signals output by the successive approximation type analog-to-digital conversion module and combining the digital signals output by the N-order successive approximation type analog-to-digital conversion module into a streamline form for output;
the clock control module is used for providing clock signals for the cascade integration comb filter and the moving average filter;
the cascade integration comb filter is used for receiving a clock signal sent by the clock control module, receiving a digital code output by the register when receiving a trigger start clock signal, then performing integration and frequency reduction, and realizing increment of a digit in an integration process;
and the moving average filter is used for receiving the clock signal sent by the clock control module and removing clock jitter and inherent noise of the digital code output by the cascade integrator comb filter when receiving the trigger starting clock signal so as to realize smooth output.
When the invention is applied, the high-precision output is completed by the digital bit increasing module and the clock control module. In particular, the process of accumulating the digital code through a cascaded integrator-comb filter achieves an increase in the number of bits without requiring a large number of storage elements.
Furthermore, the successive approximation type analog-to-digital conversion module comprises two sampling switches, two capacitor arrays, two comparators, a logic control module and an output buffer module, wherein the two sampling switches are connected with the input ends of the two capacitor arrays in a one-to-one correspondence manner, and the output ends of the two capacitor arrays are respectively connected with the non-inverting input end and the inverting input end of the comparator; the output end of the comparator is connected with the input end of the logic control module, the digital control output end of the logic control module is connected with the digital bit control input end of the capacitor array, and the output end of the logic control module is connected with the input end of the output buffer module.
Furthermore, a signal amplifying circuit is arranged on a line between any two adjacent successive approximation type analog-to-digital conversion modules.
Further, the cascaded integrator-comb filter is formed by cascading a plurality of single-stage CIC filters.
Further, the CIC filter comprises an integrator, a decimator and a differentiator, and the integrator, the decimator and the differentiator are connected in sequence.
In conclusion, the invention has the following beneficial effects: (1) the invention has simple integral structure, less used components, convenient realization and low cost, and can effectively improve the output rate of the ADC by combining the SAR-ADC circuit structure with the Pipeline operation mode.
(2) The invention adopts a fully differential structure and a digital bit expansion technology, and can reduce noise and interference of capacitor mismatch.
(3) The invention can divide the full range from the maximum (first stage) to the minimum (N stages) by dividing the range step by step when being applied, each stage is converted by the SAR-ADC, and then the Pipeline type recombination output is formed, so that the resolution of the final output is greatly improved.
(4) The invention improves the resolution ratio and is not influenced by the change of the power supply voltage, and finally realizes the output of high resolution ratio and high linearity, thereby being beneficial to the popularization and application of the invention.
(5) The invention can be applied to various different input bit widths, so that the invention is more convenient to popularize and apply.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a schematic structural diagram of an embodiment of the present invention;
FIG. 2 is a block diagram of an analog-to-digital conversion system in an embodiment of the invention;
FIG. 3 is a block diagram of a successive approximation analog-to-digital conversion module of FIG. 2;
FIG. 4 is a block diagram of the digital bit expansion system of FIG. 1;
FIG. 5 is a schematic diagram of the structure of the cascaded integrator-comb filter of FIG. 4;
FIG. 6 is a block diagram of a single stage CIC filter;
FIG. 7 is a block diagram of an application of an embodiment of the present invention;
FIG. 8 is a simulation diagram of one embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
Example 1:
as shown in fig. 1 and fig. 2, an oversampling Pipeline SAR-ADC system includes an oversampling switch, an analog-to-digital conversion system, and a digital bit extension system, which are sequentially connected, where the analog-to-digital conversion system includes successive approximation analog-to-digital conversion modules and a register, where the number of the successive approximation analog-to-digital conversion modules is N, N is a positive integer greater than or equal to 2, and the N successive approximation analog-to-digital conversion modules are sequentially connected to form N stages. In this embodiment, the order of each successive approximation type analog-to-digital conversion module corresponds to the order of signals input in all successive approximation type analog-to-digital conversion modules, and the order of signals input by the N-order successive approximation type analog-to-digital conversion module is as follows: a first order successive approximation type analog-to-digital conversion module, a second order successive approximation type analog-to-digital conversion module, … … and an Nth order successive approximation type analog-to-digital conversion module. In the specific setting of this embodiment, a signal amplifying circuit is disposed on a line between any two adjacent successive approximation type analog-to-digital conversion modules. The oversampling switch of this embodiment is used to input an analog signal and output the analog signal after sampling, and a signal input by the first-order successive approximation type analog-to-digital conversion module is a signal output by the oversampling switch.
The Pipeline SAR-ADC system comprises successive approximation type analog-to-digital conversion modules and a register, wherein the number of the successive approximation type analog-to-digital conversion modules is N, N is a positive integer greater than or equal to 2, the N successive approximation type analog-to-digital conversion modules are sequentially connected to form N orders, the order of each successive approximation type analog-to-digital conversion module corresponds to the order of signals input in all the successive approximation type analog-to-digital conversion modules, and the digital output end of each successive approximation type analog-to-digital conversion module is connected with the input end of the register; the successive approximation type analog-to-digital conversion module is used for converting an analog signal input into the successive approximation type analog-to-digital conversion module into a digital signal and sending the digital signal to the register; and the register is used for receiving the digital signals output by the successive approximation type analog-to-digital conversion module and combining the digital signals output by the N-order successive approximation type analog-to-digital conversion module into a pipeline form for output.
In this embodiment, the digital output end of each successive approximation type analog-to-digital conversion module is connected to the input end of the register, and the successive approximation type analog-to-digital conversion module is configured to convert an analog signal input thereto into a digital signal and send the digital signal to the register; the register is used for receiving the digital signals output by the successive approximation type analog-to-digital conversion module and combining the digital signals output by the N-order successive approximation type analog-to-digital conversion module into a pipeline type for output.
As shown in fig. 4 and 5, the digital bit extension system of the present embodiment includes a digital bit adding module and a clock control module, wherein the digital bit adding module includes a cascaded integrator-comb filter and a moving average filter connected to the cascaded integrator-comb filter. The clocks of both the cascaded integrator-comb filter and the moving average filter of the present embodiment are connected to the clock signal terminal clk of the clock control module, and the clock control module is used for providing clock signals to the cascaded integrator-comb filter and the moving average filter. The cascade integration comb filter of the embodiment is used for receiving a clock signal sent by a clock control module, receiving a digital code output by a register when receiving a trigger start clock signal, then performing integration and frequency reduction, and realizing increment of a digit in an integration process. The moving average filter of the embodiment is used for receiving a clock signal sent by a clock control module, and removing clock jitter and inherent noise of an output signal of the cascaded integrator-comb filter when receiving a trigger start clock signal so as to realize smooth output.
The cascaded integrator-comb filter of the present embodiment is formed by cascading a plurality of single-stage CIC filters, wherein the structure diagram of the single-stage CIC filter is shown in fig. 6. The CIC filter comprises an integrator, a decimator and a differentiator which are connected in sequence.
In this embodiment, the decimation multiple of the single-stage CIC filter is D, and the time domain expression of the integrator is y1(n)＝y1(n-1)+x1(n) the time domain expression of the differentiator is y2(n)＝x2(n)-x2(n-D) wherein x1(n) is the digital code input to the integrator, y1(n) is the digital code, x, of the integrator output2(n) is the digital code input to the differentiator, y2And (n) is the digital code output by the differentiator. The cascade integration comb filter completes integration and frequency reduction by cascade connection of single-stage CIC multiple stages, each stage of integration process has increment of corresponding digit, and the increment digit isThe Q-stage CIC filters are connected in series to obtain the expression B of the total output digital quantityout＝Qlog2D+BinWherein Q is the cascade stage number, and Bin is the bit width of the input signal. Therefore, the expansion of the number of bits is realized, and the output frequency is reduced by D times. The moving average filter of the embodiment is mainly used for improving the reliability and the precision of system output, reasonably removing errors caused by circuit inherent noise and clock jitter, ensuring that the data precision is not reduced, improving the resolution and smoothly outputting. The time domain expression of the moving average filter isWhere n is the size of the moving average window, y3And (n) is the digital code output by the moving average filter.
When the embodiment is applied, the input of the cascade integrator-comb filter is b0、……、bmOutput ofThe output terminal of the moving average filter isThe resulting digital bit increase achieved is (1/2+ Qlog)2D) A bit.
When the embodiment is applied, the analog input signal x (t) is sampled into x (z) by the over-sampling mode (the sampling frequency is far greater and the bandwidth of the signal) through the switch OVERSAMP, the x (z) enters the first-order successive approximation type analog-to-digital conversion module, and the analog signal is converted into N through the first-order successive approximation type analog-to-digital conversion module1Bit digital signal D1Store to the register. The residual voltage V output by the first-order successive approximation type analog-to-digital conversion moduleo1Amplified into a voltage V by a signal amplifying circuiti2Voltage V ofi2Converting the analog signal into N by a second-order successive approximation type analog-to-digital conversion module2Bit digital signal D2Store to a register fromResidual voltage V output by second-order successive approximation type analog-to-digital conversion moduleo2Amplified into a voltage V by a signal amplifying circuiti3. By analogy, the input signal V is input in the last orderiNAfter entering the Nth order successive approximation type analog-to-digital conversion module, the analog signal is converted into NnBit digital signal Dn. And finally, after the N-bit digital output signal x (N) enters a digital bit expansion system, expanding the N-bit digital signal x (N) into (N + M) bits by the digital bit expansion system, and finally outputting an (N + M) -bit digital analog-to-digital conversion digital signal ADC (N).
As shown in fig. 7, the present embodiment employs and implements a 24-bit analog-to-digital converter (24-bit ADC). The analog input signal x (t) is sampled into x (z) by an oversampling switch and enters an analog-digital conversion system, after the analog-digital conversion system converts the x (z) into a 16-bit digital signal, the 16-bit digital signal is promoted to a 24-bit digital signal by a digital bit expansion system, and finally, a 24-bit digital analog-digital conversion digital signal is output. The sampling rate of the 24-bit oversampling type Pipeline SAR-ADC system is 33kHz, the reference voltage is 2.5V, and the input signal changes from 0V to 2.5V. The output result is that the significant digit (ENOB) reaches 16 bits, the Integral Nonlinearity (INL) is less than 0.5LSB, and the Differential Nonlinearity (DNL) is less than 0.5 LSB. Fig. 8 shows a simulation diagram of a 24-bit oversampled Pipeline SAR-ADC system by passing the output digital signal of the 24-bit oversampled Pipeline SAR-ADC system through an ideal DAC and comparing the analog signal output by the DAC with the input analog signal. Wherein the upper line in the coordinate system shown in fig. 8 is the voltage input signal varying from 0V to 2.5V and the lower line is the analog signal into which the circuit converts from the output digital signal. As can be seen from fig. 8, the voltage output signal of the circuit varies linearly and substantially corresponds to the voltage input signal.
Example 2:
this embodiment is further defined on the basis of embodiment 1 as follows: the successive approximation type analog-to-digital conversion module of the embodiment includes a sampling switch, a capacitor array, a comparator, a logic control module and an output buffer module, wherein the sampling switch, the capacitor array, the comparator, the logic control module and the output buffer module are connected to the output buffer moduleThe capacitor array has IN, OUT, G, H, L and C1-NThe pin and the logic control module are provided with IN, OUT, CLK and C1(1-N)And C2(1-N)And (7) a pin. In this embodiment, the number of the sampling switches and the number of the capacitor arrays are two, and the two sampling switches are sampling switches SAMP respectively1And a sampling switch SAMP2SAMP switch1And a sampling switch SAMP2Respectively connected with IN input ends of two capacitor arrays IN one-to-one correspondence, and input voltage Vip(t)By sampling switches SAMP1Input, input voltage Vin(t)By sampling switches SAMP2And (4) inputting. And OUT output ends of the two capacitor arrays are respectively connected with a non-inverting input end and an inverting input end of the comparator. The output end of the comparator is connected with the input end of the IN of the logic control module, and the C of the logic control module1(1-N)Digital control output and C of a capacitor array1-NC of digital bit control input end connection and logic control module2(1-N)C of digital control output end and another capacitor array1-NThe digital bit control input end is connected, and the OUT output end of the logic control module is connected with the input end of the output buffer module.
When the embodiment is applied, the reference high voltage V is input into the H ends of the two capacitor arraysrefHThe L ends of the two capacitor arrays are input with a reference low voltage VrefLThe G ends of the two capacitor arrays are input with a ground voltage GND, and the CLK Clock input end of the logic control module is input with a Clock signal. At the sampling phase, the sampling switch SAMP1SAMP (sampling switch)2Closed, differential positive input voltage Vip(t)By sampling switch SAMP1Form Vip(z)Entering a capacitor array, inputting a voltage V at the negative terminalin(t)By sampling switch SAMP2Form Vin(z)Into another capacitor array. Sampling switch SAMP during the comparison phase1SAMP (sampling switch)2Disconnecting, the comparator CMP compares the output voltages V of the two capacitor arrayspAnd VnThereby determining the output logic D of the comparator CMPcmpAnd inputting the data to a logic control module. Input to logic control module according to value of output voltageIN input, logic control module slave C1(1-N)Outputting control signals of corresponding digital positions to a control port C of a capacitor array1-NAnd from C2(1-N)Outputting control signals of corresponding digital positions to a control port C of another capacitor array1-NAnd further eliminating charges stored in the two capacitor arrays corresponding to the digital position, and simultaneously recording corresponding digital data of the digital position. After one comparison procedure is completed, the logic control module eliminates the charges stored in the capacitor array in the same way in successive cycles to complete the output data of all digital positions, and finally outputs the final digital data D in a pipeline (pipeline) formout. The output buffer signal D of the output buffer module can be selectively added according to specific requirementsbout。
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (5)
1. An oversampling-type Pipeline SAR-ADC system is characterized by comprising an oversampling switch, an analog-to-digital conversion system and a digital bit expansion system which are sequentially connected, wherein the analog-to-digital conversion system comprises successive approximation type analog-to-digital conversion modules and a register, the number of the successive approximation type analog-to-digital conversion modules is N, N is a positive integer greater than or equal to 2, the N successive approximation type analog-to-digital conversion modules are sequentially connected to form N orders, the order of each successive approximation type analog-to-digital conversion module corresponds to the order of signals input by the successive approximation type analog-to-digital conversion module in all the successive approximation type analog-to-digital conversion modules, and the digital output end of each successive approximation type analog-to-digital conversion module is connected with the input end of the register; the digital bit-expanding system comprises a digital bit increasing module and a clock control module, wherein the digital bit increasing module comprises a cascade integral comb filter and a moving average filter connected with the cascade integral comb filter; wherein,
the over-sampling switch is used for inputting an analog signal, sampling and outputting the analog signal;
the successive approximation type analog-to-digital conversion module is used for converting an analog signal input into the successive approximation type analog-to-digital conversion module into a digital signal and sending the digital signal to the register, wherein the signal input by the first-order successive approximation type analog-to-digital conversion module is a signal output by the oversampling switch;
the register is used for receiving the digital signals output by the successive approximation type analog-to-digital conversion module and combining the digital signals output by the N-order successive approximation type analog-to-digital conversion module into a streamline form for output;
the clock control module is used for providing clock signals for the cascade integration comb filter and the moving average filter;
the cascade integration comb filter is used for receiving a clock signal sent by the clock control module, receiving a digital code output by the register when receiving a trigger start clock signal, then performing integration and frequency reduction, and realizing increment of a digit in an integration process;
and the moving average filter is used for receiving the clock signal sent by the clock control module and removing clock jitter and inherent noise of the digital code output by the cascade integrator comb filter when receiving the trigger starting clock signal so as to realize smooth output.
2. The oversampling SAR-ADC system according to claim 1, wherein the successive approximation type analog-to-digital conversion module includes two sampling switches, two capacitor arrays, two comparators, a logic control module and an output buffer module, the two sampling switches are connected with the input ends of the two capacitor arrays in a one-to-one correspondence manner, and the output ends of the two capacitor arrays are respectively connected with the non-inverting input end and the inverting input end of the comparator; the output end of the comparator is connected with the input end of the logic control module, the digital control output end of the logic control module is connected with the digital bit control input end of the capacitor array, and the output end of the logic control module is connected with the input end of the output buffer module.
3. The oversampling synthetic aperture radar-ADC system according to claim 1, wherein a signal amplifying circuit is provided on a line between any two adjacent successive approximation type analog-to-digital conversion modules.
4. An oversampled Pipeline SAR-ADC system according to any of claims 1-3, wherein said cascaded integrator-comb filter is formed by a cascade of a plurality of single-stage CIC filters.
5. The oversampled Pipeline SAR-ADC system of claim 1, wherein said CIC filter comprises an integrator, a decimator, and a differentiator, said integrator, decimator, and differentiator being connected in series.
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