CN111711453B

CN111711453B - Successive approximation type analog-to-digital converter

Info

Publication number: CN111711453B
Application number: CN202010834430.9A
Authority: CN
Inventors: 刘筱伟; 刘盛富; 李建平; 班桂春; 向可强; 王强
Original assignee: Micro Niche Guangzhou Semiconductor Co Ltd
Current assignee: Micro Niche Guangzhou Semiconductor Co Ltd
Priority date: 2020-08-19
Filing date: 2020-08-19
Publication date: 2020-11-13
Anticipated expiration: 2040-08-19
Also published as: CN111711453A

Abstract

The invention provides a successive approximation type analog-to-digital converter, comprising: the first DAC module and the second DAC module are respectively divided into three sections, and the weight is gradually decreased from high to low; the input end of the first comparator is connected to the high-order weight sections of the first DAC module and the second DAC module respectively; the input end of the second comparator is respectively connected with the low-order weight sections of the first DAC module and the second DAC module; the first comparator works in the comparison stage of the high-order weight section and the middle-order weight section, and the second comparator works in the comparison stage of the low-order weight section; and the SAR logic module outputs a digital signal based on the comparison result output by the first comparison module and the second comparison module and generates a corresponding control signal. According to the invention, the two comparators work at different weight bit comparison stages respectively, so that the requirement on the comparator precision is reduced, the power consumption is not increased, and the design problem of the high-speed high-precision comparator is solved.

Description

Successive approximation type analog-to-digital converter

Technical Field

The invention relates to the field of integrated circuit design, in particular to a successive approximation type analog-to-digital converter.

Background

A high-precision Successive Approximation (SAR) ADC is a very common ADC, especially for some high-speed, high-precision and low-power applications. The SAR ADC main body structure comprises a DAC, a comparator and SAR logic. The DAC in the SAR ADC is realized by a capacitor type DAC and a resistor type DAC, the capacitor type DAC or a capacitor and resistor combination type SAR ADC is generally selected in a high-precision SAR ADC, a segmented capacitor array is generally used for compressing the area of a capacitor when the precision is more than 12 bits, the capacitor is generally divided into two sections when the precision is more than 12 bits, 14-18 bits are generally divided into three sections, the corresponding voltages at different sections are different, and the input of a comparator is generally fixed at the upper end of the highest section capacitor array. Comparators for high speed and high accuracy performance typically use a preamplifier and a rebuilt latch configuration, and the preamplifier uses multiple stages of amplification to identify weak signals. The SAR logic can select synchronous logic or asynchronous logic according to design requirements, the synchronous logic needs a fixed-frequency clock, the turnover of the DAC is triggered by a clock edge, and the time length of each comparison period is fixed; the asynchronous logic does not need a fixed clock, the next DAC is triggered to turn over according to the last comparator result, the clock edge does not need to wait for the arrival of the clock, the next conversion can be carried out as long as the comparator result is compared, and therefore the SAR logic in the high-speed SAR ADC is usually realized by adopting the asynchronous logic.

As application requirements become more stringent for the accuracy and speed of SAR ADCs, the design of SAR ADCs also faces a number of challenges. Of the three modules described above, the high-speed high-precision comparator is one of the cores of designing the SAR ADC with high speed and high precision. The high precision means that the signal to be identified by the comparator is very small, the high speed means that the comparison time of the comparator is very short, and the bandwidth of the preamplifier for realizing the high gain is necessarily reduced, especially in the comparison process of the low weight bit, the signal equivalent to the input end of the comparator is very weak, so in the design, the gain and the bandwidth of the comparator must be optimized, and the design difficulty is greatly improved.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present invention provides a successive approximation type analog-to-digital converter, which is used to solve the problem of difficulty in optimizing the gain and bandwidth of a high-precision comparator in the prior art.

To achieve the above and other related objects, the present invention provides a successive approximation type analog-to-digital converter, which at least includes:

the SAR analog-to-digital conversion circuit comprises a first DAC module, a second DAC module, a first comparison module, a second comparison module and an SAR logic module;

the first DAC module is divided into three sections, and the weight is gradually decreased from high to low; the second DAC module has the same structure as the first DAC module;

the input end of the first comparator is respectively connected with the high-order weight sections of the first DAC module and the second DAC module, and the input end of the second comparator is respectively connected with the low-order weight sections of the first DAC module and the second DAC module; the first comparator works in the comparison stage of the high-order weight section and the middle-order weight section, and the second comparator works in the comparison stage of the low-order weight section;

the SAR logic module is connected with the output ends of the first comparison module and the second comparison module, outputs a digital signal based on the comparison result output by the first comparison module and the second comparison module and generates a corresponding control signal.

Optionally, the first DAC module is respectively connected to a normal-phase input voltage, a reference ground and a common-mode voltage in an ADC sampling stage and a conversion stage, and in the sampling stage, the normal-phase input voltage is sampled, and in the conversion stage, charge redistribution is performed based on the magnitude of the sampled voltage, the reference voltage and the reference ground connection; the second DAC is respectively connected with a negative phase input voltage, a reference ground and a common mode voltage in an ADC sampling stage and a conversion stage, the negative phase input voltage is sampled in the sampling stage, and charge redistribution is carried out based on the size of the sampling voltage, the reference voltage and a reference ground connection mode in the conversion stage.

Optionally, the first DAC module and the second DAC module are of a capacitive type or a combined capacitive and resistive type.

More optionally, the first DAC module and the second DAC module are of a capacitive structure, and include a high-order weight section, a medium-order weight section, and a low-order weight section, the high-order weight section is connected to the medium-order weight section through a first coupling capacitor, the medium-order weight section is connected to the low-order weight section through a second coupling capacitor, an output terminal of the high-order weight section is connected to the common-mode voltage through a switch, and an output terminal of the low-order weight section is grounded through a capacitor; the weight of the first DAC module is sequentially decreased from high to low by an equal ratio coefficient of 0.5;

each weight section comprises at least one capacitor, an upper polar plate of each capacitor is used as an output end of the corresponding weight section, and a lower polar plate is connected with the corresponding input voltage, the reference voltage and the reference ground through three switches.

More optionally, parameters of corresponding devices in the first DAC module and the second DAC module are the same.

As described above, the successive approximation type analog-to-digital converter according to the present invention has the following advantageous effects:

the successive approximation type analog-to-digital converter provided by the invention works in different weight bit comparison stages through the two comparators respectively, so that the requirement on the precision of the comparators is reduced, meanwhile, the power consumption is not increased, the problem of designing the high-speed high-precision comparator which is difficult to solve in the design of the high-speed high-precision successive approximation type analog-to-digital converter is solved in a simple mode, and the successive approximation type analog-to-digital converter has great application value in the actual engineering design.

Drawings

Fig. 1 is a schematic diagram of a successive approximation type analog-to-digital converter according to the present invention.

FIG. 2 is a schematic diagram of a 4-bit successive approximation type analog-to-digital converter according to the present invention.

FIG. 3 is a schematic diagram of an alternative successive approximation analog-to-digital converter according to the present invention.

FIG. 4 is a schematic diagram of the 4-bit successive approximation analog-to-digital converter of the present invention converting the weight B3.

FIG. 5 is a schematic diagram of the 4-bit successive approximation analog-to-digital converter of the present invention converting the weight B2.

FIG. 6 is a schematic diagram of the 4-bit successive approximation analog-to-digital converter of the present invention converting the weight B1.

FIG. 7 is a schematic diagram of the 4-bit successive approximation analog-to-digital converter of the present invention converting the weight B0.

Description of the element reference numerals

1-successive approximation type analog-to-digital converter; 11-a first DAC module; 111-high weight segment; 112-median weight segment; 113-lower weight segment; 12-a second DAC module; 13-a first comparison module; 14-a second comparison module; 15-SAR logic module.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1-2. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

As shown in fig. 1, the present invention provides a successive approximation type analog-to-digital converter 1, where the successive approximation type analog-to-digital converter 1 includes:

a first DAC module 11, a second DAC module 12, a first comparison module 13, a second comparison module 14, and a SAR logic module 15.

As shown in fig. 1, the first DAC module 11 is connected to the first comparison module 13 and the second comparison module 14, and provides a positive-phase input signal for the first comparison module 13 and the second comparison module 14.

Specifically, the first DAC module 11 is connected to the non-inverting input voltage VIP, the reference voltage VREF, the ground reference GND and the common-mode voltage VCM during the ADC sampling phase and the conversion phase, respectively. In a sampling phase, the first DAC module 11 samples the non-inverting input voltage VIP; in the conversion phase, the first DAC module 11 performs charge redistribution based on the sampling voltage level, the reference voltage VREF, and the reference ground connection.

Specifically, as shown in fig. 1, the first DAC module 11 is divided into three segments, and the weights are sequentially decreased from high to low. The first DAC module 11 includes, but is not limited to, a capacitive type or a capacitive-resistive type, and the weight of the first DAC module is sequentially decreased from high to low by an equal coefficient of 0.5. In this embodiment, the first DAC module 11 adopts a capacitive structure, and the first DAC module 11 includes a high-order weight section 111, a middle-order weight section 112, and a low-order weight section 113. The output end of the high-order weight section 111 is connected with the common-mode power through a switchAnd (3) pressing the VCM. The DAC with the high-order weight section 111 of H bit comprises H capacitors, wherein the value of the ith capacitor is defined as 2^i-1Cu, i is a natural number not greater than H (excluding 0); the upper plates of the capacitors are connected together to form a first node A, and the lower plates are respectively connected with the positive phase input voltage VIP, the reference voltage VREF and the ground GND through a switch. The middle weight section 112 is a DAC of M bits, and includes M capacitors, wherein the value of the jth capacitor is defined as 2^j-1Cu, j is a natural number not greater than M (excluding 0); the upper plates of the capacitors are connected together to form a second node B, and the lower plates are respectively connected with the positive phase input voltage VIP, the reference voltage VREF and the ground GND through a switch. The output end (upper plate of each capacitor) of the high-order weight segment 111 and the output end (upper plate of each capacitor) of the medium-order weight segment 112 are connected through a first coupling capacitor Ca 1. The low-order weight section 113 is a DAC of L bit, and comprises L capacitors, wherein the value of the kth capacitor is defined as 2^k- ¹Cu, k is a natural number not greater than L (excluding 0); the upper electrode plates of the capacitors are connected together to form a third node C, and the lower electrode plates are respectively connected with the positive phase input voltage VIP, the reference voltage VREF and the reference ground GND through a switch. The output end (upper plate of each capacitor) of the middle weight section 112 and the output end of the low weight section 113 are connected through a second coupling capacitor Ca 2. The output terminal (the upper plate of each capacitor) of the low weight segment 113 is grounded via a capacitor (with a capacitance of Cu). The values of the capacitors in the same weight section are sequentially in a 2-time relationship, the value of the capacitor with the smallest weight in each weight section (in this embodiment, the smallest capacitance value is Cu) is equal, and the voltage jump value of the first node a is reduced by an equal coefficient of 0.5 in the process of sequentially converting the weight from high to low.

It should be noted that the invention adopts a three-stage capacitive architecture to realize the design of an N-bit ADC, where the high-order weight section 111 realizes H bit, the middle-order weight section 112 realizes M bit, and the low-order weight section 113 realizes L bit, and the total is N = H + M + L-bit DAC.

As an example, as shown in fig. 2, taking a 4-bit DAC module as an example, the high-order weight section 111 implements 2 bits, the medium-order weight section 112 implements 1 bit, and the low-order weight section 113 implements 1 bit, so that a total of 4-bit DACs is obtained. The high-order weight section 111 comprises two capacitors, wherein the values of the capacitors are 2Cu and Cu respectively; the middle weight section 112 comprises a capacitor with the value of Cu, and the lower weight section 113 comprises a capacitor with the value of Cu; the values of the first coupling capacitor Ca1 and the second coupling capacitor Ca2 are both 2 Cu. The capacitance values of the high-order weight segment 111, the medium-order weight segment 112 and the low-order weight segment 113, and the capacitance values of the first coupling capacitor Ca1 and the second coupling capacitor Ca2 are calculated according to the requirement that the weight of the first DAC module 11 is reduced from high to low by a factor of 0.5, which is not limited in this embodiment.

As shown in fig. 1, the second DAC module 12 is connected to the first comparing module 13 and the second comparing module 14, and provides inverted input signals for the first comparing module 13 and the second comparing module 14.

Specifically, the second DAC module 12 connects the inverting input voltage VIN, the reference voltage VREF, the ground GND, and the common-mode voltage VCM. In the sampling phase, the second DAC module 12 samples the inverted input voltage VIN and the common-mode voltage VCM; during the successive comparison phase, the second DAC module 12 redistributes charge to the output based on the reference voltage VREF.

Specifically, the second DAC module 12 and the first DAC module 11 have the same structure and corresponding device parameters, but the difference is that the non-inverting input voltage VIP received by the first DAC module 11 is replaced by the corresponding inverting input voltage VIN (differential structure, with opposite polarity), and the specific structure is not repeated herein.

As shown in fig. 1, the input terminal of the first comparator 13 is connected to the output terminal of the high weight segment of the first DAC module 11 and the second DAC module 12, respectively, and the first comparator 13 operates in the comparison phase of the high weight segment.

Specifically, in this embodiment, the non-inverting input terminal of the first comparator 13 is connected to the first node a of the first DAC module 11, and the inverting input terminal of the first comparator 13 is connected to the first node a of the second DAC module 12, and outputs the comparison result. In practical use, the correspondence relationship between the polarity of the input terminal of the first comparator 13 and the input signal is interchangeable, and is not limited to this embodiment.

Specifically, in the present embodiment, the first comparator 13 operates in the comparison stage of the high-order weight segment 111 and the medium-order weight segment 112.

As shown in fig. 1, the input terminal of the second comparator 14 is connected to the output terminal of the low-weight segment of the first DAC module 11 and the second DAC module 12, respectively, and the second comparator 14 operates in the comparison phase of the low-weight segment.

Specifically, in this embodiment, the non-inverting input terminal of the second comparator 14 is connected to the third node C of the first DAC module 11, and the inverting input terminal of the second comparator 14 is connected to the third node C of the second DAC module 12, and outputs the comparison result. In practical use, the correspondence relationship between the polarity of the input terminal of the second comparator 14 and the input signal is interchangeable, and is not limited to this embodiment.

Specifically, in the present embodiment, the second comparator 14 operates in the comparison stage of the low weight section 113.

As shown in fig. 1, the SAR logic module 15 is connected to the output ends of the first comparing module 13 and the second comparing module 14, and outputs a digital signal based on the comparison result output by the first comparing module 13 and the second comparing module 14 and generates a corresponding control signal.

Specifically, the SAR logic module 15 generates control signals for each switch for sampling and successive comparison control. After each comparison, the switching state is adjusted according to the comparison result output by the first comparing module 13 and the second comparing module 14 to gradually approximate the input voltage, and the corresponding digital signal is output.

As shown in fig. 3, the successive approximation type analog-to-digital converter includes a first DAC module 11, a second DAC module 12, a first comparison module 13 and a SAR logic module (not shown). The positive phase input voltage VIP and the negative phase input voltage VIN are sampled to the lower electrode plate of each capacitor in the capacitor array, and the upper electrode plate of each capacitor is connected to the common mode voltage VCM; then, the ADC starts conversion, at which time the upper plate of each capacitor in the capacitor array is disconnected from the common-mode voltage VCM, and is connected to the input end of the first comparing module 13, that is, the first nodes a of the first DAC module 11 and the second DAC module 12 are respectively connected to the non-inverting input end and the inverting input end of the first comparing module 13, and the conversion is gradually performed from the high-order weight section 111 to the medium-order weight section 112 and then to the last low-order weight section 113. As shown in fig. 4 to 7, in the process of gradually converting from the high weight to the low weight (B3, B2, B1, B0 in sequence), the voltage value Vo input to the first comparing module 13 gradually approaches from 1/2 VREF, 1/4 VREF, 1/8 VREF, 1/16 VREF (fig. 4 to 7 only illustrate the voltage at the positive input end of the first comparing module 13, and the voltage at the negative input end is in a differential relationship with the positive input end, which is not described herein), so the differential voltage at the first node a gradually decreases, the differential voltage at the first node a is larger in the converting phase of the high weight segment 111, and the differential voltage at the first node a is smaller in the converting phase of the low weight segment 113, which means that the voltage at the input end of the first comparing module 13 is smaller in the converting process, and reaches a minimum (1/16 × VREF) during the transition phase of the low weight segment 113, which requires the first comparison module 13 to recognize this smaller signal in a shorter time, i.e. the accuracy requirement of the first comparison module 13 is very high during this phase, especially the lowest weight bit (LSB) of the low weight segment 113 reaches the highest. In addition, the first comparison module 13 can correct the comparison stages of the middle weight section 112 and the lower weight section 113 step by step if a comparison error occurs in the comparison stage of the upper weight section 111, and can correct the comparison stage of the middle weight section 112 in the comparison stage of the lower weight section 113 if an error occurs, but no lower bits are corrected once an error occurs in the comparison stage of the lower weight section 113. Therefore, the first comparing module 13 needs to be able to identify the corresponding small signal at the time of the lowest weight bit transition of the low weight segment 113, which means that the first comparing module 13 needs to meet the requirement of high precision.

Based on the above analysis, the differential input voltage of the first comparing module 13 (i.e. the differential voltage of the first node a) is gradually decreased during the conversion process, and the requirement for the resolving capability of the first comparing module 13 is stronger and stronger, rather than the requirement for high accuracy all the time. Therefore, in the design of the high-speed high-precision successive approximation type analog-to-digital converter, a high-speed high-precision comparator is the key, the high speed of the comparator is required in each conversion stage of the ADC (the compression consumes time to improve the overall speed), but the high precision is not always required.

As shown in fig. 1, the present invention provides two comparison modules, namely a first comparison module 13 and a second comparison module 14, wherein an input end of the first comparison module 13 is connected to the first nodes a of the first DAC module 11 and the second DAC module 12, respectively, and an input end of the second comparison module 14 is connected to the third nodes C of the first DAC module 11 and the second DAC module 12, respectively. During the conversion process, in the comparison stage of the high-order weight segment 111 and the medium-order weight segment 112, the first comparison module 13 is used (working), the second comparison module 14 is turned off (not working), and since the differential voltage value corresponding to the first node a at this time is not very small (in fig. 4 to 7, the single-end minimum voltage is 1/8 × VREF), and the correction in the comparison stage of the low-order weight segment 113 is performed, the precision requirement of the first comparison module 13 is not very high; in the comparison stage of the low-order-weight segment 113, the first comparison module 13 is turned off (not operating), and the second comparison module 14 is turned on (operating), considering that the differential value of the first node a is small at this stage, the second comparison module 14 does not compare the differential value of the first node a, but compares the differential value of the third node C, in fig. 4 to 7, at this time, the voltage value of the single end of the first node a is 1/16 VREF, the differential value of the third node C is not attenuated by the capacitor in series, the voltage value of the single end is (21/64) VREF, which is more than 4 times larger than that of the first node a, and the voltage of the third node C is used as the input of the second comparison module 14, which is more efficient, and greatly reduces the requirement for the accuracy of the second comparison module 14. The design of the two comparison modules has low requirement on precision, the two comparison modules cannot be used simultaneously, the power consumption cannot be increased, the problem of high precision of the comparison modules in the design of the high-speed high-precision successive approximation type analog-to-digital converter is solved to a great extent, in addition, the precision of the comparison modules is relieved to a certain extent, the gain of the comparison modules can be properly reduced, the bandwidth of the comparison modules is easier to be increased, and the problem of high speed of the comparison modules is solved easily.

In summary, the present invention provides a successive approximation type analog-to-digital converter, including: the SAR analog-to-digital conversion circuit comprises a first DAC module, a second DAC module, a first comparison module, a second comparison module and an SAR logic module; the first DAC module is divided into three sections, and the weight is gradually decreased from high to low; the second DAC module has the same structure as the first DAC module; the input end of the first comparator is respectively connected with the high-order weight sections of the first DAC module and the second DAC module, and the input end of the second comparator is respectively connected with the low-order weight sections of the first DAC module and the second DAC module; the first comparator works in the comparison stage of the high-order weight section and the middle-order weight section, and the second comparator works in the comparison stage of the low-order weight section; the SAR logic module is connected with the output ends of the first comparison module and the second comparison module, outputs a digital signal based on the comparison result output by the first comparison module and the second comparison module and generates a corresponding control signal. The successive approximation type analog-to-digital converter provided by the invention works in different weight bit comparison stages through the two comparators respectively, so that the requirement on the precision of the comparators is reduced, meanwhile, the power consumption is not increased, the problem of designing the high-speed high-precision comparator which is difficult to solve in the design of the high-speed high-precision successive approximation type analog-to-digital converter is solved in a simple mode, and the successive approximation type analog-to-digital converter has great application value in the actual engineering design. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A successive approximation analog-to-digital converter, comprising:

the input end of the first comparison module is respectively connected with the high-order weight sections of the first DAC module and the second DAC module, and the input end of the second comparison module is respectively connected with the low-order weight sections of the first DAC module and the second DAC module; the first comparison module works in a comparison stage of a high-order weight section and a medium-order weight section, and the second comparison module works in a comparison stage of a low-order weight section;

2. The successive approximation analog-to-digital converter of claim 1, wherein: the first DAC module is respectively connected with a normal-phase input voltage, a reference ground and a common-mode voltage in an ADC sampling stage and a conversion stage, the normal-phase input voltage is sampled in the sampling stage, and charge redistribution is carried out based on the size of the sampling voltage, the reference voltage and a reference ground connection mode in the conversion stage; the second DAC is respectively connected with a negative phase input voltage, a reference ground and a common mode voltage in an ADC sampling stage and a conversion stage, the negative phase input voltage is sampled in the sampling stage, and charge redistribution is carried out based on the size of the sampling voltage, the reference voltage and a reference ground connection mode in the conversion stage.

3. The successive approximation analog-to-digital converter of claim 2, wherein: the first DAC module and the second DAC module are of a capacitance type or a capacitance resistance combination type.

4. A successive approximation analog to digital converter according to claim 3, characterized in that: the first DAC module is of a capacitive structure and comprises a high-order weight section, a middle-order weight section and a low-order weight section, the high-order weight section is connected with the middle-order weight section through a first coupling capacitor, the middle-order weight section is connected with the low-order weight section through a second coupling capacitor, the output end of the high-order weight section is connected with the common-mode voltage through a switch, and the output end of the low-order weight section is grounded through a capacitor; the weight of the first DAC module is sequentially decreased from high to low by an equal ratio coefficient of 0.5;

5. The successive approximation analog-to-digital converter of claim 4, wherein: and the parameters of corresponding devices in the first DAC module and the second DAC module are the same.