Nothing Special   »   [go: up one dir, main page]

CN107644876B - 台阶结构及其形成方法 - Google Patents

台阶结构及其形成方法 Download PDF

Info

Publication number
CN107644876B
CN107644876B CN201710750398.4A CN201710750398A CN107644876B CN 107644876 B CN107644876 B CN 107644876B CN 201710750398 A CN201710750398 A CN 201710750398A CN 107644876 B CN107644876 B CN 107644876B
Authority
CN
China
Prior art keywords
layer
mask
coating
forms
mask layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710750398.4A
Other languages
English (en)
Other versions
CN107644876A (zh
Inventor
吕震宇
陈俊
戴晓望
朱继锋
陶谦
黄郁茹
胡思平
姚兰
肖莉红
郑阿曼
鲍琨
杨号号
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yangtze Memory Technologies Co Ltd
Original Assignee
Yangtze Memory Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yangtze Memory Technologies Co Ltd filed Critical Yangtze Memory Technologies Co Ltd
Priority to CN201710750398.4A priority Critical patent/CN107644876B/zh
Publication of CN107644876A publication Critical patent/CN107644876A/zh
Priority to PCT/CN2018/098962 priority patent/WO2019042091A1/en
Priority to CN202110745130.8A priority patent/CN113241350B/zh
Priority to CN201880005628.7A priority patent/CN110121777A/zh
Priority to TW107127920A priority patent/TWI721303B/zh
Priority to US16/126,956 priority patent/US10680003B2/en
Application granted granted Critical
Publication of CN107644876B publication Critical patent/CN107644876B/zh
Priority to US16/885,858 priority patent/US11145666B2/en
Priority to US17/447,456 priority patent/US12010838B2/en
Priority to US18/054,468 priority patent/US12137558B2/en
Priority to US18/907,135 priority patent/US20250031366A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

本发明公开了一种台阶结构及其形成方法，属于半导体技术领域。所述方法包括：提供衬底，在衬底上形成叠层结构，在叠层结构上形成第一掩膜层；刻蚀第一掩膜层和叠层结构形成各台阶层；在各台阶层上形成着陆垫；去除剩余的第一掩膜层，并形成覆盖各台阶层的覆盖层。本发明中，通过在各台阶层上形成着陆垫，增加了台阶层之间互联部分的厚度，使得即使是很薄的字线需求，通过单张掩膜来形成台阶间的互连亦是可行的。

Description

台阶结构及其形成方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种台阶结构及其形成方法。
背景技术
闪存是一种非易变性的存储器，是电可擦除且可编程的只读存储器的一种特殊结构，其运作原理是通过改变晶体管或存储单元的临界电压来控制门极通道的开关以达到存储数据的目的，使存储在存储器中的数据不会因电源中断而消失。闪存以其便捷、存储密度高、可靠性好等优点成为非挥发性存储器研究的热点。从二十世纪八十年代第一个闪存产品问世以来，随着技术的发展和各类电子产品对存储的需求，闪存被广泛的应用于手机、笔记本、掌上电脑和U盘等移动和通讯设备中，并占据了非挥发性半导体存储器的大部分市场份额。
如今，经历了平面型闪存存储器的发展时期，已进入了三维闪存存储器的发展热潮，其主要特色是将平面结构转换为立体结构，通过光刻工艺形成台阶结构，在台阶结构中形成多个横向和纵向的存储单元阵列，并通过在台阶结构中形成水平方向上的字线(Wordline)和竖直方向的位线(Bit line)来准确定位各存储区，进而对存储区中的数据进行操作。目前的三维存储器，其台阶结构中字线的厚度是均匀的，然而，随着人们对存储器的容量及体积的要求不断提升，使形成台阶结构的堆栈会不断减小，从而字线的厚度会越来越小，进而导致用单个掩膜来创建台阶间的互连会越来越困难。
发明内容
为解决现有技术的不足，本发明提供一种台阶结构及其形成方法。
一方面，本发明提供一种台阶结构的形成方法，包括：
提供衬底，在所述衬底上形成叠层结构，在所述叠层结构上形成第一掩膜层；
刻蚀所述第一掩膜层和所述叠层结构形成各台阶层；
在各台阶层上形成着陆垫；
去除剩余的第一掩膜层，并形成覆盖各台阶层的覆盖层。
可选地，所述刻蚀所述第一掩膜层和所述叠层结构形成各台阶层，具体为：在所述第一掩膜层上旋涂光阻层，以所述光阻层为掩膜，多次刻蚀所述第一掩膜层和所述叠层结构形成各台阶层。
可选地，所述叠层结构，具体为多个层叠的氮氧层组，所述氮氧层组自上至下依次为氧化物层和氮化物层；
刻蚀所述第一掩膜层和所述叠层结构形成的各台阶层分别对应一个所述氮氧层组。
可选地，所述在各台阶层上形成着陆垫，具体包括：
在除最底层台阶层外的其他台阶层中，去除部分氮化物层，使氮化物层相对于氧化物层凹陷，形成第一凹陷结构；
形成第二掩膜层，所述第二掩膜层覆盖各台阶层及剩余的第一掩膜层，并将所述第一凹陷结构完全填充；
去除第二掩膜层，并在所述第一凹陷结构中形成填充结构，所述填充结构高于所述第一凹陷结构并覆盖部分对应的氧化物层的侧面；
去除各台阶层中的氧化物层，呈现各台阶层中的氮化物层；
形成加固层，所述加固层覆盖各台阶层中的氮化物层、填充结构及剩余的第一掩膜层；
去除部分加固层、所述填充结构和部分剩余的第一掩膜层，形成各台阶层的着陆垫，使除最底层台阶层外的各台阶层的氮化物层相对于对应的着陆垫凹陷，形成第二凹陷结构。
可选地，所述去除剩余的第一掩膜层，并形成覆盖各台阶层的覆盖层，具体为：去除当前剩余的第一掩膜层及其上的加固层和其下的氧化物层，并形成覆盖层，所述覆盖层将所述第二凹陷结构完全填充，并覆盖各台阶层。
另一方面，本发明提供一种台阶结构，包括：
衬底及衬底上的叠层结构；
形成于所述叠层结构上的各台阶层；
形成于各台阶层上的着陆垫；
覆盖各台阶层的覆盖层。
可选地，所述叠层结构，具体为多个层叠的氮氧层组，所述氮氧层组自上至下依次为氧化物层和氮化物层。
可选地，各台阶层分别对应一个氮氧层组，各台阶层的氮化物层相对于对应的着陆垫凹陷，形成第二凹陷结构。
可选地，所述覆盖层将所述第二凹陷结构完全填充，并覆盖各台阶层。
本发明的优点在于：
本发明中，通过在各台阶层上形成着陆垫，增加了台阶层之间互联部分的厚度，使得即使是很薄的字线需求，通过单张掩膜来形成台阶间的互连亦是可行的。
附图说明
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的，而并不认为是对本发明的限制。而且在整个附图中，用相同的参考符号表示相同的部件。在附图中：
附图1为本发明提供的一种形成台阶结构的方法流程图；
附图2和附图3为本发明提供的形成台阶层的结构变化示意图；
附图4至附图9为本发明提供的形成着陆垫的结构变化示意图；
附图10为本发明提供的部分台阶结构示意图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
实施例一
根据本发明的实施方式，提供一种台阶结构的形成方法，如图1所示，包括：
提供衬底，在衬底上形成叠层结构，在叠层结构上形成第一掩膜层；
刻蚀第一掩膜层和叠层结构形成各台阶层；
在各台阶层上形成着陆垫(Landing Pad)；
去除剩余的第一掩膜层，并形成覆盖各台阶层的覆盖层。
根据本发明的实施方式，刻蚀第一掩膜层和叠层结构形成各台阶层，具体为：在第一掩膜层上旋涂光阻层，以光阻层为掩膜，多次刻蚀第一掩膜层和叠层结构形成各台阶层。
根据本发明的实施方式，如图2和图3所示，叠层结构，具体为多个层叠的氮氧层组，氮氧层组自上至下依次为氧化物层(图中未示出)和氮化物层(图中未示出)；
对应地，刻蚀第一掩膜层和叠层结构形成的各台阶层分别对应一个氮氧层组。
需要说明地，在本实施例中，对叠层结构的氮氧层组的数量及形成的台阶层的数量不作具体限定，具体依需求而定，附图仅用于示例说明。
根据本发明的实施方式，在各台阶层上形成着陆垫，如图4至图9所示，具体包括：
在除最底层台阶层外的其他台阶层中，去除部分氮化物层，使氮化物层相对于氧化物层凹陷，形成第一凹陷结构(Nitride Recess)；
形成第二掩膜层，第二掩膜层覆盖各台阶层及剩余的第一掩膜层，并将第一凹陷结构完全填充(Poly Dep)；
去除第二掩膜层，并在第一凹陷结构中形成填充结构，填充结构高于第一凹陷结构并覆盖部分对应的氧化物层的侧面(Poly Etch)；
去除各台阶层中的氧化物层，呈现各台阶层中的氮化物层(Oxide Etch)；
形成加固层，加固层覆盖各台阶层中的氮化物层、填充结构及剩余的第一掩膜层(Niteide Dep)；
去除部分加固层、填充结构和部分剩余的第一掩膜层，形成各台阶层的着陆垫，使除最底层台阶层外的各台阶层的氮化物层相对于对应的着陆垫凹陷，形成第二凹陷结构(Nitride/Poly Recess)。
其中，第二掩膜层具体为多晶硅，加固层具体为氮化物。
根据本发明的实施方式，采用低压化学气相沉积(Low Pressure Chemical VaporDeposition，简称LPCVD)的方法和/或等离子体增强化学气相沉积(Plasma EnhancedChemical Vapor Deposition，简称PECVD)的方法形成第二掩膜层；
根据本发明的实施方式，采用干法刻蚀(Dry Etch)工艺去除第二掩膜层，并在第一凹陷结构中形成填充结构；
根据本发明的实施方式，采用不良梯形覆盖共形工艺(Poor Step CoverageConformal Process)形成加固层。
进一步地，在本实施例中，去除剩余的第一掩膜层，并形成覆盖各台阶层的覆盖层，具体为：去除当前剩余的第一掩膜层及其上的加固层和其下的氧化物层，并形成覆盖层，覆盖层将第二凹陷结构完全填充，并覆盖各台阶层。
实施例二
根据本发明的实施方式，提供一种台阶结构，包括：
衬底及衬底上的叠层结构；
形成于叠层结构上的各台阶层；
形成于各台阶层上的着陆垫；
覆盖各台阶层的覆盖层。
根据本发明的实施方式，叠层结构，具体为多个层叠的氮氧层组，氮氧层组自上至下依次为氧化物层和氮化物层。
根据本发明的实施方式，各台阶层分别对应一个氮氧层组，各台阶层的氮化物层相对于对应的着陆垫凹陷，形成第二凹陷结构。
根据本发明的实施方式，覆盖层将第二凹陷结构完全填充，，并覆盖各台阶层。
本发明中，通过在各台阶层上形成着陆垫，增加了台阶层之间互联部分的厚度，使得即使是很薄的字线需求，通过单张掩膜来形成台阶间的互连亦是可行的。
以上所述，仅为本发明较佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (3)

1.一种台阶结构的形成方法，其特征在于，包括：
提供衬底，在所述衬底上形成含有多个氮氧层组的叠层结构，所述氮氧层组自上至下依次为氧化物层和氮化物层；
在所述叠层结构上形成第一掩膜层；
刻蚀所述第一掩膜层和所述叠层结构形成各台阶层；
在除最底层台阶层外的其他台阶层中，去除部分氮化物层，使氮化物层相对于氧化物层凹陷，形成第一凹陷结构；
形成第二掩膜层，所述第二掩膜层覆盖各台阶层及剩余的第一掩膜层，并将所述第一凹陷结构完全填充；
去除第二掩膜层，并在所述第一凹陷结构中形成填充结构，所述填充结构高于所述第一凹陷结构并覆盖部分对应的氧化物层的侧面；
去除各台阶层中的氧化物层，呈现各台阶层中的氮化物层；
形成加固层，所述加固层覆盖各台阶层中的氮化物层、填充结构及剩余的第一掩膜层；
去除部分加固层、所述填充结构和部分剩余的第一掩膜层，形成各台阶层的着陆垫，使除最底层台阶层外的各台阶层的氮化物层相对于对应的着陆垫凹陷，形成第二凹陷结构；
去除剩余的第一掩膜层，并形成覆盖各台阶层的覆盖层。
2.根据权利要求1所述的方法，其特征在于，所述刻蚀所述第一掩膜层和所述叠层结构形成各台阶层，具体为：在所述第一掩膜层上旋涂光阻层，以所述光阻层为掩膜，多次刻蚀所述第一掩膜层和所述叠层结构形成各台阶层。
3.根据权利要求1所述的方法，其特征在于，所述去除剩余的第一掩膜层，并形成覆盖各台阶层的覆盖层，具体为：去除当前剩余的第一掩膜层及其上的加固层和其下的氧化物层，并形成覆盖层，所述覆盖层将所述第二凹陷结构完全填充，并覆盖各台阶层。
CN201710750398.4A 2017-08-28 2017-08-28 台阶结构及其形成方法 Active CN107644876B (zh)

Priority Applications (10)

Application Number Priority Date Filing Date Title
CN201710750398.4A CN107644876B (zh) 2017-08-28 2017-08-28 台阶结构及其形成方法
CN202110745130.8A CN113241350B (zh) 2017-08-28 2018-08-06 存储器装置的阶梯结构
PCT/CN2018/098962 WO2019042091A1 (en) 2017-08-28 2018-08-06 STAIR STRUCTURE FOR MEMORY DEVICE
CN201880005628.7A CN110121777A (zh) 2017-08-28 2018-08-06 存储器装置的阶梯结构
TW107127920A TWI721303B (zh) 2017-08-28 2018-08-10 記憶體裝置的階梯結構
US16/126,956 US10680003B2 (en) 2017-08-28 2018-09-10 Staircase structure for memory device
US16/885,858 US11145666B2 (en) 2017-08-28 2020-05-28 Staircase structure for memory device
US17/447,456 US12010838B2 (en) 2017-08-28 2021-09-13 Staircase structure for memory device
US18/054,468 US12137558B2 (en) 2017-08-28 2022-11-10 Staircase structure for memory device
US18/907,135 US20250031366A1 (en) 2017-08-28 2024-10-04 Staircase structure for memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710750398.4A CN107644876B (zh) 2017-08-28 2017-08-28 台阶结构及其形成方法

Publications (2)

Publication Number Publication Date
CN107644876A CN107644876A (zh) 2018-01-30
CN107644876B true CN107644876B (zh) 2019-01-01

Family

ID=61110794

Family Applications (3)

Application Number Title Priority Date Filing Date
CN201710750398.4A Active CN107644876B (zh) 2017-08-28 2017-08-28 台阶结构及其形成方法
CN202110745130.8A Active CN113241350B (zh) 2017-08-28 2018-08-06 存储器装置的阶梯结构
CN201880005628.7A Pending CN110121777A (zh) 2017-08-28 2018-08-06 存储器装置的阶梯结构

Family Applications After (2)

Application Number Title Priority Date Filing Date
CN202110745130.8A Active CN113241350B (zh) 2017-08-28 2018-08-06 存储器装置的阶梯结构
CN201880005628.7A Pending CN110121777A (zh) 2017-08-28 2018-08-06 存储器装置的阶梯结构

Country Status (4)

Country Link
US (5) US10680003B2 (zh)
CN (3) CN107644876B (zh)
TW (1) TWI721303B (zh)
WO (1) WO2019042091A1 (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107644876B (zh) 2017-08-28 2019-01-01 长江存储科技有限责任公司 台阶结构及其形成方法
CN108428703A (zh) * 2018-04-17 2018-08-21 长江存储科技有限责任公司 三维存储器及其制造方法
US10847523B1 (en) * 2019-07-03 2020-11-24 Macronix International Co., Ltd. Stacked memory and ASIC device
KR102697629B1 (ko) 2019-07-18 2024-08-26 삼성전자주식회사 게이트 영역 및 절연 영역을 갖는 적층 구조물을 포함하는 반도체 소자
JP2021039965A (ja) * 2019-08-30 2021-03-11 キオクシア株式会社 半導体記憶装置および半導体記憶装置の製造方法
KR20210051262A (ko) * 2019-10-30 2021-05-10 삼성전자주식회사 반도체 메모리 장치 및 반도체 메모리 장치 제조 방법
KR102689656B1 (ko) 2019-12-10 2024-07-30 삼성전자주식회사 반도체 소자
CN112673472B (zh) 2020-12-04 2022-07-15 长江存储科技有限责任公司 半导体器件及其制作方法
CN117769255A (zh) * 2021-01-13 2024-03-26 长江存储科技有限责任公司 用于在三维存储器件中形成台阶的方法
US11688688B2 (en) * 2021-03-16 2023-06-27 Macronix International Co., Ltd. Memory device including a landing pad with increased thickness of a conductive film in the landing area
CN113192966B (zh) * 2021-04-12 2022-05-20 长江存储科技有限责任公司 3d存储器件及其制造方法
US11721629B2 (en) 2021-07-21 2023-08-08 Micron Technology, Inc. Memory device including staircase structure having conductive pads
CN114207823A (zh) * 2021-10-30 2022-03-18 长江存储科技有限责任公司 具有阶梯结构的三维存储器器件及其形成方法
US20230187351A1 (en) * 2021-12-10 2023-06-15 Fujian Jinhua Integrated Circuit Co., Ltd. Three-dimensional memory device and method for forming the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110015338A (ko) * 2009-08-07 2011-02-15 주식회사 하이닉스반도체 수직채널형 비휘발성 메모리 소자 제조 방법
CN106601746A (zh) * 2015-10-08 2017-04-26 三星电子株式会社 半导体器件及其制造方法

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8012817B2 (en) * 2008-09-26 2011-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor performance improving method with metal gate
JP2011035237A (ja) * 2009-08-04 2011-02-17 Toshiba Corp 半導体装置の製造方法及び半導体装置
KR101843580B1 (ko) * 2011-08-16 2018-03-30 에스케이하이닉스 주식회사 3차원 구조의 비휘발성 메모리 소자 및 그 제조 방법
JP2013055136A (ja) * 2011-09-01 2013-03-21 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
KR101884002B1 (ko) * 2012-04-13 2018-08-01 삼성전자주식회사 콘택 구조물 형성 방법
KR101881857B1 (ko) * 2012-08-27 2018-08-24 삼성전자주식회사 계단형 패턴 형성 방법
KR20140089793A (ko) * 2013-01-07 2014-07-16 에스케이하이닉스 주식회사 반도체 장치 및 그 제조 방법
US9165937B2 (en) * 2013-07-01 2015-10-20 Micron Technology, Inc. Semiconductor devices including stair step structures, and related methods
KR20150073251A (ko) * 2013-12-20 2015-07-01 에스케이하이닉스 주식회사 반도체 장치 및 그 제조 방법
KR102125018B1 (ko) * 2014-01-23 2020-07-07 에스케이하이닉스 주식회사 반도체 장치 및 그 제조방법
KR20150104817A (ko) * 2014-03-06 2015-09-16 에스케이하이닉스 주식회사 반도체 장치 및 그 제조 방법
KR102168189B1 (ko) * 2014-03-07 2020-10-21 삼성전자주식회사 3차원 반도체 장치 및 그 제조 방법
KR102134912B1 (ko) * 2014-03-21 2020-07-20 에스케이하이닉스 주식회사 반도체 장치 및 그 제조방법
KR102094470B1 (ko) * 2014-04-08 2020-03-27 삼성전자주식회사 반도체 소자 및 그 제조 방법
US9324728B2 (en) * 2014-07-07 2016-04-26 Macronix International Co., Ltd. Three-dimensional vertical gate NAND flash memory including dual-polarity source pads
KR102299673B1 (ko) * 2014-08-11 2021-09-10 삼성전자주식회사 반도체 패키지
CN105514018B (zh) * 2014-09-26 2019-02-26 中芯国际集成电路制造(北京)有限公司 制造半导体装置的方法
KR102307633B1 (ko) * 2014-12-10 2021-10-06 삼성전자주식회사 반도체 소자 및 그 제조 방법
JP2016174064A (ja) * 2015-03-17 2016-09-29 株式会社東芝 半導体装置および半導体装置の製造方法
KR20160143261A (ko) * 2015-06-05 2016-12-14 에스케이하이닉스 주식회사 비휘발성 메모리 소자 및 그의 제조 방법
US9406609B1 (en) * 2015-06-23 2016-08-02 Macronix International Co., Ltd. Opening structure and manufacturing method thereof and interconnection structure
US9520402B1 (en) * 2015-08-25 2016-12-13 Intel Corporation Provision of etch stop for wordlines in a memory device
KR102422087B1 (ko) * 2015-09-23 2022-07-18 삼성전자주식회사 수직형 메모리 장치 및 이의 제조 방법
US9837431B2 (en) * 2015-11-20 2017-12-05 Sandisk Technologies Llc 3D semicircular vertical NAND string with recessed inactive semiconductor channel sections
KR102497116B1 (ko) * 2015-12-30 2023-02-07 에스케이하이닉스 주식회사 전자 장치 및 그 제조 방법
US9911753B2 (en) * 2016-01-15 2018-03-06 Toshiba Memory Corporation Semiconductor device and method for manufacturing semiconductor device
US9741563B2 (en) * 2016-01-27 2017-08-22 Lam Research Corporation Hybrid stair-step etch
US10134672B2 (en) * 2016-03-15 2018-11-20 Toshiba Memory Corporation Semiconductor memory device having a stepped structure and contact wirings formed thereon
US9786681B1 (en) * 2016-04-01 2017-10-10 Sandisk Technologies Llc Multilevel memory stack structure employing stacks of a support pedestal structure and a support pillar structure
US10090320B2 (en) * 2016-05-19 2018-10-02 Toshiba Memory Corporation Semiconductor device and method for manufacturing the same
KR102675911B1 (ko) * 2016-08-16 2024-06-18 삼성전자주식회사 반도체 소자
US10134757B2 (en) * 2016-11-07 2018-11-20 Asm Ip Holding B.V. Method of processing a substrate and a device manufactured by using the method
KR20180068587A (ko) * 2016-12-14 2018-06-22 삼성전자주식회사 수직형 반도체 소자
US9941153B1 (en) * 2016-12-22 2018-04-10 Macronix International Co., Ltd. Pad structure and manufacturing method thereof
US11171050B2 (en) * 2017-03-09 2021-11-09 Tokyo Electron Limited Method for manufacturing a contact pad, method for manufacturing a semiconductor device using same, and semiconductor device
KR20180107905A (ko) * 2017-03-23 2018-10-04 에스케이하이닉스 주식회사 반도체 장치 및 그 제조 방법
JP2018170447A (ja) * 2017-03-30 2018-11-01 東芝メモリ株式会社 半導体装置及びその製造方法
US10847529B2 (en) * 2017-04-13 2020-11-24 Asm Ip Holding B.V. Substrate processing method and device manufactured by the same
KR102424875B1 (ko) * 2017-07-03 2022-07-26 삼성전자주식회사 반도체 소자
KR102421766B1 (ko) * 2017-07-07 2022-07-18 삼성전자주식회사 3차원 반도체 장치 및 그 제조 방법
CN107644876B (zh) 2017-08-28 2019-01-01 长江存储科技有限责任公司 台阶结构及其形成方法
US10608010B2 (en) * 2018-03-09 2020-03-31 Sandisk Technologies Llc Three-dimensional memory device containing replacement contact via structures and method of making the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110015338A (ko) * 2009-08-07 2011-02-15 주식회사 하이닉스반도체 수직채널형 비휘발성 메모리 소자 제조 방법
CN106601746A (zh) * 2015-10-08 2017-04-26 三星电子株式会社 半导体器件及其制造方法

Also Published As

Publication number Publication date
US20250031366A1 (en) 2025-01-23
US20230083030A1 (en) 2023-03-16
WO2019042091A1 (en) 2019-03-07
CN113241350B (zh) 2023-07-18
CN110121777A (zh) 2019-08-13
US20230084008A1 (en) 2023-03-16
US10680003B2 (en) 2020-06-09
US20190081070A1 (en) 2019-03-14
CN113241350A (zh) 2021-08-10
US12137558B2 (en) 2024-11-05
US20200295019A1 (en) 2020-09-17
TW201913972A (zh) 2019-04-01
TWI721303B (zh) 2021-03-11
US11145666B2 (en) 2021-10-12
CN107644876A (zh) 2018-01-30
US12010838B2 (en) 2024-06-11

Similar Documents

Publication Publication Date Title
CN107644876B (zh) 台阶结构及其形成方法
CN107482013B (zh) 三维存储器及其形成方法
US11456307B2 (en) Flash memory containing air gaps
US8760909B2 (en) Memory and manufacturing method thereof
US20150348986A1 (en) Non-volatile memory and method of forming the same
US20120098048A1 (en) Vertical memory devices and methods of manufacturing the same
TWI601270B (zh) 半導體結構及其形成方法
CN109887917B (zh) 电子设备、三维存储器及其制作方法
US7951670B2 (en) Flash memory cell with split gate structure and method for forming the same
CN108807401A (zh) 一种半导体器件及其制造方法
JP2019121778A (ja) 不揮発性メモリ構造およびその製造方法
CN106356374A (zh) 快闪存储器及其制作方法
KR20190012581A (ko) 집적도를 개선시킨 3차원 플래시 메모리 및 그 제조 방법
JP5667961B2 (ja) 半導体装置の製造方法
CN106328654A (zh) 半导体器件及其形成方法
CN210535667U (zh) 三维存储结构
CN107994031A (zh) 一种3d nand制造方法
CN107658313B (zh) 三维存储器中高深宽比的字线形成方法
CN103295968B (zh) 半导体器件的制备方法
CN107731835B (zh) 双台阶结构的三维存储器及其形成方法
CN105789213B (zh) 一种半导体存储器件及其制备方法、电子装置
TW200901449A (en) Flash memory structure and method of making the same
CN114050163A (zh) 一种拓扑绝缘体非易失性存储器件及其制备方法
CN107564913B (zh) 一种阶梯覆盖层的平坦化方法
CN106169478B (zh) 闪存存储器及其形成方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant