CN107425017A - A kind of array base palte, display panel and display device - Google Patents
A kind of array base palte, display panel and display device Download PDFInfo
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- CN107425017A CN107425017A CN201710707163.7A CN201710707163A CN107425017A CN 107425017 A CN107425017 A CN 107425017A CN 201710707163 A CN201710707163 A CN 201710707163A CN 107425017 A CN107425017 A CN 107425017A
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- 239000010410 layer Substances 0.000 claims abstract description 113
- 239000002184 metal Substances 0.000 claims abstract description 91
- 229910052751 metal Inorganic materials 0.000 claims abstract description 91
- 230000004888 barrier function Effects 0.000 claims abstract description 49
- 239000011241 protective layer Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000009413 insulation Methods 0.000 claims abstract description 16
- 239000000203 mixture Substances 0.000 claims description 9
- 230000005611 electricity Effects 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 238000003466 welding Methods 0.000 abstract description 6
- 238000000034 method Methods 0.000 description 18
- 238000000059 patterning Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000010949 copper Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical group O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 210000000707 wrist Anatomy 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Liquid Crystal (AREA)
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Abstract
The invention discloses a kind of array base palte, display panel and display device, including：Underlay substrate, the transistor positioned at the array base palte row driving GOA regions of underlay substrate；Transistor includes the first barrier metal layer, the first gate insulation layer, the first active layer, the first Source and drain metal level and the first protective layer, wherein, the first Source and drain metal level is used to form source electrode, drain electrode and data signal line；Wherein, source electrode is connected with data signal line by the first conductive component；First barrier metal layer corresponding to orthographic projection of first conductive component in the first barrier metal layer has pierced pattern.Once short circuit occurs for source electrode and the first barrier metal layer, can solve short circuit problem by removing the first conductive component, and because the first barrier metal layer corresponding to orthographic projection of first conductive component in the first barrier metal layer has pierced pattern, therefore the first Source and drain metal level and new poor short circuit caused by the first barrier metal layer welding will not be formed while the first conductive component is removed.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of array base palte, display panel and display device.
Background technology
With the rapid development of Display Technique, display panel presents the development trend of high integration and low cost.Its
In, GOA (Gate Driver on Array, array base palte row driving) technology by TFT (Thin Film Transistor, it is thin
Film transistor) gate switch circuit is integrated on the array base palte of display panel to be formed to the turntable driving of display panel, from
And binding (Bonding) region of grid integrated circuits (IC, Integrated Circuit) can be saved and be fanned out to (Fan-
Out) the wiring space in region, not only product cost can be reduced in material cost and the aspect of manufacture craft two, and can made
Display panel accomplishes that both sides are symmetrical and the design for aesthetic of narrow frame；Also, this integrated technique may be omitted with controlling grid scan line
The binding technique in direction, so as to improve production capacity and yield.
However, complicated using GOA product structure, circuit is intensive, and Source and drain metal level easily occurs short with gate metal layer
Road, cause GOA bad；For the product that particularly barrier metal layer and Source and drain metal level are made using copper (Cu), it is more likely formed
Grain (Particle), and then cause GOA unit that short circuit occurs.Due in barrier metal layer in existing GOA products and Source and drain metal level
Lower overlapping design, when being repaired using the bad point of laser cutting, easily cause barrier metal layer and Source and drain metal level welding shape
Cheng Xin poor short circuit, therefore once occur that GOA is bad, and prior art is difficult to repair, entire panel will scrap processing, cause
Great economic loss, for example, for current 8.5 generation line product, general GOA correlations unrepairable is bad left 0.5%
The right side, caused economic loss is at 5,000,000/million.
The content of the invention
In view of this, the embodiment of the present invention provides a kind of array base palte, display panel and display device, can improve GOA
Bad repairable rate, reduce economic loss.
Therefore, a kind of array base palte provided in an embodiment of the present invention, including：Underlay substrate, positioned at the underlay substrate
The transistor in array base palte row driving GOA regions；The transistor has including the first barrier metal layer, the first gate insulation layer, first
Active layer, the first Source and drain metal level and the first protective layer, wherein, first Source and drain metal level is used to form source electrode, drain electrode sum
According to signal wire；
The source electrode is connected with the data signal line by the first conductive component；
The first barrier metal layer tool corresponding to orthographic projection of first conductive component in first barrier metal layer
There is pierced pattern.
In a kind of possible implementation, in above-mentioned array base palte provided in an embodiment of the present invention, the source electrode, institute
Data signal line is stated to be structure as a whole with first conductive component.
In a kind of possible implementation, in above-mentioned array base palte provided in an embodiment of the present invention, in addition to：It is located at
The pixel electrode of the viewing area of the underlay substrate；And layer where the pixel electrode is located at first protective layer and deviates from institute
State underlay substrate side；
First conductive component is set with the pixel electrode with layer.
In a kind of possible implementation, in above-mentioned array base palte provided in an embodiment of the present invention, described first protects
Sheath has the first via corresponding with the source electrode, and the second via corresponding with the data signal line；
Part first conductive component is separately filled with first via and second via.
In a kind of possible implementation, in above-mentioned array base palte provided in an embodiment of the present invention, in addition to：It is located at
The GOA regions and the overlapping element of the electric capacity being connected with the transistor；The electric capacity, which overlaps element, to be included：With the first grid
The second barrier metal layer that metal level is set with layer, the second gate insulation layer set with first gate insulation layer with layer are and described
The second Source and drain metal level that first Source and drain metal level is set with layer, and the second protection set with first protective layer with layer
Layer；
Second Source and drain metal level is by multiple separate isolated island structure compositions.
In a kind of possible implementation, in above-mentioned array base palte provided in an embodiment of the present invention, each isolated island
Structure is connected by the second conductive component.
In a kind of possible implementation, in above-mentioned array base palte provided in an embodiment of the present invention, described second leads
Electric part is set with the pixel electrode with layer.
In a kind of possible implementation, in above-mentioned array base palte provided in an embodiment of the present invention, described second protects
Sheath has and each one-to-one 3rd via of isolated island structure；
Part second conductive component is separately filled with each 3rd via.
The embodiment of the present invention additionally provides a kind of display panel, including above-mentioned array base palte.
The embodiment of the present invention additionally provides a kind of display device, including above-mentioned display panel.
The present invention has the beneficial effect that：
Array base palte, display panel and display device provided in an embodiment of the present invention, including：Underlay substrate, positioned at substrate
The transistor in the array base palte row driving GOA regions of substrate；Transistor includes the first barrier metal layer, the first gate insulation layer, first
Active layer, the first Source and drain metal level and the first protective layer, wherein, the first Source and drain metal level is used to form source electrode, drain electrode and data
Signal wire；Wherein, source electrode is connected with data signal line by the first conductive component；First conductive component is in the first barrier metal layer
Orthographic projection corresponding to the first barrier metal layer there is pierced pattern.Once short circuit occurs for source electrode and the first barrier metal layer, pass through shifting
Except the first conductive component can solve short circuit problem, and the orthographic projection pair due to the first conductive component in the first barrier metal layer
The first barrier metal layer answered has pierced pattern, therefore will not form the first source and drain metal while the first conductive component is removed
Layer and new poor short circuit caused by the first barrier metal layer welding, so as to reduce economic loss to a certain extent.
Brief description of the drawings
Fig. 1 is the structural representation of array base palte provided in an embodiment of the present invention；
Fig. 2 is cross-sectional view of the array base palte along dotted line AA ' shown in Fig. 1；
Fig. 3 is cross-sectional view of the array base palte along dotted line BB ' shown in Fig. 1；
Fig. 4 is cross-sectional view of the array base palte along dotted line CC ' shown in Fig. 1.
Embodiment
Below in conjunction with the accompanying drawings, to the specific reality of array base palte provided in an embodiment of the present invention, display panel and display device
The mode of applying is described in detail.It should be noted that embodiment described herein is only part of the embodiment of the present invention,
Rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art are not making creative labor
The every other embodiment obtained under the premise of dynamic, belongs to the scope of protection of the invention.
The shapes and sizes of each film layer do not reflect the actual proportions of array base palte in accompanying drawing, and purpose is schematically illustrate hair
Bright content.
A kind of array base palte provided in an embodiment of the present invention, as shown in Figures 1 to 4, including：Underlay substrate 101, positioned at lining
The transistor in the array base palte row driving GOA regions of substrate 101；Transistor includes the first barrier metal layer 102, the first gate insulation
The 103, first active layer 104 of layer, the first Source and drain metal level and the first protective layer 106, wherein, the first Source and drain metal level is used to be formed
Source electrode 1051, drain electrode 1052 and data signal line 1053；
Source electrode 1051 is connected with data signal line 1053 by the first conductive component 107；
First barrier metal layer 102 corresponding to orthographic projection of first conductive component 107 in the first barrier metal layer 102, which has, engraves
Null pattern.
In above-mentioned array base palte provided in an embodiment of the present invention, once source electrode 1051 occurs with the first barrier metal layer 102
Short circuit, can solve short circuit problem by removing the first conductive component 107, reduce economic loss to a certain extent；And
Because first barrier metal layer 102 has hollow out figure corresponding to orthographic projection of first conductive component 107 in the first barrier metal layer 102
Case, therefore will not form the first Source and drain metal level and the welding of the first barrier metal layer 102 while the first conductive component 107 are removed
Caused new poor short circuit.
It should be noted that the transistor in GOA regions can be bottom-gate-type transistor, or top gate-type transistors,
Do not limit herein.It is below that transistor includes being successively set on substrate using the transistor in GOA regions as bottom-gate-type transistor
The first barrier metal layer 102, the first gate insulation layer 103, the first active layer 104, the first Source and drain metal level and first on substrate 101
Illustrated exemplified by protective layer 106.
Typically also, existing GOA regions have multiple transistors, and the source electrode of each transistor is interconnected on one
Rise；And the source electrode of each transistor in the GOA regions of above-mentioned array base palte provided in an embodiment of the present invention is separate.Further
Ground, when the grid of the first barrier metal layer 102 loads scanning gate signal, the first active layer 104 above grid can be from partly leading
Body state is changed into conductive state, and an electric current can be formed towards the surface of the side of the first gate insulation layer 103 in the first active layer 104
Passage, the current channel is relative with source electrode 1051 in embodiments of the present invention, i.e., source electrode 1051 can answer in the embodiment of the present invention
With the raceway groove for transistor.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, the realization of the first conductive component 107
Mode can have it is a variety of, such as depicted in figs. 1 and 2, the source electrode 1051, (figure of 1053 and first conductive component of data signal line 107
Rectangle dotted line frame in 1) it can be structure as a whole, i.e., source electrode 1051, data signal line are formed using the first Source and drain metal level
1053 and first conductive component 107.Because the first conductive component 107 formed using the first Source and drain metal level is in the first grid metal
First barrier metal layer 102 corresponding to orthographic projection on layer 102 has pierced pattern, that is to say, that the first conductive component 107 first
Orthographic projection region in barrier metal layer 102 does not have the pattern of the first barrier metal layer 102, when the grid metal of source electrode 1051 and first
Short circuit occurs for layer 102, and after there is bad point S1, source electrode 1051 and data signal line 1053 will be connected using modes such as laser cuttings
The cut-out of the first conductive component 107 can repair poor short circuit, and new GOA short circuits caused by levels welding will not be formed not
It is good.
For another example, the first conductive component 107 can also be realized in the following manner, specifically, in the embodiment of the present invention
In the above-mentioned array base palte provided, as shown in figure 3, also including：Pixel electrode (figure positioned at the viewing area of underlay substrate 101
Not shown in)；And layer where pixel electrode is located at the first protective layer 106 and deviates from the side of underlay substrate 101；
First conductive component 107 is set with pixel electrode with layer, in this way, can pass through a structure on array base palte
Figure technique forms pixel electrode and the first conductive component 107 simultaneously, without extra increase manufacture craft, reduces production
Cost.Also, usually, the material of pixel electrode is tin indium oxide (ITO), then the material of the first conductive component 107 can also
For ITO., will connection source electrode 1051 and data after producing bad point S2 when short circuit occurs for the barrier metal layer 102 of source electrode 1051 and first
The ITO of signal wire 1053, which is removed, can repair poor short circuit.
Further, in above-mentioned array base palte provided in an embodiment of the present invention, the first protective layer 106 has and source electrode
First via corresponding to 1051, and second via corresponding with data signal line 1053；
The first conductive component of part 107 is separately filled with first via and the second via.
Specifically, the first protective layer 106 is deposited in the first Source and drain metal level, is then formed on the first protective layer 106
While via (the Via Hole) of connection drain electrode 1052 and pixel electrode, formed and source electrode 1051 on the first protective layer 106
Corresponding first via, and second via corresponding with data signal line 1053, by both corresponding first vias or second
Cross the metal exposure of hole location；The patterning processes of pixel electrode pattern are then carried out on the first protective layer 106, so as to pass through
The ITO in region between the first via and ITO in the second via and the first via of covering and the second via is filled in, realizes source
Connection conducting between pole 1051 and data signal line 1053.
Certainly, in the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, the first conductive component 107
It can also be formed by additionally increasing single patterning processes, do not limited herein.
It should be noted that in above-mentioned array base palte provided in an embodiment of the present invention, the first conductive component 107 is in substrate
The shape of orthographic projection can be a variety of on substrate 101, such as rectangle, ellipse, triangle, square, rhombus, trapezoidal, just
Any regulars such as polygon or irregular figure, are not limited herein.
In the specific implementation, in above-mentioned array base palte provided in an embodiment of the present invention, as shown in Figure 1 and Figure 4, also wrap
Include：Element is overlapped positioned at GOA regions and the electric capacity that is connected with transistor；Electric capacity, which overlaps element, to be included：With the first barrier metal layer 102
The second barrier metal layer 108 set with layer, the second gate insulation layer 109 set with the first gate insulation layer 103 with layer, with the first source
The second Source and drain metal level that leakage metal level is set with layer, and the second protective layer 111 set with the first protective layer 106 with layer；
And formed simultaneously in practical application, electric capacity overlaps each film layer of each film layer of element typically with being set in transistor with layer；
Second Source and drain metal level can be made up of multiple separate isolated island structures 1101.
Specifically, to ensure the satisfactory electrical conductivity of the second Source and drain metal level, in above-mentioned array provided in an embodiment of the present invention
In substrate, each isolated island structure 1101 is connected by the second conductive component 112.
It is preferred that for not additional process flow, in above-mentioned array base palte provided in an embodiment of the present invention, second
Conductive component 112 can be set with pixel electrode with layer, in favor of forming the second conductive component simultaneously by a patterning processes
112 and pixel electrode.
Further, in above-mentioned array base palte provided in an embodiment of the present invention, the second protective layer 111 has and each isolated island
One-to-one 3rd via of structure 1101；The second conductive component of part 112 is separately filled with each 3rd via.I.e. first
While connection drain electrode 1052 and via (the Via Hole) of pixel electrode are formed on protective layer 106, on the second protective layer 111
The 3rd via corresponding with each isolated island structure 1101 is formed, each isolated island structure 1101 the corresponding 3rd is crossed to the metal of hole location
Exposure；The composition work of pixel electrode pattern is then carried out on the first protective layer 106 and the second protective layer 111 that same layer is set
Skill, so as to by the ITO in region between the 3rd via of the ITO being filled in each 3rd via and covering, realize each isolated island
Connection conducting between structure 1101, form the network structure of conducting.Occur in isolated island structure 1101 and the second barrier metal layer 108
Short circuit, when there is bad point S3, you can bad to repair GOA by the way that the ITO isolation of bad point S3 opening positions is got rid of.
Also, in the specific implementation, existing any number of composition flow can be used to make each film on underlay substrate 101
Layer, such as 6 patterning processes can be used：The gate insulation layer of first barrier metal layer and second gate metal layer → first and second
The active layer of gate insulation layer composition → first and the second active layer composition → data signal line, source electrode, drain electrode and the second source and drain metal
Layer composition → first protective layer and the second protective layer composition → pixel electrode layer, the first conductive component and the second conductive component structure
Figure；It can certainly not limited herein using the patterning processes of other numbers according to actual design.
It should be noted that in the patterning processes provided in an embodiment of the present invention for forming each Rotating fields and being related to, not only may be used
With including all or part of techniques such as deposition, photoresist coating, mask plate mask, exposure, development, etching, photoresist lift offs
Process, other technical process can also be included, specifically the figure by composition needed for formation during actual fabrication is defined, herein not
Limit.For example, dry technique with after can also including before etching after developing.
Wherein, depositing operation can be chemical vapour deposition technique, plasma enhanced chemical vapor deposition method or physics gas
Phase sedimentation, is not limited herein；Mask plate used can be intermediate tone mask plate (Half Tone in masking process
Mask), single slit diffraction mask plate (Single Slit Mask) or gray mask plate (GrayTone Mask), do not do herein
Limit；Etching can be dry etching or wet etching, not limit herein.
Based on same inventive concept, the embodiments of the invention provide a kind of display panel, including above-mentioned array base palte.Due to
The principle that the principle of display panel solution problem solves problem to above-mentioned array base palte is similar, and therefore, the embodiment of the present invention carries
The implementation of the display panel supplied may refer to the implementation of above-mentioned array base palte provided in an embodiment of the present invention, repeat part no longer
Repeat.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of display device, including the embodiment of the present invention carries
The above-mentioned display panel supplied, the display device can be：Mobile phone, tablet personal computer, television set, display, notebook computer, number
Any product or part with display function such as photo frame, navigator, intelligent watch, body building wrist strap, personal digital assistant.This is aobvious
The implementation of showing device may refer to the embodiment of above-mentioned display panel, repeats part and repeats no more.
Above-mentioned array base palte, display panel and display device provided in an embodiment of the present invention, including：Underlay substrate, it is located at
The transistor in the array base palte row driving GOA regions of underlay substrate；Transistor include the first barrier metal layer, the first gate insulation layer,
First active layer, the first Source and drain metal level and the first protective layer, wherein, the first Source and drain metal level be used for formed source electrode, drain electrode and
Data signal line；Wherein, source electrode is connected with data signal line by the first conductive component；First conductive component is in the first grid metal
The first barrier metal layer has pierced pattern corresponding to orthographic projection on layer.Once short circuit occurs for source electrode and the first barrier metal layer, lead to
Short circuit problem, and the positive throwing due to the first conductive component in the first barrier metal layer can be solved by crossing the first conductive component of removal
First barrier metal layer corresponding to shadow has pierced pattern, therefore will not form the first source and drain while the first conductive component is removed
New poor short circuit caused by metal level and the first barrier metal layer welding, so as to reduce economic loss to a certain extent.
It should be noted that herein, such as first and second etc relational terms are used merely to an entity
Or operation makes a distinction with another entity or operation, and not necessarily require or imply to exist between these entities or operation and appoint
What this actual relation or order.
Obviously, those skilled in the art can carry out the essence of various changes and modification without departing from the present invention to the present invention
God and scope.So, if these modifications and variations of the present invention belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising including these changes and modification.
Claims (10)
1. a kind of array base palte, including：Underlay substrate, the crystalline substance positioned at the array base palte row driving GOA regions of the underlay substrate
Body pipe；The transistor includes the first barrier metal layer, the first gate insulation layer, the first active layer, the first Source and drain metal level and first
Protective layer, wherein, first Source and drain metal level is used to form source electrode, drain electrode and data signal line；Characterized in that,
The source electrode is connected with the data signal line by the first conductive component；
First barrier metal layer corresponding to orthographic projection of first conductive component in first barrier metal layer, which has, engraves
Null pattern.
2. array base palte as claimed in claim 1, it is characterised in that the source electrode, the data signal line and described first
Conductive component is structure as a whole.
3. array base palte as claimed in claim 1, in addition to：Pixel electrode positioned at the viewing area of the underlay substrate；
And layer where the pixel electrode is located at first protective layer and deviates from the underlay substrate side；Characterized in that,
First conductive component is set with the pixel electrode with layer.
4. array base palte as claimed in claim 3, it is characterised in that first protective layer has corresponding with the source electrode
First via, and the second via corresponding with the data signal line；
Part first conductive component is separately filled with first via and second via.
5. array base palte as claimed in claim 3, in addition to：Positioned at the GOA regions and the electricity that is connected with the transistor
Hold overlapping element；The electric capacity, which overlaps element, to be included：The second barrier metal layer set with first barrier metal layer with layer, with institute
The second gate insulation layer that the first gate insulation layer is set with layer is stated, the second source and drain gold set with first Source and drain metal level with layer
Belong to layer, and the second protective layer set with first protective layer with layer；Characterized in that,
Second Source and drain metal level is by multiple separate isolated island structure compositions.
6. array base palte as claimed in claim 5, it is characterised in that each isolated island structure is connected by the second conductive component
Connect.
7. array base palte as claimed in claim 6, it is characterised in that second conductive component and the same layer of the pixel electrode
Set.
8. array base palte as claimed in claim 7, it is characterised in that second protective layer has and each isolated island structure
One-to-one 3rd via；
Part second conductive component is separately filled with each 3rd via.
A kind of 9. display panel, it is characterised in that including：Array base palte as described in claim any one of 1-8.
10. a kind of display device, it is characterised in that including display panel as claimed in claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710707163.7A CN107425017B (en) | 2017-08-17 | 2017-08-17 | Array substrate, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710707163.7A CN107425017B (en) | 2017-08-17 | 2017-08-17 | Array substrate, display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107425017A true CN107425017A (en) | 2017-12-01 |
| CN107425017B CN107425017B (en) | 2020-11-27 |
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| CN108231756A (en) * | 2018-01-03 | 2018-06-29 | 京东方科技集团股份有限公司 | Display device, array substrate, gate driving circuit, transistor and manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020180897A1 (en) * | 2001-06-05 | 2002-12-05 | Chae Gee Sung | Liquid crystal display and fabricating method thereof |
| CN101093845A (en) * | 2006-06-23 | 2007-12-26 | 北京京东方光电科技有限公司 | Baseplate structure of thin film transistor device array, and preparation method |
| CN104934441A (en) * | 2015-04-29 | 2015-09-23 | 京东方科技集团股份有限公司 | GOA unit, preparation method thereof, gate drive circuit and display device |
-
2017
- 2017-08-17 CN CN201710707163.7A patent/CN107425017B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020180897A1 (en) * | 2001-06-05 | 2002-12-05 | Chae Gee Sung | Liquid crystal display and fabricating method thereof |
| CN101093845A (en) * | 2006-06-23 | 2007-12-26 | 北京京东方光电科技有限公司 | Baseplate structure of thin film transistor device array, and preparation method |
| CN104934441A (en) * | 2015-04-29 | 2015-09-23 | 京东方科技集团股份有限公司 | GOA unit, preparation method thereof, gate drive circuit and display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108231756A (en) * | 2018-01-03 | 2018-06-29 | 京东方科技集团股份有限公司 | Display device, array substrate, gate driving circuit, transistor and manufacturing method |
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