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CN106653617A - 堆叠式集成电路结构及形成方法 - Google Patents

堆叠式集成电路结构及形成方法 Download PDF

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Publication number
CN106653617A
CN106653617A CN201610738898.1A CN201610738898A CN106653617A CN 106653617 A CN106653617 A CN 106653617A CN 201610738898 A CN201610738898 A CN 201610738898A CN 106653617 A CN106653617 A CN 106653617A
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CN
China
Prior art keywords
die
substrate
tube core
molding material
integrated circuit
Prior art date
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Pending
Application number
CN201610738898.1A
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English (en)
Inventor
陈伟铭
胡宪斌
侯上勇
魏文信
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN106653617A publication Critical patent/CN106653617A/zh
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Abstract

本发明实施例提供了半导体器件以及形成器件的方法。半导体器件包括具有多个第一接触焊盘的第一管芯和具有多个第二接触焊盘的第二管芯。以与第一管芯和第二管芯面对面的方位将衬底接合至多个第一接触焊盘的第一接触焊盘和多个第二接触焊盘的第一接触焊盘。第一通孔延伸穿过衬底。在第一管芯、第二管芯和衬底之间插入模制材料，模制材料沿着第一管芯、第二管芯和衬底的侧壁延伸。在多个第一接触焊盘的第二接触焊盘上方设置第二通孔，第二通孔延伸通过模制材料。

Description

堆叠式集成电路结构及形成方法
技术领域
本发明实施例涉及堆叠式集成电路结构及形成方法。
背景技术
随着半导体技术的演变，半导体芯片/管芯变得越来越小。同时，需要将更多功能集成在半导体管芯中。因此，半导体管芯需要使越来越多数量的I/O焊盘封装在更小的区域中，并且I/O焊盘的集成度随时间快速上升。因此，半导体管芯的封装变得越来越困难，这不利地影响封装件的产量。
常规封装技术可分为两类。在第一分类中，在将它们锯切之前，将晶圆上的管芯封装。该封装技术具有一些有利特征，诸如更大生产量和更低成本。此外，需要更少的底部填充物或模塑料。然而，该封装技术还具有一些缺点。如上所述，管芯的尺寸变得越来越小，并且相应的封装件仅可能是扇入型封装件，其中各个管芯的I/O焊盘限制在相应的管芯的表面正上方的区域。在管芯的区域有限的情况下，由于I/O焊盘的间距的限制，I/O焊盘的数量受到限制。如果降低焊盘的间距，可能发生焊料桥接。此外，在固定的球尺寸要求下，焊球必需具有一定尺寸，这反过来限制可被封装在管芯表面上的焊球的数量。
在其他类型的封装中，在将它们封装之前，将管芯从晶圆中锯切，并且只封装“已知良好管芯”。该封装技术的有利特征是形成扇出封装件的可能性，这是指可将管芯上的I/O焊盘再分布至比管芯更大的区域，因此可增加在管芯表面上封装的I/O焊盘的数量。
发明内容
根据本发明的一些实施例，提供了一种形成半导体器件的方法，所述方法包括：在载体衬底上设置第一管芯和第二管芯；将衬底接合至所述第一管芯和所述第二管芯，以面对面连接的方式将所述衬底与所述第一管芯和所述第二管芯连接；沿着所述第一管芯、所述第二管芯和所述衬底的侧壁形成模制材料；以及在所述第一管芯上方形成第一通孔，使得所述第一通孔延伸穿过所述模制材料至所述第一管芯。
根据本发明的另一些实施例，还提供了一种半导体器件，包括：第一管芯，具有多个第一接触焊盘；第二管芯，具有多个第二接触焊盘；衬底，接合至所述多个第一接触焊盘的第一接触焊盘和所述多个第二接触焊盘的第一接触焊盘，所述衬底位于与所述第一管芯和所述第二管芯面对面方位，并且所述第一通孔延伸穿过所述衬底；模制材料，插入在所述第一管芯、所述第二管芯和所述衬底之间，所述模制材料沿着所述第一管芯、所述第二管芯和所述衬底的侧壁延伸；以及第二通孔，设置在所述多个第一接触焊盘的第二接触焊盘上方，所述第二通孔延伸穿过所述模制材料。
根据本发明的又一些实施例，还提供了一种半导体器件，包括：第一管芯；第二管芯，位于所述第一管芯旁边；中介层，连接至所述第一管芯和所述第二管芯，所述中介层以位于所述中介层上的接触焊盘位于中介层的朝向所述第一管芯和所述第二管芯的表面上的方式定向，并且设置所述中介层使得它与各个所述第一管芯和所述第二管芯部分重叠；模制材料，插入在所述第一管芯、所述第二管芯和所述中介层之间，所述模制材料沿着所述第一管芯、所述第二管芯和所述中介层的侧壁延伸；以及第一通孔，设置在所述第一管芯的接触焊盘上方，所述第一通孔在所述第一管芯的接触焊盘和设置在所述模制材料上方的外部连接件之间延伸。
附图说明
为更完整地理解实施例及其优点，现在结合附图对下列描述进行引用，其中：
图1至图12是根据一些示例性实施例的制造通孔(TV)封装件的中间阶段的截面图；
图13是根据一些示例性实施例的TV封装件的截面图；以及
图14是根据一些示例性实施例的TV封装件的截面图。
具体实施方式
以下公开提供了多种不同实施例或实例，用于实现所提供主题的不同特征。以下将描述组件和布置的特定实例以简化本发明。当然，这些仅是实例并且不旨在限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，也可以包括其他部件可以形成在第一部件和第二部件之间使得第一部件和第二部件不直接接触的实施例。另外，本发明可以在多个实例中重复参考符号和/或字符。这种重复用于简化和清楚，并且其本身不表示所述多个实施例和/或配置之间的关系。
此外，在此可使用诸如“在…之下”、“在…下面”、“下面的”、“在…之上”、以及“上面的”等的空间关系术语，以容易地描述如图中所示的一个元件或部件与另一元件或部件的关系。除图中所示的方位之外，空间关系术语将包括使用或操作中的装置的各种不同的方位。装置可以以其它方式定位(旋转90度或在其他方位)，并且通过在此使用的空间关系描述符进行相应地解释。
根据各个示例性实施例，提供了包括通孔的堆叠式集成电路封装件及其形成方法。示出了形成封装件的中间阶段并且讨论了实施例的变型。
图1-12示出根据一些实施例的形成半导体封装件的中间步骤的截面图。在一些实施例中，可形成具有降低的成本和增大的可靠性的本文描述的半导体封装件。例如，在一些示例性实施例中，衬底与两个集成电路管芯面对面连接，并且设置衬底使得它至少部分地在两个集成电路管芯上方。衬底和集成电路管芯的方位和位置允许衬底和集成电路管芯之间和之中的较短连接，在一些实施例中这可增大可靠性和电性能。而且，在一些实施例中，衬底可允许细间距金属连接。因此，衬底能实现更小空间中的连接并且使用更少的材料，这可降低制造成本。
首先参考图1，示出了载体衬底100，在载体衬底100上形成有释放层102。通常，载体衬底100提供了在随后的加工步骤期间的临时机械和结构支撑。载体衬底100可包括任何适当的材料，例如，诸如硅晶圆、玻璃或氧化硅的硅基材料，或诸如氧化铝、陶瓷材料的其他材料，任何这些材料的组合等。在一些实施例中，将载体衬底100平坦化以适应进一步加工。
释放层102为在载体衬底100上方形成的任选层，其可以允许更容易地去除载体衬底100。如下面更详细描述的，在载体衬底100上方放置各个层和器件，此后可去除载体衬底100。任选的释放层102帮助去除载体衬底100，减少对形成在载体衬底100上方的结构的损伤。释放层102可由聚合物基材料形成。在一些实施例中，释放层102为诸如光热转换(LTHC)释放涂层的环氧基热释放材料，其在加热时丧失它的粘合性质。在其他实施例中，释放层102可为紫外(UV)胶，其在暴露于UV光时丧失它的粘合性质。释放层102可以以液体的形式分配并且固化。在其他实施例中，释放层102可为层压在载体衬底100上的层压膜。可使用其他释放层。
参考图2，根据一些实施例，将两个集成电路管芯200接合至释放层102的背面。在一些实施例中，可通过诸如管芯附接膜(DAF)的粘合层(未示出)将集成电路管芯200粘附至释放层102。粘合层的厚度可为从约5μm至约50μm的范围，诸如约10μm。集成电路管芯200可为图2所示的两个管芯200，或者在一些实施例中，可附接单个管芯或多于两个管芯。集成电路管芯200可包括适于特定设计的任何管芯。例如，集成电路管芯可包括静态随机存储存储器(SRAM)芯片或动态随机存储存储器(DRAM)芯片、处理器、存储器芯片、逻辑芯片、模拟芯片、数字芯片、中央处理单元(CPU)、图形处理单元(GPU)或其组合等。可将集成电路管芯200附接至释放层102上的适当位置以用于特定设计或应用。在被附接至释放层102之前，可根据适用的制造工艺处理集成电路管芯200以在集成电路管芯200中形成集成电路(未示出)。集成电路管芯包括在集成电路管芯200的背对载体衬底100的表面上的接触件202。接触件202允许集成电路管芯200彼此连接和/或与其他外部器件、元件等连接。如在下面更详细描述的，在一些接触件202上方形成通孔(TV)，并将衬底接合至一些其他接触件202。在集成电路管芯200的顶面上布置接触件202可以以这种方式设计，从而使得接触件202设置在TV的计划位置下方或衬底的计划位置下方。
参考图3，在集成电路管芯200上方放置衬底300，使得它与集成电路管芯200面对面连接，并且将衬底300设置为与各个集成电路管芯至少部分重叠。衬底300可允许集成电路200，衬底300内部的器件(若有的话)，以及封装件外部的器件和元件等之间和之中的电连接。取决于特定设计，结构的应用，衬底300可包含一个或多个金属连接层、一个或多个有源器件、一个或多个集成电路管芯、一个或多个无源器件、这些的组合等。衬底300还可包括一个或多个通孔(TV)302，其可允许至衬底300的外部电连接，以及通过衬底300中的金属连接件连接至接触件202。
在一些实施例中，衬底300可消除对于一个或多个再分布层的需要，这通常提供不同于现有的集成电路管芯、通孔等的图案的导电图案。例如，衬底300可提供金属连接，金属连接将以其他方式提供在一个或多个再分布层中。在一些实施例中，衬底300提供这些具有细间距的连接，这消耗封装件中较少的空间并且这可降低制造成本。例如，在一些实施例中，衬底300可包括具有约0.1μm至约20μm的间距的金属连接，诸如约0.4μm。
设置衬底300使得它与集成电路管芯200面对面连接。在一些实施例中，还设置衬底300使得它与两个相邻的集成电路管芯200部分重叠。这种配置允许衬底300和集成电路管芯200之间和之中的金属连接之间更短的距离。更短的距离可帮助增大金属连接的可靠性。
可使用已知方法预先形成衬底300。例如，可提供适当材料的衬底300。取决于特定设计，衬底300可包括一个或多个有源器件。通过化学气相沉积、溅射或适于形成ILD的任何其他方法，在衬底300和有源器件(若存在)上方形成层间电介质(ILD)。可通过应用和显影适当的光刻胶层，然后蚀刻ILD和下层衬底300以在衬底300中形成开口来形成TV 302。在该阶段形成开口以延伸至衬底300中，并且至少比ILD中的有源器件延伸得更远，并且达到至少大于完成的衬底300的最终期望高度的深度。可形成具有约5μm至约20μm的直径的开口，所述直径诸如约12μm。
一旦形成开口，可使用阻挡层和导电材料填充开口以形成TV 302。阻挡层可包括诸如氮化钛的导电材料，但是诸如氮化钽、钛、电介质等的其他材料也可以可选地使用。可使用诸如等离子体增强化学气相沉积(PECVD)的化学气相沉积(CVD)工艺形成阻挡层。然而，诸如溅射或金属有机化学气相沉积(MOCVD)的其他可选工艺也可以可选地使用。形成阻挡层以勾勒出用于下面的TV 302的开口的形状的轮廓。
导电材料可包括铜，但是诸如铝、合金、掺杂多晶硅、其组合等的其他适当材料可以可选地使用。可通过沉积晶种层，然后在晶种层上电镀铜，填充和过填充用于TV 302的开口来形成导电材料。一旦填充用于TV 302的开口，就通过诸如化学机械抛光(CMP)的研磨工艺去除TV 302的开口外部的过多阻挡层和过多导电材料，但是可使用任何适当的去除工艺。最后，将衬底300的背面减薄以暴露TV 302。可使用诸如CMP的研磨工艺实施减薄，但是诸如蚀刻的其他适当的工艺可以被可选地使用。
在衬底300的减薄之后，可实施清洗蚀刻。该清洗蚀刻旨在在CMP之后清洗和抛光衬底300。此外，该清洗蚀刻还帮助释放在研磨衬底300的CMP工艺期间可能形成的应力。清洗蚀刻可使用HNO3，但是可选地，可使用其他适当的蚀刻剂。
用于形成衬底300的本文描述的方法仅意图作为实例。可使用形成衬底300的任何适当的方法，包括相同或不同方法等。
衬底300可包括适于特定设计的任何材料。衬底300通常包括与用于形成集成电路管芯200的材料类似的材料，诸如硅。尽管衬底300可由其他材料形成，但人们认为使用硅衬底可降低应力，因为硅衬底之间的热膨胀系数(CTE)不匹配以及通常用于集成电路管芯200的硅的热膨胀系数(CTE)低于由不同材料形成的衬底的CTE。
在一些实施例中，衬底300的尺寸小于集成电路管芯200的尺寸。例如，在一些实施例中，衬底300可具有约10μm至约100μm的高度，诸如约50μm。
使用连接件304将衬底300接合至集成电路200上的接触件202。连接件304可为微凸块、焊球、金属柱、可控坍塌芯片连接(C4)凸块、无电镀镍-无电镀钯-浸金技术(ENEPIG)形成的凸块、其组合(例如，具有与其附接的焊球的金属柱)等。连接件304可包括诸如焊料、铜、铝、金、镍、银、钯、锡等或其组合的导电材料。在一些实施例中，作为实例，连接件304包括共熔材料并且可包括焊料凸块或焊球。例如，焊料材料可为铅基和无铅焊料，诸如用于铅基焊料的Pb-Sn组合物；包括InSb的无铅焊料；锡、银和铜(SAC)组合物；以及具有常用熔点并且在电应用中形成导电焊料连接的其他共熔材料。对于无铅焊料，可使用不同组成的SAC焊料，作为实例，诸如SAC 105(Sn 98.5％、Ag 1.0％、Cu 0.5％)、SAC 305和SAC 405。诸如焊球的无铅连接件可由SnCu化合物形成同时不使用银(Ag)。可选地，无铅焊料连接件可包括锡和银、Sn-Ag并且不使用铜。连接件304可形成诸如球栅阵列(BGA)的栅格。在一些实施例中，可实施回流工艺，在一些实施例中给予连接件304局部球面的形状。可选地，连接件304可包括其他形状。例如，连接件304还可包括非球形导电连接件。
接下来，参考图4，沿着集成电路管芯200和衬底300的侧壁形成模制材料400。根据一些实施例，模制材料400填充集成电路管芯200、衬底300和连接件304之间的空间。模制材料400支持集成电路管芯200和衬底300并且减少连接件304的破裂。模制材料400可包括模制底部填充物、模塑料、环氧树脂或树脂。
接下来，实施研磨步骤以减薄模制材料400直至暴露TV 302。产生的结构在图4中示出。由于研磨，TV 302的顶端与模制材料400的顶面基本齐平(共面)。由于研磨，可产生诸如金属颗粒的剩余物，并且留在顶面上。因此，在研磨之后，例如，通过湿蚀刻实施清洗以便去除剩余物。
参考图5，在模制材料400中产生多个开口500。如在下面更详细讨论的，在开口500中形成TV以实现至集成电路管芯200上的接触件202的外部电连接。可通过诸如激光钻孔、蚀刻等的任何适当的方法形成开口500。开口500的直径将取决于在开口500中将形成的计划的TV的期望直径。在一些实施例中，开口500的直径可为约50μm至约300μm，诸如约100μm。由图5可以看出，通过衬底300的高度确定开口500的高度。在一些实施例中，开口500的高度可为约50μm至约300μm，诸如约100μm。
参考图6，在开口500中形成TV 600。例如，可通过在模制材料400上方形成导电晶种层(未示出)形成TV 600。在一些实施例中，晶种层为金属层，其可为单层或包含由不同材料形成的多个子层的复合层。晶种层可由铜、钛、镍、金或其组合等制成。在一些实施例中，晶种层包括钛层和在钛层上方的铜层。例如，可使用物理气相沉积(PVD)、CVD、原子层沉积(ALD)、其组合等形成晶种层。
接下来，例如，可使用无电镀工艺或电化学镀工艺将开口500填充导电材料，从而建立TV 600。金属部件TV 600可包括铜、铝、钨、镍、焊料或其合金。TV 600的顶视图形状可为矩形、正方形、圆形等。接下来，可实施蚀刻步骤或研磨步骤以去除位于模制材料400上方的晶种层的暴露部分和位于开口500上方的任何过多导电材料。可使用任何适当的蚀刻或研磨工艺。在图6中描述产生的结构。
在一些实施例中，当晶种层由与TV 600类似或相同的材料形成时，可将晶种层与TV 600合并，并且在晶种层和TV 600之间没有可区分的界面。在一些实施例中，在晶种层和TV 600之间存在可区分的界面。
可选地，在一些实施例中，在沿着衬底300的侧壁形成模制材料之前可形成TV600。例如，如图7所示，在将衬底300接合至集成电路管芯200之前，可沿着集成电路管芯200的侧壁形成第一模制材料700。第一模制材料700填充集成电路管芯200之间的空隙，并且可与释放层102接触。第一模制材料700可包括模塑料、模制底部填充物、环氧树脂或树脂。第一模制材料700的顶面高于金属接触件202的顶端。
接下来，实施研磨步骤以减薄第一模制材料700直至暴露金属接触件202。产生的结构在图8中示出。由于研磨，金属接触件202的顶端与第一模制材料700的顶面基本齐平(共面)。由于研磨，可产生诸如金属颗粒的金属剩余物，并且留在顶面上。因此，在研磨之后，例如，通过湿蚀刻实施清洗以便去除金属剩余物。
参考图9，在金属接触件202上方形成TV 600。在一些实施例中，可沉积并图案化诸如图案化的光刻胶层的掩模层，其中，掩模层中的开口暴露TV 600的期望位置。例如，可使用无电镀工艺或电化学镀工艺将开口填充导电材料，从而建立TV 600。镀工艺可单方向填充图案化的光刻胶层中的开口(例如，从金属接触件202向上)。单方向填充可允许这种开口的更均匀的填充。可选地，可在图案化的光刻胶层中的开口的侧壁上形成晶种层，并且可多方向填充这种开口。TV 600可包括铜、铝、钨、镍、焊料或其合金。TV 600的顶视图形状可为矩形、正方形、圆形等。一旦填充用于TV 600的开口，就通过诸如化学机械抛光(CMP)的研磨工艺去除TV 600的开口外部的过多晶种层(若有的话)和过多导电材料，但是可使用任何适当的去除工艺。最后，可通过可接受的灰化或剥离工艺去除光刻胶层，诸如使用氧等离子体等。
可选地，还可通过诸如铜引线接合工艺的引线接合工艺放置的金属引线钉实现TV600。引线接合工艺的使用可消除对沉积和图案化掩模层的需求，并且镀以形成TV 600。
参考图9，使用与上述那些相同或类似的方法，使用连接件304将衬底300接合至金属接触件202。接下来，参考图10，沿着衬底300和TV 600的侧壁形成第二模制材料1000。第二模制材料1000填充TV 600和衬底300之间的空隙，并且可与第一模制材料700或金属接触件202接触。第二模制材料1000可包括模塑料、模制底部填充物、环氧树脂或树脂。第二模制材料1000的顶面高于TV 600和TV 302的顶端。
接下来，实施研磨步骤以减薄第二模制材料1000直至暴露金属接触件202。产生的结构在图11中示出。由于研磨，TV 600和TV 302的顶端与第二模制材料1000的顶面基本齐平(共面)。由于研磨，可产生诸如金属颗粒的剩余物，并且留在顶面上。因此，在研磨之后，例如，通过湿蚀刻实施清洗以便去除金属剩余物。
接下来，参考图12，在TV 600和TV 302上方形成连接件700。在一些实施例中，连接件700各自包括第一导电柱700A和在第一导电柱700A上形成的焊球700B。
可使用任何适当的方法形成连接件700。例如，可使用与上述那些类似的方法，在第二模制材料700上方沉积晶种层(未示出)。在一些实施例中，晶种层为金属层，其可为单层或包含由不同材料形成的多个子层的复合层。晶种层可由铜、钛、镍、金或其组合等制成。在一些实施例中，晶种层包括钛层和在钛层上方的铜层。例如，可使用物理气相沉积(PVD)、CVD、原子层沉积(ALD)、其组合等形成晶种层。
接下来，在模制材料400上方沉积光刻胶层并图案化以暴露TV 600和TV 302。可通过旋转涂布等形成光刻胶层，并且可使用可接受的光刻工艺将光刻胶层暴露于光以用于图案化。接下来，可通过在光刻胶层的开口中和在晶种层上形成导电材料来形成导电柱700A。可通过诸如电镀或无电镀等的镀形成导电材料。导电材料可包括金属，例如铜、钛、钨、铝等，例如，其可具有比焊料更高的回流温度。第一导电柱700A的宽度对应于光刻胶层中的开口的宽度并且可为从约20μm至约200μm的范围，诸如约100μm。导电柱700A的高度可为从约20μm至约150μm的范围，诸如约40μm，其中，垂直于模制材料400的顶侧测量高度。
可使用诸如电镀或无电镀的镀、丝网印刷等在导电柱700A上和在光刻胶层的开口中形成焊帽700B。焊帽700B可为诸如无铅焊料的任何可接受的低温可回流导电材料。焊帽700B的宽度对应于光刻胶层的开口和导电柱700A中的宽度并且可从约20μm至约200μm的范围，诸如约100μm。焊帽700B的厚度可从约5μm至约50μm的范围，诸如约20μm，其中，垂直于模制材料400的顶侧测量厚度。连接件700(例如，导电柱700A和焊帽700B)的高度为从约25μm至约200μm的范围，诸如约60μm。在形成焊帽700B之后，可通过可接受的灰化或剥离工艺去除光刻胶层，诸如使用氧等离子体等。
接下来，在完成加工之后，去除载体衬底100。还去除释放层102。如果建立多于一个封装件，则将晶圆切割成单个封装件。产生的结构在图13中示出。
其他实施例是可能的。例如，图14示出包含三个集成电路管芯200和两个衬底300的封装件。衬底300和集成电路管芯200处于面对面方位并且通过连接件304连接。设置各个衬底300使得它与两个集成电路管芯200部分重叠。连接件700提供至封装件的外部电连接。可使用与本文描述的方法相同或相似的方法形成图14中描述的实施例。
在一些实施例中，可形成具有降低的成本和增大的可靠性的本文描述的半导体封装件。例如，在一些示例性实施例中，衬底与两个集成电路管芯面对面连接，并设置衬底使得它与两个集成电路管芯至少部分重叠。衬底和集成电路管芯的方位和位置允许衬底和集成电路管芯之间和之中的较短连接，这在一些实施例中可增大可靠性。而且，在一些实施例中，衬底可允许细间距金属连接。因此，衬底可实现在较小的空间中的电连接并且使用较少的材料，这可降低制造成本。
在一些实施例中，提供了制造半导体器件的方法。方法包括在载体衬底上设置第一管芯和第二管芯。将衬底接合至第一管芯和第二管芯使得衬底以面对面连接的方式与第一管芯和第二管芯连接。沿着第一管芯、第二管芯和衬底的侧壁形成模制材料。在第一管芯上方形成第一通孔使得第一通孔延伸通过模制材料至第一管芯。
在一些实施例中，提供了半导体器件。半导体器件包括具有多个第一接触焊盘的第一管芯和具有多个第二接触焊盘的第二管芯。衬底以与第一管芯和第二管芯面对面的方位接合至多个第一接触焊盘的第一接触焊盘和多个第二接触焊盘的第一接触焊盘。第一通孔延伸通过衬底。模制材料插入在第一管芯、第二管芯和衬底之间，模制材料沿着第一管芯、第二管芯和衬底的侧壁延伸。第二通孔设置在多个第一接触焊盘的第二接触焊盘上方，第二通孔延伸通过模制材料。
在一些实施例中，提供了半导体器件。半导体器件包括第一管芯和在第一管芯旁边的第二管芯。中介层连接至第一管芯和第二管芯，所述中介层以中介层上的接触焊盘位于中介层的朝向第一管芯和第二管芯的表面上的方式定向。设置中介层使得它与各个第一管芯和第二管芯部分重叠。模制材料插入在第一管芯、第二管芯和中介层之间，模制材料沿着第一管芯、第二管芯和中介层的侧壁延伸。第一通孔设置在第一管芯的接触焊盘上方，第一通孔在第一管芯的接触焊盘和设置在模制材料上方的外部连接件之间延伸。
根据本发明的一些实施例，提供了一种形成半导体器件的方法，所述方法包括：在载体衬底上设置第一管芯和第二管芯；将衬底接合至所述第一管芯和所述第二管芯，以面对面连接的方式将所述衬底与所述第一管芯和所述第二管芯连接；沿着所述第一管芯、所述第二管芯和所述衬底的侧壁形成模制材料；以及在所述第一管芯上方形成第一通孔，使得所述第一通孔延伸穿过所述模制材料至所述第一管芯。
在上述方法中，还包括：在所述第一通孔上方形成第一柱连接件；在所述衬底中的通孔上方形成第二柱连接件；以及去除所述载体衬底。
在上述方法中，还包括在每个所述第一柱连接件和所述第二柱连接件上方形成焊帽。
在上述方法中，所述衬底包括具有约0.1μm至约20μm的间距的金属连接。
在上述方法中，使用微凸块连接件将所述衬底接合至所述第一管芯和所述第二管芯。
在上述方法中，形成所述第一通孔包括：使用激光钻孔在所述模制材料中建立开口，其中，在所述开口中形成所述第一通孔。
在上述方法中，还包括：在所述载体衬底上的所述第一管芯旁边设置第三管芯；将第二衬底接合至所述第一管芯和所述第三管芯，以面对面方式将第二衬底与所述第一管芯和所述第三管芯连接；在所述第三管芯上方形成所述模制材料；以及在所述第三管芯上方形成第二通孔，使得所述第二通孔延伸穿过所述模制材料至所述第三管芯。
根据本发明的另一些实施例，还提供了一种半导体器件，包括：第一管芯，具有多个第一接触焊盘；第二管芯，具有多个第二接触焊盘；衬底，接合至所述多个第一接触焊盘的第一接触焊盘和所述多个第二接触焊盘的第一接触焊盘，所述衬底位于与所述第一管芯和所述第二管芯面对面方位，并且所述第一通孔延伸穿过所述衬底；模制材料，插入在所述第一管芯、所述第二管芯和所述衬底之间，所述模制材料沿着所述第一管芯、所述第二管芯和所述衬底的侧壁延伸；以及第二通孔，设置在所述多个第一接触焊盘的第二接触焊盘上方，所述第二通孔延伸穿过所述模制材料。
在上述半导体器件中，还包括设置在所述多个第二接触焊盘的第二接触焊盘上方的第三通孔，所述第三通孔延伸穿过所述模制材料。
在上述半导体器件中，还包括设置在所述衬底上方并且连接至所述第一通孔的第一柱连接件；以及设置在所述模制材料上方并且连接至所述第二通孔的第二柱连接件。
在上述半导体器件中，还包括在各个所述第一柱连接件和所述第二柱连接件上方的焊帽。
在上述半导体器件中，所述衬底包括具有约0.1μm至约20μm的间距的金属连接。
在上述半导体器件中，设置所述衬底使得它部分地位于各个所述第一管芯和所述第二管芯上方。
在上述半导体器件中，以所述衬底的中心点位于所述第一管芯和所述第二管芯之间的区域上方的方式设置所述衬底。
根据本发明的又一些实施例，还提供了一种半导体器件，包括：第一管芯；第二管芯，位于所述第一管芯旁边；中介层，连接至所述第一管芯和所述第二管芯，所述中介层以位于所述中介层上的接触焊盘位于中介层的朝向所述第一管芯和所述第二管芯的表面上的方式定向，并且设置所述中介层使得它与各个所述第一管芯和所述第二管芯部分重叠；模制材料，插入在所述第一管芯、所述第二管芯和所述中介层之间，所述模制材料沿着所述第一管芯、所述第二管芯和所述中介层的侧壁延伸；以及第一通孔，设置在所述第一管芯的接触焊盘上方，所述第一通孔在所述第一管芯的接触焊盘和设置在所述模制材料上方的外部连接件之间延伸。
在上述半导体器件中，所述中介层包括具有约0.1μm至约20μm的间距的金属连接。
在上述半导体器件中，还包括第三管芯，位于所述第一管芯旁边；第二中介层，连接至所述第三管芯和所述第一管芯，所述第二中介层以所述接触焊盘位于所述第二中介层的朝向所述第一管芯和所述第三管芯的表面上的方式定向，并且设置所述第二中介层使得它与各个所述第一管芯和所述第三管芯部分重叠；以及第二通孔，设置在所述第三管芯的接触焊盘上方，所述第二通孔从所述第三管芯的接触焊盘延伸穿过所述模制材料至设置在所述模制材料上方的柱连接件。
在上述半导体器件中，中介层通孔延伸通过所述中介层。
在上述半导体器件中，所述中介层的表面与所述模制材料的表面共面。
在上述半导体器件中，还包括连接至所述第一通孔的第一柱连接件和连接至中介层通孔的第二柱连接件。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。此外，每条权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。

Claims (1)

1.一种形成半导体器件的方法，所述方法包括：
在载体衬底上设置第一管芯和第二管芯；
将衬底接合至所述第一管芯和所述第二管芯，以面对面连接的方式将所述衬底与所述第一管芯和所述第二管芯连接；
沿着所述第一管芯、所述第二管芯和所述衬底的侧壁形成模制材料；以及
在所述第一管芯上方形成第一通孔，使得所述第一通孔延伸穿过所述模制材料至所述第一管芯。
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