CN105792533A - Manufacturing method of PCB and PCB - Google Patents
Manufacturing method of PCB and PCB Download PDFInfo
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- CN105792533A CN105792533A CN201410800051.2A CN201410800051A CN105792533A CN 105792533 A CN105792533 A CN 105792533A CN 201410800051 A CN201410800051 A CN 201410800051A CN 105792533 A CN105792533 A CN 105792533A
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- line pattern
- pcb
- thickness
- insulating barrier
- metal level
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Abstract
The embodiment of the invention discloses a manufacturing method of a PCB. The manufacturing method is used for reducing the side etching influence in a line pattern manufacturing process and improving the qualified rate of manufacturing a fine line. The method comprises the following steps: carrying out exposure and development on a dry film to form a through groove for manufacturing a line pattern; covering a metal layer on the PCB with the dry film, and etching the metal layer through the through groove to form a line pattern region and a non-line pattern region; etching away the metal layer in the non-line pattern region to form the line pattern; and thickening the line pattern to the target thickness. The embodiment of the invention further provides the PCB. The PCB is used for reducing the side etching influence in the line pattern manufacturing process and improving the qualified rate of manufacturing the fine line.
Description
Technical field
The present invention relates to surface-mounted integrated circuit technical field, particularly relate to manufacture method and the PCB of a kind of PCB
Background technology
Printed circuit board (PCB) is (English: PrintedCircuitBoard, PCB, it is called for short: PCB), it is by insulated substrate, connect the pad composition of wire and welding electronic component, there is the dual function of wire and insulating base, it can realize the electrical connection of each components and parts in circuit, replace complicated wiring, reduce the workload under traditional approach, simplify the assembling of electronic product, welding, debugging efforts, reduce machine volume, reduce product cost, improve the q&r of electronic equipment, printed substrate has good homogeneity of product, it can adopt standardized designs, be conducive to realizing mechanization and automatization in process of production, make monoblock through the printed substrate of assembling and setting as a spare part, it is easy to exchange and the maintenance of machine product.
Along with the development of electronic product, the especially appearance of electronic computer, printed wire plate technique is proposed highdensity requirement, therefore the circuit pattern on PCB need to have higher precision and density, i.e. fine-line.
The manufacture method general step of current circuit is that first heavy copper, imposite are electroplated on circuit boards, then carries out outer graphics transfer, prepares line pattern then through after development etching.But when adopting existing processing technology to make fine-line, owing to line pattern is subject to impact of side etching, it is difficult to ensure the qualification rate of fine-line.
Summary of the invention
Embodiments provide manufacture method and the PCB of a kind of PCB, for reducing the impact of lateral erosion in line pattern manufacturing process, improve the qualification rate making fine-line.
The manufacture method of a kind of PCB that embodiment of the present invention first aspect provides, including: dry film is exposed development, to form the groove for making line pattern；
The metal level of pcb board covers described dry film, and by described groove, described metal level is etched, to form line pattern region and logicalnot circuit graphics field；
The etching metal layer of described logicalnot circuit graphics field is fallen, to form line pattern；
Described line pattern is thickeied to target thickness.
In conjunction with the first aspect of the embodiment of the present invention, in the first implementation of embodiment of the present invention first aspect, also included before target thickness described line pattern is thickeied: cover the first insulating barrier in described logicalnot circuit graphics field.
In conjunction with the first implementation of the first aspect of the embodiment of the present invention, in the second implementation of embodiment of the present invention first aspect, bigger than the thickness of described metal level 20～50 μm of the thickness of described first insulating barrier.
First aspect in conjunction with the embodiment of the present invention, in the third implementation of embodiment of the present invention first aspect, before metal level on described pcb board is etched, also includes described pcb board surface is carried out roughening treatment, and plate described metal level on the pcb.
In conjunction with the third implementation of the first aspect of the embodiment of the present invention, in the 4th kind of implementation of embodiment of the present invention first aspect, described roughening treatment includes: described pcb board surface is carried out pickling and/or blasting treatment.
First aspect in conjunction with the embodiment of the present invention, in the 5th kind of implementation of embodiment of the present invention first aspect, described thicken described line pattern to target thickness mode includes: by the mode of plating or chemical plating on described line pattern, thickening the thickness of described line pattern to target thickness, described metal level is layers of copper.
In conjunction with the 5th kind of implementation of the first aspect of the embodiment of the present invention, in the 6th kind of implementation of embodiment of the present invention first aspect, the thickness of described line pattern is 15～25 μm, and described target thickness is 45～65 μm.
In conjunction with the first aspect of the embodiment of the present invention, in the 7th kind of implementation of embodiment of the present invention first aspect, after by described line pattern thickening to target thickness, it is additionally included on described pcb board and the second insulating barrier is set, to cover described line pattern.
The 7th kind of implementation in conjunction with the first aspect of the embodiment of the present invention, in the 8th kind of implementation of embodiment of the present invention first aspect, on described pcb board after silk-screen the second insulating barrier, the predeterminated position being additionally included on described second insulating barrier carries out alkaline development, so that the line pattern of described predeterminated position exposes.
The 8th kind of PCB that implementation is obtained that a kind of PCB, described PCB are the 7th kind of implementation in conjunction with the 5th kind of implementation of the third implementation of the second implementation of the first aspect of the embodiment of the present invention or the first implementation of first aspect or first aspect or the second implementation of first aspect or first aspect or the 4th kind of implementation of first aspect or first aspect or the 6th kind of implementation of first aspect or first aspect or first aspect that embodiment of the present invention second aspect provides.
Application technical scheme, has the advantages that
On the metal level of PCB, first make line pattern, then this line pattern is thickeied to target thickness, directly it is etched on the metal level of target thickness relative to prior art, the etching period making line pattern can be shortened, play the impact reducing line pattern by lateral erosion, thus improving the qualification rate of fine-line.
Accompanying drawing explanation
The Making programme that Fig. 1 is a kind of PCB in the embodiment of the present invention illustrates intention；
Another Making programme that Fig. 2 A is a kind of PCB in the embodiment of the present invention illustrates intention；
Fig. 2 B to Fig. 2 J is the structural representation of a kind of PCB manufacturing process in the embodiment of the present invention.
Detailed description of the invention
Embodiments provide manufacture method and the PCB of a kind of PCB, for reducing the impact of lateral erosion in line pattern manufacturing process, it is adaptable to the making of fine-line.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those skilled in the art obtain under not making creative work premise, broadly fall into the scope of protection of the invention.、
It should be noted that the term used in embodiments of the present invention is only merely for the purpose describing specific embodiment, and it is not intended to be limiting the present invention." one ", " described " and " being somebody's turn to do " of the singulative used in the embodiment of the present invention and appended claims is also intended to include most form, unless context clearly shows that other implications.
To facilitate understanding of the present embodiment of the invention, first the scene that the embodiment of the present invention is applied is introduced at this, the technical scheme of the embodiment of the present invention, the PCB being applied to have fine pitch outer-layer circuit figure makes, the spacing of this line pattern is 70～100 μm, and the metal level on this pcb board is generally layers of copper, in actual applications all right aluminium lamination or other metal levels, specifically it is not construed as limiting herein, is specifically described for layers of copper for metal level below:
Referring to Fig. 1, in the embodiment of the present invention, an embodiment of the manufacture method of a kind of circuit board includes:
101, on the metal level of pcb board, dry film is covered, to form line pattern region and logicalnot circuit graphics field.
It is understood that this layers of copper is bonded on pcb board after can be through lamination, it is also possible to covered on this pcb board by electroless copper plating, be specifically not construed as limiting herein.
First, dry film it is exposed and develops, thus forming the groove for making line pattern on dry film, then this dry film being covered in layers of copper, by the groove on this dry film, the logicalnot circuit graphics field in layers of copper being exposed.
102, the etching metal layer of described logicalnot circuit graphics field is fallen, to form line pattern.
After covering dry film on the metal layer, re-use the liquid medicine layers of copper to logicalnot circuit graphics field and be etched, thus forming line pattern.
103, described line pattern is thickeied to target thickness.
After making line pattern, the thickness of this line pattern is thickeied, thus reaching the thickness of target.
Wherein the target thickness of this line pattern is specified by client, or can according to the practical application of PCB time, this line pattern needs through size of current, it is determined that the target thickness of this line pattern.
In the embodiment of the present invention, on the metal level of PCB, first make line pattern, then this line pattern is thickeied to target thickness, directly it is etched on the metal level of target thickness relative to prior art, the etching period making line pattern can be shortened, play the impact reducing line pattern by lateral erosion, thus improving the qualification rate of fine-line.
In above example, the line pattern made is thickeied to target thickness, in actual applications, specifically can pass through the mode electroplated, this line pattern is thickeied, below the another embodiment of the manufacture method of a kind of PCB of the embodiment of the present invention is described:
Refer to Fig. 2 A to Fig. 2 J, the manufacture method of a kind of PCB in the embodiment of the present invention, specifically include:
Alternatively, in the present embodiment, the metal level of pcb board covers before dry film, also includes step 201 and 202.
201, pcb board surface is carried out roughening treatment.
Refer to Fig. 2 B, in order to improve the adhesion on pcb board 201 surface and metal level, the surface of pcb board 201 can be carried out roughening treatment, wherein, the mode carrying out roughening treatment is specifically as follows pickling and/or blasting treatment, as by dilute hydrochloric acid or dilute sulfuric acid, the surface of pcb board 201 is carried out, thus reaching the effect of alligatoring.
202, heavy copper and plating are carried out on pcb board 201 surface, thus forming layers of copper 202.
Refer to Fig. 2 C, after the surface of pcb board is carried out roughening treatment, pass through chemical plating process, first on this pcb board, carry out heavy copper, form bottom copper, then electroplate on this bottom copper, obtaining the copper layer thickness needed, wherein, the thickness of this layers of copper 202 is generally 15～25 μm.
Alternatively, after forming layers of copper 202 through heavy copper and plating, it is also possible to by layers of copper 202 being carried out the mode of microetch, the thickness of this layers of copper is controlled, thick with the copper obtaining needing.
203, on the metal level of pcb board 201, dry film is covered, to form line pattern region and logicalnot circuit graphics field.
First, dry film it is exposed and develops, thus forming the groove for making line pattern on dry film, then this dry film being covered in layers of copper, by the groove on this dry film, the logicalnot circuit graphics field in layers of copper being exposed.
204, the etching metal layer of described logicalnot circuit graphics field 2022 is fallen, to form line pattern 2021.
Referring to Fig. 2 D, after covering dry film on the metal layer, re-use the liquid medicine layers of copper to logicalnot circuit graphics field 2022 and be etched, thus forming line pattern 2021, the thickness of this line pattern 2021 is 15～25 μm.
Alternatively, in the present embodiment, after forming line pattern 2021, also include step 205 and 206.
205, carrying out heavy copper in logicalnot circuit graphics field, forming layers of copper 207, so that being attached between line pattern.
Refer to figure E and be likely to exist with the form of isolated pad due to the line pattern 2021 formed after overetch, in order to line pattern is thickeied by the mode by electroplating, need to be attached between line pattern, to form the conductive layer of entirety, specifically can sink copper at least one times in logicalnot circuit graphics field 2022, to form the layers of copper 207 that thickness is 1～2 μm.
206, the first insulating barrier 203 is covered in described logicalnot circuit graphics field 2022.
Refer to Fig. 2 F, it is understandable that, when line pattern 2021 being thickeied by electroplating technology, easily there is plating in logicalnot circuit graphics field 2022, cause that line pattern 2021 thickness is inconsistent, therefore when line pattern 2021 is electroplated, it is possible to by filling or cover insulating barrier 203 in logicalnot circuit graphics field 2022, thus avoiding plating.
In the present embodiment, the layers of copper 207 of logicalnot circuit graphics field covers insulating barrier 203 and bigger than the thickness of line pattern 2,021 20～50 μm of the thickness of this insulating barrier 203, the folder film phenomenon occurred when circuit graphic plating thickeies can be prevented.
It should be noted that the mode wherein filling or covering insulating barrier 203 in logicalnot circuit graphics field 2022 can be silk-screen, coating or other modes, specifically it is not construed as limiting herein.
207, described line pattern is thickeied to target thickness.
Refer to Fig. 2 F, after making line pattern, the thickness of this line pattern 2021 is thickeied, thus reaching the thickness of target.
Wherein the target thickness of this line pattern 2021 is specified by client, or can according to the practical application of PCB time, this line pattern 2021 needs the size of current of process, it is determined that the target thickness of this line pattern.
It should be noted that in the present embodiment, the target thickness of this line pattern 2021 is 45～65 μm, in actual applications, the target thickness of this line pattern 2021 can also be other values, is not construed as limiting herein.
Alternatively, after step 207,208 and 209 are also included.
208, the second insulating barrier 204 is set on described pcb board.
Referring to Fig. 2 G, it is possible to by the mode of silk-screen, the line pattern after thickening increases insulation 204 layers, alternatively, this insulating barrier 204 is epoxy resin layer, bigger than the thickness of described line pattern 2,021 10～20 μm of the thickness of this epoxy resin layer.
209, on described second insulating barrier, the predeterminated position of 204 carries out alkaline development, so that the line pattern of described predeterminated position exposes.
Refer to Fig. 2 H to scheming I, after line pattern 2021 covers the second insulating barrier 204, predeterminated position 205 on this second insulating barrier 204 is carried out alkaline development, wherein this position 205 preset is the position needing to place components and parts, such as can use alkalescence developing solution that this second insulating barrier 204 is developed, thus windowing placing component locations formation, line pattern is made to expose, and power on the surface-coated such as plating nickel gold 206 at the line pattern 2021 exposed, with the impact preventing line pattern 2021 from because of oxidation, PCB serviceability being caused.
It should be noted that in the present embodiment, step 208 and 209 can not be performed after step 207, but after direct-on-line road figure thickeies, power on plating nickel gold at line pattern, be specifically not construed as limiting herein.
210, insulating barrier and layers of copper 207 are removed.
Refer to Fig. 2 J, use alkalescence to take off film liquid and take off the non-graphic region except insulating barrier 204 correspondence and insulating barrier 203, re-use micro-corrosion liquid or etching solution removes layers of copper 207, form 2021 complete line layers.
The invention process, in the layers of copper of PCB, first make line pattern 2021, then this line pattern 2021 is thickeied to target thickness, relative to prior art, the etching period making line pattern can be shortened, play the impact reducing line pattern by lateral erosion, thus improving the qualification rate of fine-line, additionally, line pattern 2021 is thickeied to after target thickness, line pattern 2021 covers insulating barrier 204, and the predeterminated position of insulating barrier 204 is carried out alkaline development make line pattern 2021 expose, namely formed on insulating barrier 204 and window, then re-plating nickel gold, the purpose of selectivity plating nickel gold can be reached, while satisfied use needs, raising efficiency, save manufacturing cost.
It is the PCB obtained by the manufacture method in above-described embodiment that the embodiment of the present invention also provides for a kind of PCB, this PCB, and wherein, the concrete structure of PCB may refer to above-mentioned relevant schematic diagram, and for other parts on PCB, such as on PCB, boring etc. does not limit.
Those skilled in the art is it can be understood that arrive, for convenience and simplicity of description, the system of foregoing description, the specific works process of device and unit, it is possible to reference to the corresponding process in preceding method embodiment, do not repeat them here.
In several embodiments provided herein, it should be understood that disclosed printed substrate and preparation method thereof, it is possible to realize by another way.Such as, printed substrate embodiment described above is merely schematic, and actual can have other dividing mode when realizing.
The above, above example only in order to technical scheme to be described, is not intended to limit；Although the present invention being described in detail with reference to previous embodiment, it will be understood by those within the art that: the technical scheme described in foregoing embodiments still can be modified by it, or wherein portion of techniques feature is carried out equivalent replacement；And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (10)
1. the manufacture method of a PCB, it is characterised in that including:
Dry film is exposed development, to form the groove for making line pattern；
The metal level of pcb board covers described dry film, and by described groove, described metal level is etched, to form line pattern region and logicalnot circuit graphics field；
The etching metal layer of described logicalnot circuit graphics field is fallen, to form line pattern；
Described line pattern is thickeied to target thickness.
2. method according to claim 1, it is characterised in that also included before target thickness described line pattern is thickeied: cover the first insulating barrier in described logicalnot circuit graphics field.
3. method according to claim 2, it is characterised in that bigger than the thickness of described metal level 20～50 μm of the thickness of described first insulating barrier.
4. method according to claim 1, it is characterised in that before the metal level on described pcb board is etched, also includes described pcb board surface is carried out roughening treatment, and plates described metal level on the pcb.
5. method according to claim 4, it is characterised in that described roughening treatment includes: described pcb board surface is carried out pickling and/or blasting treatment.
6. method according to claim 1, it is characterized in that, described thicken described line pattern to target thickness mode includes: by the mode of plating or chemical plating on described line pattern, thickening the thickness of described line pattern to target thickness, described metal level is layers of copper.
7. wanting the method described in 6 according to right, it is characterised in that the thickness of described line pattern is 15～25 μm, described target thickness is 45～65 μm.
8. method according to claim 1, it is characterised in that after by described line pattern thickening to target thickness, be additionally included on described pcb board and the second insulating barrier is set, to cover described line pattern.
9. method according to claim 8, it is characterised in that on described pcb board after silk-screen the second insulating barrier, the predeterminated position being additionally included on described second insulating barrier carries out alkaline development, so that the line pattern of described predeterminated position exposes.
10. a PCB, it is characterised in that described PCB is the PCB that the manufacture method any one of claim 1 to 9 is obtained.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410800051.2A CN105792533B (en) | 2014-12-19 | 2014-12-19 | A kind of production method and PCB of PCB |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410800051.2A CN105792533B (en) | 2014-12-19 | 2014-12-19 | A kind of production method and PCB of PCB |
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| CN105792533A true CN105792533A (en) | 2016-07-20 |
| CN105792533B CN105792533B (en) | 2018-11-02 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107835564A (en) * | 2017-10-19 | 2018-03-23 | 广东欧珀移动通信有限公司 | A kind of flexible PCB and preparation method thereof, electronic equipment |
| CN109638435A (en) * | 2018-11-27 | 2019-04-16 | 深圳市臻鼎盛通讯有限公司 | The manufacturing process and 5G antenna of a kind of non-metallic substrate antenna or route |
| CN110029375A (en) * | 2019-05-14 | 2019-07-19 | 四川海英电子科技有限公司 | The circulation copper electroplating method of high-order high-density circuit board |
| CN114641136A (en) * | 2020-12-16 | 2022-06-17 | 深南电路股份有限公司 | Method for manufacturing copper layer boss of circuit board and circuit board |
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| US20090032493A1 (en) * | 2007-08-03 | 2009-02-05 | Tsung Kuei Chang | Method For Manufacturing Predetermined Pattern |
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| CN103491710A (en) * | 2013-09-09 | 2014-01-01 | 莆田市龙腾电子科技有限公司 | Process for processing two-sided and multilayer circuit board |
| CN103687309A (en) * | 2012-09-24 | 2014-03-26 | 广东兴达鸿业电子有限公司 | Production process for high-frequency circuit board |
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Patent Citations (4)
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|---|---|---|---|---|
| US20090032493A1 (en) * | 2007-08-03 | 2009-02-05 | Tsung Kuei Chang | Method For Manufacturing Predetermined Pattern |
| CN102677135A (en) * | 2011-03-17 | 2012-09-19 | 深圳市深联电路有限公司 | Electroplating production device and method for high-precision circuit board with complete metal wrapped edge |
| CN103687309A (en) * | 2012-09-24 | 2014-03-26 | 广东兴达鸿业电子有限公司 | Production process for high-frequency circuit board |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107835564A (en) * | 2017-10-19 | 2018-03-23 | 广东欧珀移动通信有限公司 | A kind of flexible PCB and preparation method thereof, electronic equipment |
| CN109638435A (en) * | 2018-11-27 | 2019-04-16 | 深圳市臻鼎盛通讯有限公司 | The manufacturing process and 5G antenna of a kind of non-metallic substrate antenna or route |
| CN110029375A (en) * | 2019-05-14 | 2019-07-19 | 四川海英电子科技有限公司 | The circulation copper electroplating method of high-order high-density circuit board |
| CN114641136A (en) * | 2020-12-16 | 2022-06-17 | 深南电路股份有限公司 | Method for manufacturing copper layer boss of circuit board and circuit board |
| CN114641136B (en) * | 2020-12-16 | 2024-05-14 | 深南电路股份有限公司 | Manufacturing method of copper layer boss of circuit board and circuit board |
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| CN105792533B (en) | 2018-11-02 |
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Address after: 518053 No. 99 East Qiaocheng Road, Nanshan District, Shenzhen City, Guangdong Province Patentee after: SHENZHEN SHENNAN CIRCUIT CO., LTD. Address before: 518053 No. 99 East Qiaocheng Road, Nanshan District, Shenzhen City, Guangdong Province Patentee before: Shenzhen Shennan Circuits Co., Ltd. |