CN105515413B - A kind of output voltage sampling circuit and method based on AC-DC converter - Google Patents
A kind of output voltage sampling circuit and method based on AC-DC converter Download PDFInfo
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- CN105515413B CN105515413B CN201510895297.7A CN201510895297A CN105515413B CN 105515413 B CN105515413 B CN 105515413B CN 201510895297 A CN201510895297 A CN 201510895297A CN 105515413 B CN105515413 B CN 105515413B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/145—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
- H02M7/155—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
- H02M7/162—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only in a bridge configuration
- H02M7/1623—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only in a bridge configuration with control circuit
- H02M7/1626—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only in a bridge configuration with control circuit with automatic control of the output voltage or current
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
- H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
Abstract
The present invention relates to a kind of output voltage sampling circuit and method based on AC-DC converter, the circuit include：Output voltage detecting circuit, error amplifier, PDM keyer, degaussing time detection circuit and timer；Output voltage detecting circuit exports feedback voltage for sampling and keeping FB signals；Feedback voltage is compared by error amplifier with reference voltage, exports first voltage；Degaussing time detection circuit is detected the degaussing time of FB signals, exports the first testing result；Timer controls PDM keyer according to the first testing result, exports controlling value；PDM keyer exports gate signal according to the pulsewidth of controlling value and first voltage adjusting pulsewidth modulated signal.The present invention is modulated the Gate signal opening times by the collective effect of pulse-width modulation PWM controller, degaussing time detection circuit and timer, can accurately FB waveforms be acquired under any circumstance by realizing in the case where exporting constant voltage.
Description
Technical field
The present invention relates to IC design fields, and in particular to a kind of output voltage based on AC-DC converter
Sample circuit and method.
Background technology
In AC-DC converter circuit, the voltage of sampling transformer inductance can be passed through to the detection of output voltage
It realizes, and primary inductance voltage can be transferred to pulse modulation controller by transformer auxiliary winding.Fig. 1 is the prior art
In a kind of AC-DC converter in output voltage sampling circuit structural schematic diagram.As shown in Figure 1, resistance R1 is indicated
The series parasitic resistance of secondary windings and the series parasitic resistance of output lead and.In the case where inputting identical line voltage, no
Different with the load current of output loading, the output voltage of secondary windings is distinguishing at this time.
When output loading is heavier, the voltage or current waveform of each node are as shown in Figure 2.Output voltage by auxiliary around
Group and the waveform sampling of the feedback signal FB after resistor voltage divider network R2, R3 obtain.Within the inductance degaussing time (Tdmg), FB electricity
Pressure, i.e. FB=k*Vout directly proportional to output voltage, scale parameter k are：Wherein, Ns is transformer
Secondary winding turns, Na are transformer auxiliary winding the number of turns.Due to the presence of transformer leakage inductance, in the wink that the degaussing time starts
Between, the voltage waveform of FB will produce a decaying concussion, is detected to FB waveforms will appear detection error during this period.Therefore
Effective detection time needs (front end blanking time LEB) after the degaussing time starts a period of time that could start.Work as output
When light load, the gate signal Gate relative to load resistance value when larger as shown in Figure 3, the opening time of Gate at this time subtracts
Small, the peak point current of primary inductance accordingly reduces, this will be such that the degaussing time also reduces.When load changes to it is sufficiently small when, degaussing
Time, which can be reduced to FB waveforms, does not have the effective sampling time, can not detect output voltage at this time.
Invention content
To solve the above-mentioned problems, on the one hand, the present invention provides a kind of output voltages based on AC-DC converter
Sample circuit, the circuit include：Output voltage detecting circuit, error amplifier, PDM keyer, degaussing time detection electricity
Road and timer, output voltage detecting circuit export feedback voltage for sampling and keeping FB signals；Error amplifier is used for will
Feedback voltage is compared with reference voltage, exports first voltage；When degaussing time detection circuit is used for the degaussing to FB signals
Between be detected, export the first testing result；Timer is for controlling PDM keyer according to the first testing result
System exports controlling value；PDM keyer is used for according to controlling value and first voltage, the pulsewidth of adjusting pulsewidth modulated signal,
Export gate signal.
Further, degaussing time detection circuit is detected FB signals, specially；Disappear more than front end when the degaussing time
When the hidden time, the first testing result of degaussing time detection circuit output is the first level, then the controlling value of timer output is
First level；When the degaussing time being less than the front end blanking time, the first testing result of degaussing time detection circuit output is the
Two level, then the controlling value of timer output is second electrical level.
Further, PDM keyer includes simulation accumulator circuit；Simulate an input termination of accumulator circuit
Receive the first voltage of error amplifier circuit output, the controlling value of another input terminal count pick up device output, output end output the
Two voltages；PDM keyer is used for according to controlling value and first voltage, the pulsewidth of adjusting pulsewidth modulated signal, out gate letter
Number；The modulated signal of PDM keyer is modulated according to second voltage, exports gate signal.
Further, simulation accumulator circuit includes：Operational amplifier, resistance, variable current source circuit and asynchronous timing
Device circuit；Wherein, every branch is composed in series by a switch with a current source in variable current source circuit；Asynchronous timing
The controlling value of the input terminal count pick up device output of device circuit, another input terminal receive modulated signal, output end output control
The control signal of variable current source circuit；The switch of each branch road of variable current source circuit is controlled by asynchronous timer circuit
The control signal of output, one end of variable current source circuit are grounded by current source, and the other end of variable current source circuit passes through
Switch is connected with one end of resistance；The other end of resistance is connected with the output end of operational amplifier；One input terminal of operational amplifier
First voltage is received, another input terminal receives the node voltage of resistance and variable current source circuit, and output end exports second voltage.
Further, asynchronous timer circuit includes：Trigger corresponding with each branch in variable current source circuit or
NOT gate and with door.
Further, the current source of each branch is arranged by certain coding mode in variable current source circuit.
Further, PDM keyer includes delay circuit；Delay circuit includes inverter circuit and asynchronous timing
Device circuit；Inverter circuit includes：Analog inverter, phase inverter and the parallel circuit being made of with switch capacitance；Wherein, mould
Quasi- phase inverter is for controlling delay time；Every branch includes a switch and a capacitance in parallel circuit, parallel circuit
One end is connected to the input terminal of phase inverter by switch, and the other end of parallel circuit passes through capacity earth；The output end of phase inverter
Output end as delay circuit；Input terminal of the input terminal of analog inverter as delay circuit, the output of analog inverter
End is connected to the input terminal of phase inverter；
One input terminal of asynchronous timer circuit receives the controlling value of timer output, output control signal, for controlling simultaneously
Join the break-make of branch in circuit；When inverter circuit controls the delay of delay circuit by the charging time of capacitance in parallel circuit
Between；By controlling the delay time of delay circuit, the modulated signal of PDM keyer is modulated, gate signal is exported.
Further, analog inverter includes current source and switching tube, the input of the grid of switching tube as delay circuit
The intersection point of end, source electrode ground connection, drain electrode and the output end of current source is connected to the input terminal of phase inverter, the input termination electricity of current source
Source；When switching tube is connected, the intersection point of switching tube and current source exports low level；When switching tube ends, current source is by opening
The intersection point of the drain electrode of pass pipe corresponding capacitor charging into parallel circuit, switching tube and current source exports high level.
Further, asynchronous timer circuit includes：It is corresponding with each branch of parallel circuit in inverter circuit to touch
Send out device, nor gate and with door.
On the other hand, the present invention provides a kind of the output voltage method of sampling based on AC-DC converter, this method
Including：
Sampling and holding FB signals, export feedback voltage；Feedback voltage is compared with reference voltage, the first electricity of output
Pressure；The degaussing time of FB signals is detected, the first testing result is exported；According to the first testing result to pulse width modulation controlled
Device is controlled, and controlling value is exported；According to controlling value and first voltage, the pulsewidth of adjusting pulsewidth modulated signal exports gate signal.
Further, FB signals are detected, specially；When the degaussing time being more than the front end blanking time, the first inspection
Survey result is the first level, then controlling value is the first level；When the degaussing time being less than the front end blanking time, the first testing result
For second electrical level, then controlling value is second electrical level.
The embodiment of the present invention makes the circuit in the case where exporting constant voltage, passes through pulse-width modulation PWM controller, degaussing
The collective effect of time detection circuit and timer is modulated the Gate signal opening times, realizes the circuit any
In the case of can work accurately be acquired to FB waves.
Description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this
For the those of ordinary skill of field, without creative efforts, others are can also be obtained according to these attached drawings
Attached drawing.
Fig. 1 is the structural schematic diagram of the output voltage sampling circuit in a kind of AC-DC converter in the prior art；
Fig. 2 is Fig. 1 voltage of each node or current waveform schematic diagram when output loading resistance value is larger；
Fig. 3 is Fig. 1 voltage of each node or current waveform schematic diagram when output loading resistance value is smaller；
Fig. 4 is a kind of output voltage sampling circuit structure based on AC-DC converter provided in an embodiment of the present invention
Schematic diagram；
Fig. 5 is the structural schematic diagram of Acquisition Circuit in Fig. 4；
Fig. 6 is the waveform of degaussing time detection circuit output signal and timer output signal provided in an embodiment of the present invention
Schematic diagram；
Fig. 7 is that FB signals provided in an embodiment of the present invention, degaussing time detection circuit output signal and timer output are believed
Number waveform diagram；
Fig. 8 a are a kind of specific implementation structural schematic diagram of PWM controller circuit in circuit shown in Fig. 5；
Fig. 8 b are a kind of specific implementation structural schematic diagram of analog adder circuit in Fig. 8 a；
Fig. 9 is the waveform diagram of pwm signal and opamp-output signal in circuit shown in Fig. 8 b；
Figure 10 is the specific implementation structural schematic diagram of another PWM controller circuit in circuit shown in Fig. 5；
Figure 11 is a kind of method stream of output voltage sampling based on AC-DC converter provided in an embodiment of the present invention
Cheng Tu.
Specific implementation mode
Below by drawings and examples, technical scheme of the present invention will be described in further detail.
Fig. 4 is a kind of output voltage sampling circuit structure based on AC-DC converter provided in an embodiment of the present invention
Schematic diagram.As shown in figure 4, the circuit includes：Constant-current control circuit and auxiliary winding circuit；Wherein, constant-current control circuit includes
Bridge rectifier, capacitance C1, transformer T1, power switch tube M1, rectifier diode D1, resistance R1, capacitance C2 and load RL；It is auxiliary
It includes resistance R2, resistance R3 and sample circuit 401 to help winding circuit.
Fig. 5 is the structural schematic diagram of Acquisition Circuit in Fig. 4.As shown in figure 5, the sample circuit 401 includes：Output voltage is examined
Slowdown monitoring circuit 501, error amplifier 502, pulse-width modulation PWM controller 503, degaussing time detection circuit 504 and timer 505.
Output voltage detecting circuit 501 exports feedback voltage V FB, input terminal for sampling and keeping feedback FB signals
Feedback FB signals are received, output end is connect with the in-phase input end of error amplifier 502；
Error amplifier 502 exports direct current ordinary mail for feedback voltage V FB to be compared with reference voltage Vref
Number EAout, inverting input access reference voltage Vref, and output end is connected with an input terminal of WM controllers 503,
Another input terminal of PWM controller 503 is connected with the output end of timer 505, for according to error amplifier 502
The pulse width of the direct current signal EAout adjustment pwm signals of output, output end export Gate signals；
The input terminal of degaussing time detection circuit 504 is connected with the input terminal of output voltage detecting circuit 501, output end with
The input terminal of timer 505 is connected, and for being detected to the degaussing time for feeding back FB waveforms, exports SnHOK level signals.
Further, since load is different, FB waveforms may will produce decaying concussion, when forming LEB within the degaussing time
Between section, degaussing time detection circuit 504 is detected the degaussing time of the FB waveforms.
Timer 505 is for being detected the output signal of degaussing time detection circuit 504, output control signal
Tdmg。
The course of work of circuit shown in Fig. 5 is as follows：
Output voltage detecting circuit 501 samples FB signals, detects and keep the signal, exports the voltage of FB signals
VFB, and by the voltage output to the in-phase input end of error amplifier 502, voltage VFB is compared with reference voltage Vref
Compared with output DC level signal EAout；Degaussing time detection circuit 504 carries out the detection of degaussing time to FB signals：If degaussing
Time is more than the LEB periods, and degaussing time detection circuit 504 exports high level SnHOK=1, and timer 505 exports high level
Opening time of Tdmg=1, the Gate signals triggering power switch tube M1 that PWM controller 503 exports at this time is completely by inputting
EAout is determined；If the degaussing time is less than the LEB periods, the output of degaussing time detection circuit 501 is low level SnHOK=0,
505 start-up study function of timer makes Tdmg=1 continue the tf periods, and the tf periods are determined by the internal structure of timer 505,
Can be 10-100 PWM cycle can also be 1-2mS, the unlatching of Gate signals triggering power switch tube M1 within the tf periods
Time, timer 505, which exports, after the tf periods became low level Tdmg=0, and waveform changes such as still by EAout signal decidings
Shown in Fig. 6.
The output of timer 505 becomes low level Tdmg=0, the output Gate letters of PWM controller 503 after the tf periods
The opening time of number triggering power switch tube M1 gradually increases on the basis of by EAout signal decidings, until Tdmg=1 is
Only.
Further, when the degaussing time be less than the LEB periods when, output voltage detecting circuit 501 cannot to FB signals into
Row sampling, exports SnHOK=0, and the output Tdmg=0 of timer 505 after continuing the tf periods, the pressure of PWM controller 503 makes
The opening time of Gate signals gradually lengthens, and increase to makes degaussing time long enough always, so that output voltage detecting circuit
After 501 can sample FB signals, the opening time of Gate signals is restored to the shape determined by error amplifier in loop
State, so in cycles, waveform are as shown in Figure 7.
In Tdmg=0, the scheme that the Gate signal opening times gradually increase is as follows：
Fig. 8 a are a kind of specific implementation structural schematic diagram of PWM controller circuit in circuit shown in Fig. 5.As shown in Figure 8 a,
The PWM controller circuit includes：Saw-toothed wave generator 801, comparator 802, with door 803, rest-set flip-flop 804, driver 805 and
Delay circuit 806 and simulation summation circuit 807
The in-phase input end of comparator 802 is connected to the output end of saw-toothed wave generator 801, and inverting input is connected to mould
The output end of quasi- summation circuit 807；The input terminal for simulating summation circuit 807 receives the EAout that error amplifier 502 exports,
The Tdmg that another input terminal count pick up device 505 exports,
The output end of comparator 802 is connected to the input terminal with door 803；It is connected to RS triggerings with the output end of door 803
The ends R of device 804, the ends S of rest-set flip-flop 804 are connect with other control circuits in system, the output end of rest-set flip-flop 804 respectively with
The input terminal of driver 805 is connected with the input terminal of delay circuit 806, and the output end of delay circuit 806 is connected to and door 803
The output end of another input terminal, driver 805 exports Gate signals.
Simulation summation circuit 807 is used to improve the average voltage of the EAout signals of error amplifier output, is converted into
EAout2 signals；Rest-set flip-flop 804 is used for output pwm signal；Delay circuit 806 controls the minimum opening time of Gate signals,
The turn-off time of Gate signals is determined by S end signals.Wherein, according to different control mechanisms, the generation of S end signals can be solid
It fixes time, can also be to be determined by external signal.
In one example, the specific implementation of PWM is as follows：
If the initial output state of rest-set flip-flop 804 is 0, input state Set=0, Reset=0.When its in system
When his control circuit triggering S=1, pwm signal is set to 1, saw-toothed wave generator 801 discharged into immediately minimum level and
It is started to charge up from minimum level.
When the minimum level that saw-toothed wave generator 801 is discharged is less than or equal to EAout2 level, comparator 802 exports
Low level, other circuits in control system trigger S=0, and the output signal PWM of rest-set flip-flop remains 1；When sawtooth wave occurs
When the output signal of device 801 is charged to than EAout2 high, comparator 802 exports high level, exports high level with door 803 at this time,
The ends the R input of rest-set flip-flop 804 is 1, and pwm signal is reset, PWM=0.When S is triggered 1 next time, rest-set flip-flop 804
The pwm signal of output be set to 1 again, saw-toothed wave generator 801 is discharged into minimum level and immediately again from minimum
Level starts to charge up, and the above process repeats again.That is, increasing EAout to EAout2, saw-toothed wave generator is made to be discharged
Minimum level be less than or equal to EAout2 level when, the width of pwm signal will increase.Wherein, S end signals periodically trigger
Rest-set flip-flop 804, the above process periodically repeats, and determines the width of pwm signal in each period, and should be delayed electricity in the process
Road 806 does not work.
As PWM=0, no matter the output level of comparator 802 is 1 or 0, and the output with door 803 is touched for low level RS
The ends the R input 0 for sending out device 804, keeps PWM=0 at this time.Later as S=1, PWM is turned to 1 from 0, and delay circuit 806 can be in S
It is 0 that output is kept in a period (delay time) after=1.
Within above-mentioned delay time, if the output level of comparator 802 exports low level within above-mentioned delay time,
So delay circuit does not influence the course of work of entire PWM；If the output of comparator 802 is high level, that is to say, that
The output ratio EAout2 high of saw-toothed wave generator 801, then the R=0 of triggering rest-set flip-flop 804, PWM output are high level.It crosses
After above-mentioned delay time, the output level of delay circuit is high level, the R=1 of rest-set flip-flop 804, and PWM is just set at this time
Position is zero.Above-mentioned delay time determines the minimum opening time of PWM, and therefore, delay circuit 806 controls the minimum of Gate signals
Opening time.
Fig. 8 b are a kind of specific implementation structural schematic diagram of simulation summation circuit in Fig. 8 a, and as shown in Figure 8 b, which adds
Method circuit 807 includes operational amplifier op1, resistance R1, variable current source circuit and asynchronous timer circuit.It wherein, can power transformation
Every branch is composed in series by a switch with a current source in current source circuit.
The Tdmg of an input terminal count pick up device 505 output of asynchronous timer circuit, another input terminal receive RS triggerings
The pwm signal that device 804 exports, the control signal of output end output control variable current source circuit；The one of variable current source circuit
End is grounded by current source, and the other end is connected by switching with one end of resistance, and the other end of resistance R1 is connected to operation amplifier
The output end of device op1；The in-phase input end of operational amplifier op1 receives EAout signals, and inverting input receives resistance R1 and can
The node voltage of power transformation current source circuit exports EAout2 signals.
Variable current source circuit includes current source I0-I4 and switch SW0-SW4, in the parallel circuit in every branch by
One switch is composed in series with a current source, and one end of switch is connected to one end of resistance R1, and the other end is source-series with electric current
After be grounded.Wherein, current source I0-I4 is arranged according to certain coding mode, such as is arranged according to 8421 yards, i.e. I4=2*
I3=4*I2=8*I1=16*I0.
Asynchronous timer circuit includes d type flip flop DFF1-DFF5 or non-corresponding with each branch in variable current source circuit
Door NOR and with door AND；The reversed-phase output of DFF1-DFF5 is connected to itself input terminal, and the reversed-phase output of DFF1-DFF4 connects
It is connected to the clock signal input terminal of next stage, is switched in the in-phase output end output control variable current source circuit of DFF1-DFF5
The control signal of SW0-SW4, it is that high level switch is closed such as to control signal, and control signal is that low level switch disconnects, DFF1-
The set end R series connection of DFF5, for receiving Tdmg signals.The output of DFF1-DFF5 in-phase output ends is received with the input terminal of door AND
Control signal, output end is connected to an input terminal of nor gate NOR, and another input terminal of nor gate NOR receives RS triggerings
The pwm signal that device 804 exports, output end are connected to the clock signal input terminal of DFF1.Wherein, clock signal input terminal input is high
Level is effective.
The course of work for simulating summation circuit 807 will be discussed in detail in one example below.
The node of EAout and resistance R1 and variable current source circuit that operational amplifier op1 exports error amplifier 502
Voltage is overlapped processing, exports EAout2.
As Tdmg=1, show that degaussing time long enough FB signals are correctly sampled, at this time the R of asynchronous timer circuit
End is in high level, and DFF1-DFF5 is reset, and asynchronous timer circuit does not work, and in-phase output end exports low level control
Signal, the switch SW0-SW4 for controlling variable current source circuit are disconnected, and no electric current is generated by no pressure drop on resistance R1, at this time
EAout is equal to EAout2.
As Tdmg=0, show that degaussing time shorter FB signals cannot be sampled correctly, at this time asynchronous timer circuit
The ends R are in low level, and the asynchronous timer of DFF1-DFF5 compositions is started to work.The clock signal of the asynchronous timer circuit is
Pwm signal, and failing edge is effective, i.e., often passes through the failing edge of a PWM, the pressure drop on resistance R1 can increase.Due to can power transformation
Current source I0-I4 being ranked sequentially according to I4=2*I3=4*I2=8*I1=16*I0 in current source circuit, therefore work as asynchronous timing
The output of DFF1-DFF5 is by 00000 to 11111 change procedures, the average voltage of EAout2 constantly increases in device circuit.When
When all high level of control signal of DFF1-DFF5 outputs, i.e., when in-phase output end output is 1, no matter pwm signal at this time
For high level or low level, low level will be exported after nor gate NOR processing, asynchronous timer circuit overflows, at this time DFF1-
The control signal of the output of DFF5 keeps all high level, and when Tdmg=1, DFF1-DFF5 is reset, and is repeated above-mentioned
The course of work.
Fig. 9 is the waveform diagram of pwm signal and opamp-output signal in circuit shown in Fig. 8 b.As shown in figure 9,
The failing edge of pwm signal is effective, and horizontal dotted line represents the EAout signals of operational amplifier op1 outputs, intersecting therewith solid line generation
Table EAout2 signals.It carves at the beginning, i.e. A points, EAout is identical as the voltage waveform of EAout2；Within the A-B moment, pwm signal
Failing edge come for the first time interim, the voltage waveform of EAout2 increases certain amplitude on the basis of the voltage waveform of EAout, it
The failing edge of each pwm signal arrives afterwards, and the voltage waveform of EAout2 all can be on the basis of previous moment EAout2 voltage waveforms
It is upper to increase certain amplitude, wherein the size of the amplitude is determined by the pressure drop on resistance R1；From the B moment, the voltage wave of EAout2
Shape remains unchanged, and asynchronous timer circuit overflows at this time, and the pressure drop on resistance R1 is its attainable maximum value.
Summation circuit 807 is simulated by variable current source circuit and asynchronous timer circuit collective effect, pressure makes error
The average voltage of the EAout of amplifier circuit output is increased to EAout2, and EAout2 increases to always asynchronous timer circuit and overflows
Go out, when the pressure drop on resistance R1 is its maximum value, the cumulative EAout2 of operational amplifier op1 output valves also reaches its maximum value.
During EAout2 increases to its maximum value from EAout, the pulse width of PWM is being stepped up, i.e. Gate signals are opened
Time increase is opened, the width of degaussing time is caused also to be stepped up accordingly.In this course, if the degaussing time increases
To when can meet the sampling Tdmg=1 to FB signals, asynchronous counter is reset, and all current sources are stopped, resistance R1
On pressure drop be zero, the output voltage of operational amplifier op1 is restored to its input voltage EAout.Therefore, the pressure drop on resistance R1
The maximum value that can reach determines the degree that system can be adjusted, according to the difference of application environment, such as input voltage range,
Output voltage, output current scope and transformer turn ratio etc. need the digit, the resistance value of R1 and the electricity that adjust asynchronous counter
The size of stream source I0-I4.When Tdmg signals are again at low level, asynchronous timer circuit triggers variable current source electricity again
Road with work, so in cycles.
Figure 10 is the specific implementation structural schematic diagram of another PWM controller circuit in circuit shown in Fig. 5.Such as Figure 10 institutes
Show, which includes：Saw-toothed wave generator 1001, comparator 1002 and door 1003, rest-set flip-flop 1004, driving
Device 1005 and delay circuit 1006；Delay circuit 1006 includes asynchronous timer circuit and inverter circuit 1060.Wherein, reverse phase
Device circuit 1060 is used to convey pwm signal to door 1003.
Saw-toothed wave generator 1001, comparator 1002, the connection side with door 1003, rest-set flip-flop 1004 and driver 1005
Formula is same as above with the course of work, no longer superfluous here to tell.
The Tdmg of one input terminal count pick up device 505 of asynchronous timer circuit output, another input terminal receive rest-set flip-flop
The pwm signal of 1004 outputs, the control signal of output end output control inverter circuit 1060；
Inverter circuit 1060 is including phase inverter 1061, analog inverter and by capacitance C0-C4 and switch SW0-SW4 groups
At parallel circuit.Wherein, analog inverter includes that current source 1062 and switching tube 1063 are needed for controlling delay time
Illustrate, the minimum value of delay time or initial value the parasitic capacitance of itself can be determined by current source 1062 in the present embodiment
It is fixed, it can also be determined by capacitance in parallel.
Every branch includes a switch and a capacitance in the parallel circuit, and one end of switch is by capacity earth, separately
One end is connected to the input terminal of phase inverter 1061.The output end of phase inverter 1061 is connected to an input terminal with door 1003, mould
The grid of switching tube 1063 in quasi- phase inverter is connected to the output end of rest-set flip-flop 1004, and source electrode is connected to ground, drain electrode and electric current
The intersection of the output end in source 1062, the intersection point are connected to the input terminal of phase inverter 1061, and the input of current source 1062 is connected to electricity
Source VDD, wherein the course of work of analog inverter is：
When the pwm signal that switching tube 1063 receives is high level, be connected between the drain electrode of switching tube 1063 and source electrode, due to
The conducting resistance very little of switching tube 1063, therefore its drain electrode output low level, simultaneously because 1063 conducting resistance very little, right
Quickly, therefore the drain electrode of switching tube 1063 is turned to the low level time from high level and can neglect the velocity of discharge of capacitance C0-C4
Slightly disregard；
When the pwm signal that switching tube 1063 receives is low level, end between the drain electrode and source electrode of switching tube 1063, because
For this current source 1062 by the drain electrode of switching tube 1063 to capacitor charging, drain electrode exports high level.Current source 1062 is filled to capacitance
Electricity needs a period of time, reaches the trigging signal of phase inverter 1061 after one section of delay time, phase inverter 1061 to incoming level into
Row overturning output.
The control signal of the in-phase output end output of DFF1-DFF5 controls inverter circuit 1060 in asynchronous timer circuit
The disconnection of middle switch SW0-SW4 and closure；The connection type of asynchronous timer circuit and the course of work are same as above, herein not
It goes to live in the household of one's in-laws on getting married and tells again.
The course of work of delay circuit 1006 is as follows：
As Tdmg=0, asynchronous timer circuit normal work exports the level signal from 00000 to 11111, control
Switch SW0-SW4 in inverter circuit；Switching tube 1063 send the pwm signal that rest-set flip-flop 1004 exports in inverter circuit
To the input terminal of phase inverter 1061, current source 1062 carries out the capacitance that the place branch road of closure is switched in parallel circuit at this time
It charges, the capacitance voltage being electrically charged in charging process increases, when the voltage of the parallel circuit in inverter circuit reaches overturning electricity
Usually, such as 1/2VDD, the level that phase inverter 1061 is inputted signal negates, and export to door 1003；
Delay circuit changes delay time by asynchronous timer and inverter circuit 1060, so that the arteries and veins of pwm signal
Width increases, i.e. the opening time of Gate signals increases, and the width of degaussing time is caused also to be stepped up accordingly.In this mistake
Cheng Zhong, if the degaussing time increases to Tdmg=1 when can meet the sampling to FB signals, asynchronous counter is reset, capacitance
C0-C4 is disconnected, and the delay time of analog inverter is restored to minimum value or initial value.Therefore, the time length of capacitor charging
The degree that the system of determining can be adjusted, according to the difference of application environment, such as input voltage range, output voltage, output current
Range and transformer turn ratio etc. need digit, the capacitance of capacitance C0-C4 and the arrangement mode and electricity that adjust asynchronous counter
The size in stream source.When Tdmg signals are again at low level, asynchronous timer circuit triggers inverter circuit and carries out work again
Make, so in cycles.
Figure 11 is a kind of method stream of output voltage sampling based on AC-DC converter provided in an embodiment of the present invention
Cheng Tu.Since FB signals are directly proportional to output voltage, to which output voltage can be obtained, therefore as shown in figure 11, the method for sampling
Including：
Step S111, FB signals are received, FB signals are sampled, output voltage VFB；
Step S112, voltage VFB is compared with reference voltage, exports EAout；
Step S113, FB signals are received, the degaussing time of FB signals is detected, export SnHOK；
Specifically, due to circuit load difference, FB waveforms may will produce decaying concussion, and LEB is formed within the degaussing time
Period, degaussing time detection circuit are detected the degaussing time of the FB waveforms.
Step S114, according to the signal level of SnHOK, output control signal；
Specifically, when the degaussing time being more than the LEB periods, SnHOK is high level, then the level for controlling signal is high electricity
It is flat；When the degaussing time being less than the LEB periods, SnHOK is low level, then the level for controlling signal is low level.
Step S115, according to control signal and EAout, the pulsewidth of pwm signal is adjusted, exports Gate signals.
The embodiment of the present invention makes the circuit in the case where exporting constant voltage, passes through pulse-width modulation PWM controller, degaussing
The collective effect of time detection circuit and timer is modulated the Gate signal opening times, realizes the circuit any
In the case of can work accurately be acquired to FB waves.
Above-described specific implementation mode has carried out further the purpose of the present invention, technical solution and advantageous effect
It is described in detail, it should be understood that the foregoing is merely the specific implementation mode of the present invention, is not intended to limit the present invention
Protection domain, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should all include
Within protection scope of the present invention.
Claims (10)
1. a kind of output voltage sampling circuit based on AC-DC converter, the circuit include：Output voltage detecting circuit
(501), error amplifier (502), which is characterized in that PDM keyer (503), degaussing time detection circuit (504) and
Timer (505),
The output voltage detecting circuit (501) exports feedback voltage for sampling and keeping output voltage feedback signal
(VFB)；
The error amplifier (502) exports for the feedback voltage (VFB) and reference voltage (Vref) to be compared
First voltage (EAout)；
The degaussing time detection circuit (504), is detected for the degaussing time to the output voltage feedback signal, defeated
Go out the first testing result (SnHOK)；
The timer (505), for being controlled to the PDM keyer (503) according to first testing result
System, output controlling value (Tdmg)；It is less than front end blanking time section, the controlling value of timer (505) output when the degaussing time
(Tdmg) (tf) period that is delayed will persistently be made a reservation for；
The PDM keyer (503) includes simulation accumulator circuit (807)；The simulation accumulator circuit (807)
One input terminal receives the first voltage (EAout) of error amplifier (502) output, and another input terminal receives the meter
When device (505) export the controlling value (Tdmg), output end export second voltage (EAout2)；
The PDM keyer (503), for according to the controlling value (Tdmg) and the first voltage, adjusting pulsewidth tune
The pulsewidth of signal processed；
The modulated signal of the PDM keyer (503) is modulated according to the second voltage (EAout2), is exported
Gate signal (Gate).
2. circuit according to claim 1, which is characterized in that the degaussing time detection circuit (504) is to the output
Voltage feedback signal is detected, specially；
When the degaussing time being more than the front end blanking time, described the first of degaussing time detection circuit (504) output
Testing result (SnHOK) is the first level, then the controlling value (Tdmg) of timer (505) output is first electricity
It is flat；When the degaussing time being less than the front end blanking time, described the of the degaussing time detection circuit (504) output
One testing result (SnHOK) is second electrical level, then the controlling value (Tdmg) of timer (505) output is described second
Level.
3. circuit according to claim 1, which is characterized in that the simulation accumulator circuit includes：Operational amplifier, electricity
Resistance, variable current source circuit and asynchronous timer circuit；Wherein, every branch is opened by one in the variable current source circuit
Pass is composed in series with a current source；
One input terminal of the asynchronous timer circuit receives the controlling value (Tdmg) of timer (505) output, separately
One input terminal receives the modulated signal, and output end output controls the control signal of the variable current source circuit；It is described variable
The switch of every branch road is controlled by the control signal of the asynchronous timer circuit output, institute in current source circuit
The one end for stating variable current source circuit is grounded by the current source, and the other end of the variable current source circuit is opened by described
Pass is connected with one end of the resistance；The other end of the resistance is connected with the output end of the operational amplifier；The operation
One input terminal of amplifier receives the first voltage (EAout), and another input terminal receives the resistance and the variable current source
The node voltage of circuit, output end export the second voltage (EAout2).
4. circuit according to claim 3, which is characterized in that the asynchronous timer circuit includes：With it is described can power transformation
The corresponding trigger of every branch in current source circuit, nor gate and with door.
5. circuit according to claim 3, which is characterized in that the electricity of every branch in the variable current source circuit
Stream source is arranged by certain coding mode.
6. circuit according to claim 1, which is characterized in that the PDM keyer (503) includes delay circuit
(1006)；The delay circuit (1006) includes inverter circuit (1060) and asynchronous timer circuit；
The inverter circuit includes：Analog inverter, phase inverter (1061) and the parallel circuit being made of with switch capacitance；
Wherein, the analog inverter is for controlling delay time；Every branch includes a switch and one in the parallel circuit
Capacitance, one end of the parallel circuit are connected to the input terminal of the phase inverter by described switch, the parallel circuit it is another
One end passes through the capacity earth；Output end of the output end of the phase inverter as the delay circuit (1006)；The mould
Input terminal of the input terminal of quasi- phase inverter as the delay circuit (1006), the output end of the analog inverter are connected to institute
State the input terminal of phase inverter；One input terminal of asynchronous timer circuit receives the control of timer (505) output
Value, output control signal, the break-make for controlling every branch in the parallel circuit；The inverter circuit (1060) passes through
The charging time of capacitance described in the parallel circuit controls the delay time of the delay circuit (1006)；
By controlling the delay time of the delay circuit (1006), the modulation to the PDM keyer (503)
Signal is modulated, and exports the gate signal (Gate).
7. circuit according to claim 6, which is characterized in that the analog inverter includes current source (1062) and switch
It manages (1063),
Input terminal of the grid of the switching tube (1063) as the delay circuit (1006), source electrode ground connection, drain electrode with it is described
The intersection point of the output end of current source (1062) is connected to the input terminal of the phase inverter (1061), the current source (1062) it is defeated
Enter termination power；
When the switching tube (1063) are connected, the switching tube (1063) and the intersection point of the current source (1062) export low electricity
It is flat；When the switching tube (1063) end, the current source (1062) is by the drain electrode of the switching tube (1063) to described
The corresponding capacitor charging in parallel circuit, the high electricity of intersection point output of the switching tube (1063) and the current source (1062)
It is flat.
8. circuit according to claim 6, which is characterized in that the asynchronous timer circuit includes：With the phase inverter
The corresponding trigger of each branch of parallel circuit described in circuit, nor gate and with door.
9. a kind of output voltage method of sampling based on AC-DC converter is applied to circuit as described in claim 1,
The method includes：
Sampling and holding output voltage feedback signal, export feedback voltage；
The feedback voltage is compared with reference voltage, exports first voltage；
The degaussing time of the output voltage feedback signal is detected, the first testing result is exported；
According to first testing result, controlling value is exported；
According to the controlling value and the first voltage, the pulsewidth of adjusting pulsewidth modulated signal exports gate signal.
10. according to the method described in claim 9, it is characterized in that, described be detected the output voltage feedback signal,
Specially；
When the degaussing time being more than the front end blanking time, first testing result is the first level, then the controlling value
For first level；When the degaussing time being less than the front end blanking time, first testing result is the second electricity
Flat, then the controlling value is the second electrical level.
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