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CN105428337B - 半导体封装及其制造方法 - Google Patents

半导体封装及其制造方法 Download PDF

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Publication number
CN105428337B
CN105428337B CN201510573810.0A CN201510573810A CN105428337B CN 105428337 B CN105428337 B CN 105428337B CN 201510573810 A CN201510573810 A CN 201510573810A CN 105428337 B CN105428337 B CN 105428337B
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China
Prior art keywords
semiconductor chip
semiconductor
thermal component
chip
top surface
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CN201510573810.0A
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CN105428337A (zh
Inventor
许埈荣
赵汊济
赵泰济
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN105428337A publication Critical patent/CN105428337A/zh
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Abstract

本公开提供了半导体封装及其制造方法。实施例包括一种半导体封装，该半导体封装包括：基板；第一半导体芯片，安装在基板上；第二半导体芯片，安装在第一半导体芯片的顶表面上；连接凸块，设置在第一和第二半导体芯片之间以将第二半导体芯片电连接到第一半导体芯片；以及第一散热部件，在第一和第二半导体芯片之间设置在第一半导体芯片的顶表面上且与第二半导体芯片的底表面分隔开。

Description

半导体封装及其制造方法
技术领域
各实施例涉及半导体。更具体地，各实施例涉及具有贯穿通路(through-via)的多芯片半导体封装以及制造该半导体封装的方法。
背景技术
轻、小、快、高性能且低成本的电子产品可以被发展。集成电路芯片可以通过各种封装技术之一来包封，以形成适于在电子产品中使用的半导体封装。已经进行了各种研究来改善半导体封装的性能。特别地，代替传统的引线接合技术，已经开发了硅通孔(TSV)技术来改善半导体封装的性能。
发明内容
一个实施例包括一种半导体封装，该半导体封装包括：基板；第一半导体芯片，安装在基板上；第二半导体芯片，安装在第一半导体芯片的顶表面上；连接凸块，设置在第一和第二半导体芯片之间以将第二半导体芯片电连接到第一半导体芯片；以及第一散热部件，在第一和第二半导体芯片之间设置在第一半导体芯片的顶表面上且与第二半导体芯片的底表面分隔开。
一个实施例包括一种半导体封装，该半导体封装包括：基板；第一半导体芯片，设置在基板上；第二半导体芯片，设置在第一半导体芯片上；连接凸块，设置在第一和第二半导体芯片之间以将第二半导体芯片电连接到第一半导体芯片；第一焊盘，设置在第一半导体芯片与连接凸块之间；以及第一散热部件，在第一和第二半导体芯片之间设置在第一半导体芯片的顶表面上且与第二半导体芯片的底表面分隔开，其中第一散热部件包括第二焊盘。
一个实施例包括一种制造半导体封装的方法，该方法包括：制备第一半导体芯片，该第一半导体芯片包括设置在第一半导体芯片的顶表面上的图案化的导电层；将第一半导体芯片安装在基板上；将第二半导体芯片安装在第一半导体芯片的顶表面上，第二半导体芯片通过连接凸块电连接到第一半导体芯片；以及形成设置在第一半导体芯片的顶表面上且与第二半导体芯片的底表面分隔开的散热部件。
附图说明
考虑到附图和附随的详细说明，各实施例将变得更加明显。
图1A是示出根据实施例的半导体封装的平面图；
图1B是沿着图1A的线A-B截取的截面图；
图1C是图1B的区域“Z”的放大图；
图2A是示出根据实施例的第一散热部件的示例的放大截面图；
图2B是示出根据实施例的第一散热部件另一个示例的放大截面图；
图3A是示出根据实施例的第一散热部件的截面图；
图3B是示出根据实施例的第一散热部件的截面图；
图4A是示出根据实施例的第一散热部件的平面图；
图4B是示出根据实施例的第一散热部件的平面图；
图5是示出根据实施例的半导体封装的截面图；
图6A、6B和6D至6I是示出制造根据各种实施例的半导体封装的方法的截面图；
图6C是对应于图6B的平面图；
图7是示出包括根据某些实施例的半导体封装的封装模块的示例的示意图；
图8是示出包括根据某些实施例的半导体封装的电子系统的示例的示意性方框图；以及
图9是示出包括根据某些实施例的半导体封装的存储卡的示例的示意性方框图。
具体实施方式
现在将在下面参照附图更全面地描述各实施例，附图中示出了特定的实施例。优点和特征以及实现它们的方法将从以下参照附图更详细地描述的实施例变得明显。然而，应当指出，实施例不限于下面的特定实施例，而是可以实施为各种形式。因此，这些实施例仅被提供来向本领域技术人员公开各构思。在附图中，实施例不限于这里提供的具体示例，并且为了清晰可以被夸大。
这里所用的术语仅是为了描述特定实施例的目的，而不意在进行限制。如这里所用的，单数术语“一”、“一个”和“该”旨在也包括复数形式，除非上下文另外清楚地表述。如这里所用的，术语“和/或”包括一个或多个相关所列项目的任何和所有的组合。将理解，当一元件被称为“连接”或“联接”到另一个元件时，它可以直接连接或联接到该另一个元件，或者可以存在插入的元件。
类似地，将理解，当一元件诸如层、区域或基板被称为“在”另一元件“上”时，它可以直接在该另一个元件上，或者可以存在插入的元件。相反，术语“直接”表示没有插入的元件。还将理解，术语“包括”和/或“包含”，当在这里使用时，指定所述特征、整体、步骤、操作、元件和/或部件的存在，但是并不排除一个或多个其它特征、整体、步骤、操作、元件、部件和/或其组合的存在或添加。
此外，详细描述中的实施例将用作为理想示范性视图的截面图来描述。因此，示范性视图的形状可以根据制造技术和/或可允许的误差来修改。因此，实施例不限于示范性视图中所示的特定形状，而是可以包括根据制造工艺可产生的其它形状。附图中例示的区域具有一般的性质，并用于示出元件的特定形状。因此，这不应被解释为限制实施例的范围。
还将理解的是，尽管这里可以使用术语第一、第二、第三等来描述各种元件，但是这些元件不应受到这些术语限制。这些术语仅用于将一个元件与另一个元件区别开。因此，某些实施例中的第一元件可以在另一些实施例中被称为第二元件而没有脱离本发明的教导。这里说明并示出的本发明构思的各方面的示范性实施例包括它们的互补对应物。相同的附图标记或相同的参考指示符在整个说明书中表示相同的元件。
而且，这里参照作为理想化示范性图示的截面图和/或平面图来描述实施例。因此，由例如制造技术和/或公差引起的图示的形状变化将是可预期的。因此，实施例不应被解释为限于这里示出的区域的形状，而是包括由例如制造导致的形状偏差。例如，示出为矩形的蚀刻区将通常具有圆化或弯曲的特征。因此，附图所示的区域在本质上是示意性的，它们的形状不旨在示出器件的区域的真实形状，并且不旨在限制示例实施例的范围。
根据这里描述的各个实施例的器件以及形成器件的方法可以被实施为微电子器件诸如集成电路，其中根据这里描述的各个实施例的一个或多个器件可以被集成在相同的微电子器件中。因此，在该微电子器件中，这里所示的截面图可以在不必垂直的两个不同方向上重复。因此，实施根据这里描述的各个实施例的器件的该微电子器件的平面图可以包括成阵列和/或二维图案的器件，取决于该微电子器件的功能。
根据这里描述的各个实施例的器件可以根据该微电子器件的功能而散布在其它的器件当中。而且，根据这里描述的各个实施例的微电子器件可以在第三方向上重复以提供三维的集成电路，该第三方向可以垂直于所述两个不同的方向。
因此，这里示出的截面图提供对根据这里描述的各个实施例的多个器件的支持，该多个器件在平面图中沿两个不同的方向和/或在透视图中在三个不同的方向上延伸。例如，当单个有源区在器件/结构的截面图中示出时，该器件/结构可以包括其上的多个有源区和晶体管结构(或存储单元结构、栅极结构等，根据情况需要)，如将由该器件/结构的平面图所示出的。
图1A是示出根据实施例的半导体封装的平面图。图1B是是沿着图1A的线A-B截取的截面图。图1C是图1B的区域“Z”的放大图。参照图1A和1B，半导体封装1可以包括基板100和多个半导体芯片200、300和400。基板100可以是包括电路图案的印刷电路板(PCB)或其上可安装半导体芯片的其它基板。在另一些实施例中，基板100可以包括半导体芯片。外部端子101可以设置在基板100的底表面上。外部端子101可以包括导电材料并可以具有焊球形状。基板100可以通过外部端子101电连接到外部装置(未示出)。
第一半导体芯片200可以通过倒装芯片安装技术安装在基板100上。第一半导体芯片200可以通过互连部件150电连接到基板100。互连部件150可以设置在基板100和第一半导体芯片200之间。第一半导体芯片200可以包括硅材料或者其上可形成半导体器件的其它材料。第一绝缘图案510可以提供在基板100和第一半导体芯片200之间，并可以填充互连部件150之间的空间。第一绝缘图案510可以包括绝缘的聚合物。
第一半导体芯片200可以包括第一电路图案层210和第一贯穿通路220。第一电路图案层210可以设置为邻近于第一半导体芯片200的底表面200b并可以电连接到互连部件150。第一电路图案层210可以包括集成电路，诸如存储电路、逻辑电路或其组合；然而，第一电路图案层210不限于这样的电路。第一半导体芯片200的底表面200b可以用作有源表面，并且第一半导体芯片200的顶表面200a可以用作非有源表面。第一贯穿通路220可以穿透第一半导体芯片200并可以电连接到第一电路图案层210。在某些实施例中，多个第一贯穿通路220可以存在于第一半导体芯片200中。
第二半导体芯片300可以安装在第一半导体芯片200的顶表面200a上。例如，第二半导体芯片300可以通过第一连接焊盘231和第一连接凸块233电连接到第一半导体芯片200。第一连接凸块233可以包括导电材料(例如，金属)。第二绝缘图案520可以提供在第一半导体芯片200和第二半导体芯片300之间。
第二半导体芯片300可以包括第二电路图案层310和第二贯穿通路320。第二电路图案层310可以设置为邻近于第二半导体芯片310的底表面300b。第一导电焊盘313可以设置在第二半导体芯片300的底表面300b上。第一导电焊盘313可以连接到第一连接凸块233。在某些实施例中，第二半导体芯片300可以包括硅材料或者其上可形成半导体器件的其它材料。
第一连接焊盘231可以设置在第一半导体芯片200的顶表面200a上并可以电连接到第一贯穿通路220。第一连接焊盘231可以包括各种金属或导电材料诸如铜、铝、镍等中的至少一种。
第一对准标记251可以设置在第一半导体芯片200的顶表面200a上。在某些实施例中，第一对准标记251可以设置为邻近于第一半导体芯片200的顶表面200a的角落，如图1A所示。第一对准标记251可以与第一连接焊盘231横向地间隔开。第一对准标记251可以包括与第一连接焊盘231相同或类似的材料。例如，第一对准标记251可以包括金属或导电材料诸如铜、铝、镍等中的至少一种。第一对准标记251的形状和位置可以与所示的特定形状和位置不同。
第一散热部件240可以设置在第一半导体芯片200的顶表面200a上。第一散热部件240可以与第二半导体芯片300的底表面间隔开。第一散热部件240可以包括第一散热焊盘241和第一散热焊盘243。第一散热部件240可以与第一连接焊盘231和第一对准标记251横向地间隔开。第一散热焊盘241可以包括与第一连接焊盘231相同的材料。例如，第一散热焊盘241可以包括金属或导热材料诸如铜、铝、镍等中的至少一种。第一散热部件240可以设置为不与第一导电焊盘313垂直交叠。
第一半导体芯片200可以包括提供在第一电路图案层210中的第一热源215。当第一半导体芯片200运行时，从第一热源215产生的热可以朝向第一半导体芯片200的顶表面200a传递。第一热源215可以包括第一集成电路。第一热源215可以包括知识产权(IP，intellectual property)模块，例如中央处理器(CPU)、存储器接口单元、通用串行总线(USB)等。IP模块可以包括硬件模块、软件模块或这样的模块的组合，配置为执行半导体集成电路的功能。在某些实施例中，第一热源215可以设置在第一半导体芯片200的边缘区域中或与其相邻，如图1A所示。然而，第一热源215的平面位置不限于所示的。在另一些实施例中，第一热源215的平面位置可以根据第一半导体芯片200的电路组成而不同。
第一散热部件240可以包括热膨胀系数(CTE)大于第一半导体芯片200的材料(例如，金属)。从第一热源215产生的热可以通过第一半导体芯片200快速且容易地传递到第一散热部件240，所以热可以更均匀地分布在第一半导体芯片200中。如果热集中在第一半导体芯片200中的第一热源215中，则第一半导体芯片200的集成电路的可靠性会变坏。然而，因为半导体封装1包括第一散热部件240，所以可以改善半导体封装1的可靠性。
仍参照图1A和1B，当从平面图观看时，第一散热部件240可以与第一热源215交叠。在另一些实施例中，第一散热部件240可以设置为邻近于第一热源215。因此，从第一热源215产生的热可以通过第二半导体芯片300更迅速地传递。
参照图1C，第二电路图案层310可以包括钝化层316、第一和第二层间绝缘层317和318、第二集成电路311以及互连312。钝化层316可以设置在第二半导体芯片300的底表面300b上并可以暴露第一导电焊盘313。钝化层316可以包括绝缘材料。第一和第二层间绝缘层317和318的每个可以包括硅氧化物层、硅氮化物层、硅氮氧化物层、低k电介质层等中的至少一个。第二集成电路311可以包括逻辑电路、存储电路、其组合、或者其它类型的电路或电路组合。第一导电焊盘313可以设置在第二半导体芯片300的底表面300b上并可以与第一连接凸块233接触。第一导电焊盘313可以通过互连312电连接到第二集成电路311和第二贯穿通路320。互连312可以包括多个导电层和多个接触插塞。在另一些实施例中，第一导电焊盘313可以通过一种或多种其它不同的方法电连接到第二集成电路311和第二贯穿通路320。
将参照图2A和2B描述第一散热部件的其它实施例。在下文，为了说明的容易和方便的目的，将省略或简要提及对如上所述的相同元件的描述。
参照图2A和1B，第一散热部件240可以包括第一散热焊盘241、第一散热凸块243和上散热焊盘245。上散热焊盘245可以设置在第二半导体芯片300的底表面300b上。当第一半导体芯片200运行时，从第一热源215产生的热可以通过第一半导体芯片200传递到第一散热部件240。第一散热部件240可以包括具有与第二半导体芯片300的CTE不同的CTE的材料。例如，第二半导体芯片300可以包括硅材料，并且第一散热部件240可以包括金属材料。第一散热部件240的体积可以根据期望从第一热源215传递的热而变化。随着第一半导体芯片200反复地运行，第一散热部件240会反复地收缩和膨胀。第一半导体芯片200的体积变化率可以大于第二半导体芯片300的体积变化率。由于第一散热部件240和第二半导体芯片300的CTE之间的差异，裂缝C会邻近第一散热部件240形成在第二半导体芯片300的底表面300b处。邻近第一散热部件240的互连312和/或第二集成电路311可能被裂缝C损坏。
参照图2B，第二集成电路311可以与由第一散热部件240限定的排除区域(keepout zone,KOZ)分隔开。排除区域KOZ可以是其中由于第一散热部件240和第二半导体芯片300之间的CTE差异而可能产生裂缝C的区域。排除区域KOZ可以邻近于第二半导体芯片300的底表面300b。结果，尽管发生裂缝C，但是第二集成电路311也可以不被损坏。然而，第二集成电路311的位置会受到第一散热部件240的位置限制，所以会降低第二集成电路311的位置的自由度。
再次参照图1C，第一散热部件240可以与第二半导体芯片300的底表面300b分隔开。例如，第一散热凸块243的高度H2可以低于或小于第一连接凸块233的高度H1。第一半导体芯片200的顶表面200a和第二半导体芯片300的底表面300b之间的距离D可以大于第一散热部件240的高度，例如第一散热焊盘241的厚度T2和第二散热凸块243的高度H2之和。第一散热部件240可以与第二半导体芯片300的底表面300b分隔开，所以第二绝缘图案520可以提供在第一散热部件240和第二半导体芯片300之间。从第一半导体芯片200的第一热源215产生的热不会传递到第二半导体芯片300，因此，图2A和2B的裂缝C不会形成在第二半导体芯片300中。排除区域KOZ可以不被限定在第二半导体芯片300的底表面300b处。根据某些实施例，第二半导体芯片300的第二集成电路311不会被第一散热部件240损坏。此外，第二集成电路311的位置可以不受第一散热部件240的位置限制。第二集成电路311可以邻近于第一散热部件240。例如，当从平面图观看时，第二集成电路311可以与第一散热部件240交叠。因此，第二集成电路311的位置可以被不同地修改。
第一散热焊盘241的厚度T2可以实质上等于第一连接焊盘231的厚度T1和第一对准标记251的厚度T3。这里，实质上相等的厚度的范围可以包括当焊盘241和231以及第一对准标记251通过相同的工艺形成时可能导致的厚度公差范围。
第一连接凸块233可以与分别形成在第一半导体芯片200的顶表面200a和第二半导体芯片300的底表面300b上的第一连接焊盘231和第一导电焊盘313接触。第一连接凸块233和第一散热凸块243可以包括金属材料。第一连接凸块233中包括的材料可以与第一散热凸块243中包括的材料相同或不同。
图3A和3B是示出根据另一些实施例的第一散热部件的放大截面图。在下文，为了说明的容易和方便的目的，将省略或简要提及对如上所述的相同元件的描述。
参照图1B、3A和3B，第一散热部件240可以在第一半导体芯片200的顶表面200a上与第一连接焊盘231横向地分隔开。第一散热部件240的高度可以低于或小于第一连接凸块233的高度，所以第一散热部件240可以与第二半导体芯片300的底表面300b分隔开。换言之，第一散热部件240的顶端可以低于第一连接凸块233的顶端。第一散热部件240的截面可以具有各种形状中的一种。在某些实施例中，如图3A所示，第一散热部件240可以包括图1B的第一散热凸块243，但是可以不包括图1B的第一散热焊盘241。第一散热部件240可以具有圆形的截面。在另一些实施例中，第一散热部件240可以具有矩形截面，如图3B所示。尽管圆形和矩形的截面已经用作示例，但是第一散热部件240可以具有其它的形状。第一散热部件240的厚度可以与第一连接焊盘231的厚度不同。
图4A和4B是示出根据另一些实施例的第一散热部件的平面图。在下文，为了说明的容易和方便的目的，将省略或简要提及对如上所述的相同元件的描述。
参照图4A和4B，第一散热部件240可以设置在第一半导体芯片200上。第一散热部件240可以与第一对准标记251和第一连接焊盘231分隔开。当从平面图观看时，第一散热部件240可以交叠或邻近第一热源215。第一散热部件240的位置可以根据第一热源215的位置改变。第一散热部件240可以具有各种形状中的一种。可以提供一个或多个第一散热部件240，每个具有相同、类似或不同的形状。如图4A所示，多个第一热源215可以存在于第一半导体芯片200中。在某些实施例中，第一散热部件240可以交叠两个或多个第一热源215。第一散热部件240的平面面积可以大于第一热源215的平面面积。当从平面图观看时，第一散热部件240可以具有矩形形状。可选地，第一散热部件240可以在平面图中具有圆化的(rounded)形状，如图4B所示。例如，第一散热部件240可以具有圆形、椭圆形、圆形和椭圆形的组合形状、不规则形状等。如果存在多个第一散热部件240，则第一散热部件240可以具有彼此不同的形状以及彼此不同的面积。尽管第一热源215已经被描述为与单个第一散热部件240关联，但是第一热源215可以与多个第一散热部件240关联。第一热源215的平面位置可以不限于第一半导体芯片200的边缘。换言之，第一热源215的平面位置可以在第一半导体芯片200中被不同地改变。第一散热部件240可以交叠第一半导体芯片200的第一热源215的至少一部分，或可以邻近于第一热源215。因此，从第一热源215产生的热可以更快速地传递到第一散热部件240。
再次参照图1B，第二连接焊盘331和第二散热部件340可以提供在第二半导体芯片300的顶表面300a上。在某些实施例中，第二对准标记351也可以提供在第二半导体芯片300的顶表面300a上。第二散热部件340可以包括第二散热焊盘341和第二散热凸块343。第二散热部件340可以与安装在第二半导体芯片300上的第三半导体芯片400的底表面400b分隔开。第二散热焊盘341可以包括金属(例如，铜、铝和/或镍)或其它导热材料。第二散热凸块343可以类似地包括金属或其它导热材料。当第二半导体芯片300运行时，从第二半导体芯片300的第二热源315产生的热可以通过第二散热部件340更快速地排放。因此，可以改善第二半导体芯片300的可靠性。第二散热部件340的形状和位置可以与参照图3A、3B、4A和4B描述的第一散热部件240的形状和位置相同或类似。
第二连接焊盘331可以与第二散热部件340横向地分隔开。第二连接焊盘331可以电连接到第二贯穿通路320。第二贯穿通路320可以穿过第二半导体芯片300从而电连接到第二电路图案层310。第二连接焊盘331可以包括与第二散热焊盘341相同、类似或不同的材料。第二连接焊盘331的厚度可以实质上等于第二散热焊盘341的厚度。
第三半导体芯片400可以安装在第二半导体芯片300的顶表面300a上。第二连接凸块333可以设置在第二连接焊盘331上，并可以与第二连接焊盘331和第二导电焊盘413接触。第三半导体芯片400可以通过第二连接凸块333和第二连接焊盘331而电连接到第二半导体芯片300。第二连接凸块333的高度可以大于第二散热凸块343的高度。第三绝缘图案530可以设置在第二半导体芯片300和第三半导体芯片400之间以覆盖第二连接凸块333的侧壁。第二散热部件340可以与第三半导体芯片400的底表面分隔开，所以第三绝缘图案530可以设置在第二散热部件340和第三半导体芯片400之间。第三绝缘图案530可以包括绝缘的聚合物。
第三半导体芯片400可以包括邻近其底表面400b的第三电路图案层410。第三电路图案层410可以包括与第二电路图案层310相同种类或类似种类的集成电路(例如，存储电路)。然而，实施例不限于此。在另一些实施例中，第三电路图案层410可以包括其它各种种类的集成电路中的至少一种。在另一些实施例中，可以省略第三半导体芯片400。在此情况下，可以省略第二贯穿通路320和第二连接焊盘331。
散热片(heat slug)350可以设置在第三半导体芯片400上。散热片350可以包括金属诸如铜、铝、镍或其它导热材料。当第三半导体芯片400运行时，从第三半导体芯片400的第三热源415产生的热可以通过散热片350排放。在另一些实施例中，可以省略散热片350。
实施例不限于该数量的半导体芯片。在另一些实施例中，第四半导体芯片(未示出)可以安装在第三半导体芯片400上。在此情况下，第三半导体芯片400可以包括第三贯穿通路(未示出)和第三散热部件(未示出)。第三贯穿通路可以穿过第三半导体芯片400，并且第三散热部件可以设置在第三半导体芯片400的顶表面上。在此情况下，散热片350可以形成在第四半导体芯片上。
模塑层500可以设置在基板100上以覆盖第三半导体芯片400。模塑层500还可以覆盖第一半导体芯片200的侧壁和第二半导体芯片300的侧壁。在另一些实施例中，可以省略第一、第二和第三绝缘图案510、520和530，并且模塑层500可以延伸以填充基板100和第一半导体芯片200之间的空间、第一和第二半导体芯片200和300之间的空间和/或第二和第三半导体芯片300和400之间的空间。在此情况下，模塑层500可以提供在第一散热部件240和第二半导体芯片300之间和/或在第二散热部件340和第三半导体芯片400之间。模塑层500可以包括聚合物，诸如环氧模塑料。
图5是示出根据实施例的半导体封装的截面图。在下文，为了说明的容易和方便的目的，将省略或简要提及对如上所述的相同元件的描述。参照图5，半导体封装2可以包括基板100以及多个半导体芯片200、300和400。第一半导体芯片200可以安装在基板100上。第一半导体芯片200可以通过一个或多个互连部件150电连接到基板100。第一半导体芯片200可以包括第一电路图案层210和第一贯穿通路220。第一对准标记251可以设置在第一半导体芯片200的顶表面200a上。连接焊盘231可以设置在第一半导体芯片200的顶表面200a上并可以电连接到第一贯穿通路220。
第一散热部件240可以设置在第一半导体芯片200的顶表面200a上。第一散热部件240可以与安装在第一半导体芯片200上的第二半导体芯片300的底表面300b分隔开。第一散热部件240可以包括参照图1B描述的第一散热焊盘241。另一方面，与图1B不同，本实施例中的第一散热部件240可以不包括参照图1B描述的第一散热凸块243。第一散热部件240可以与第一连接焊盘231和第一对准标记251横向地分隔开。第一散热部件240可以包括与第一连接焊盘231和第一对准标记251相同、类似或不同的材料。第一散热部件240的厚度可以实质上等于第一连接焊盘231的厚度和第一对准标记251的厚度。
如参照图1A、4A和4B所述的，本实施例中的第一散热部件240可以交叠第一半导体芯片200的第一热源215。当第一半导体芯片200运行时，从第一热源215产生的热可以更快速地且容易地传递到第一散热部件240。因此，热可以更均匀地分布在第一半导体芯片200中。换言之，可以改善半导体封装2的可靠性。如参照图4A和4B所述的，本实施例中的第一散热部件240的形状可以被不同地修改，并且任何数量的第一散热部件240可以被包括。
如上所述，第一散热部件240可以与第二半导体芯片300的底表面300b分隔开，因此，从第一半导体芯片200的第一热源215产生的热可以不传递到第二半导体芯片300。这意味着图2A和2B的裂缝C可以不形成在第二半导体芯片300中。结果，第二半导体芯片300的第二集成电路311的位置可以不受第一散热部件240的位置限制。例如，如图1C所示，第二集成电路311可以与第一散热部件240垂直地交叠。换言之，第二集成电路311可以位于不同的位置。
第二半导体芯片300可以借助于至少一个第一连接凸块233安装在第一半导体芯片200的顶表面200a上。第一连接凸块233可以与设置在第一半导体芯片200的顶表面200a上的第一连接焊盘231接触。第二绝缘图案520可以设置在第一和第二半导体芯片200和300之间以及在第一散热部件240和第二半导体芯片300之间。
第二半导体芯片300可以包括第二电路图案层310和第二贯穿通路320。第二连接焊盘331和第二散热部件340可以设置在第二半导体芯片300的顶表面300a上。第二散热部件340可以包括图1B的第二散热焊盘341，但是可以不包括图1B的第二散热凸块343。第二散热部件340可以与安装在第二半导体芯片300上的第三半导体芯片400的底表面400b分隔开。当第二半导体芯片300运行时，从第二半导体芯片300的第二热源315产生的热可以通过第二散热部件340更快速地排放。第二散热部件340的形状和位置可以与参照图4A和4B描述的第一散热部件240相同或类似。
第二连接焊盘331可以与第二散热部件340横向地分隔开。第二连接焊盘331可以包括与第二散热部件340相同的材料。第二连接焊盘331的厚度可以实质上等于第二散热部件340的厚度。
第三半导体芯片400可以安装在第二半导体芯片300的顶表面上。第二连接凸块333可以与第二连接焊盘331的顶表面接触。第二连接凸块333的高度可以大于第二散热部件340的高度。第二散热部件340可以与第三半导体芯片400的底表面400b分隔开，所以第三绝缘图案530可以提供在第二散热部件340和第三半导体芯片400之间。散热片350可以设置在第三半导体芯片400上。在另一些实施例中，可以省略散热片350。
模塑层500可以提供在基板100上以覆盖第三半导体芯片400。模塑层500可以与参照图1B描述的相同。
接下来，将描述制造半导体封装的方法。
图6A、6B和6D至6H是示出根据实施例的制造半导体封装的方法的截面图。图6C是对应于图6B的平面图。在下文，为了说明的容易和方便的目的，将省略或简要提及以上已描述的特征。
参照图6A，可以制备包括第一半导体芯片200的半导体基板201。多个第一半导体芯片200可以设置在半导体基板201中。半导体基板201可以是由半导体形成的晶片级半导体基板(例如，其上可形成半导体芯片和/或器件的硅基板或其它基板)。第一半导体芯片200可以包括第一电路图案层210和至少一个第一贯穿通路220。第一电路图案层210和第一贯穿通路220可以与参照图1B所描述的相同。导电层260可以形成在第一半导体芯片200的顶表面200a上。导电层260可以包括金属诸如铜、铝、镍等。
参照图6B和6C，导电层260可以被图案化以在第一半导体芯片200的顶表面200a上形成第一连接焊盘231、第一散热焊盘241和第一对准标记251。例如，导电层260的图案化工艺可以通过光刻工艺和蚀刻工艺进行；然而，可以采用其它的图案化技术。由于第一散热焊盘241、第一连接焊盘231和第一对准标记251通过相同的图案化工艺形成，所以第一散热焊盘241可以更容易且更快速地形成。第一散热焊盘241可以包括与第一连接焊盘231和第一对准标记251相同的材料。第一散热焊盘241的厚度T2可以实质上等于第一连接焊盘231的厚度T1和第一对准标记251的厚度T3。第一连接焊盘231、第一散热焊盘241和第一对准标记251可以包括与参照图1A至1C描述的那些相同或类似的结构。
参照图6D，半导体基板201可以被切割以使第一半导体芯片200彼此分离。每个第一半导体芯片200可以与参照图1A和1B描述的相同。然而，在某些实施例中，从基板201切割的每个半导体芯片200可以是不同的半导体芯片。
参照图6E，第一半导体芯片200可以安装在基板100上。基板100可以是印刷电路板(PCB)、半导体芯片或其上可安装半导体芯片的其它基板。第一半导体芯片200可以通过参照图6A至6D描述的方法制造。当第一半导体芯片200安装在基板100上时，第一半导体芯片200可以基于第一对准标记251而与基板100对准。互连部件150可以形成在基板100和第一半导体芯片200之间。第一绝缘图案510可以形成在基板100和第一半导体芯片200的底表面200b之间以填充互连部件150之间的空间。在另一些实施例中，可以不形成第一绝缘图案510。外部端子101可以形成在基板100的底表面上。
参照图6F，第二半导体芯片300可以安装在第一半导体芯片200的顶表面200a上。第二半导体芯片300可以包括第二电路图案层310和至少一个第二贯穿通路320。第二半导体芯片300可以与参照图1B描述的相同或类似。第二半导体芯片300可以通过与参照图6A至6D描述的第一半导体芯片200的制造方法相同的方法或类似的方法制造。例如，导电层可以沉积在第二半导体芯片300的顶表面上，沉积的导电层可以被图案化以在第二半导体芯片300的顶表面上形成第二连接焊盘331、第二散热焊盘341和第二对准标记351。当第二半导体芯片300安装在第一半导体芯片200上时，第二半导体芯片300的位置可以通过第二对准标记351而被控制在第一半导体芯片200上。
第一连接凸块233可以形成在第一连接焊盘231上。第一连接凸块233可以与第一连接焊盘231接触，但是可以不与第一散热焊盘241接触。第一散热凸块243可以形成在第一散热焊盘241上。第一散热凸块243的高度可以小于第一连接凸块233的高度。因此，第一散热部件240可以与第二半导体芯片300的底表面300b分隔开。形成第一散热凸块243的工艺可以与形成第一连接凸块233的工艺相同或类似。由于第一散热部件240还包括第一散热凸块243，所以第一散热部件240的体积可以增大。因此，从第一热源215产生的热可以更快速地传递到第一散热部件240。第二绝缘图案520可以形成在第一和第二半导体芯片200和300之间以覆盖第一连接凸块233的侧壁。第二绝缘图案520还可以提供在第一散热部件240和第二半导体芯片300之间。在另一些实施例中，可以省略第二绝缘图案520。
参照图6G，第三半导体芯片400可以安装在第二半导体芯片300上。第三半导体芯片400可以包括邻近于第三半导体芯片400的底表面400b的第三电路图案层410。安装第三半导体芯片400的工艺可以与安装第二半导体芯片300的工艺相同或类似。第二连接凸块333可以形成在第二连接焊盘331上。第二连接凸块333可以与第二连接焊盘331接触，但是可以不与第二散热焊盘341接触。第二散热凸块343可以形成在第二散热焊盘341上。第二散热凸块343的高度可以低于或小于第二连接凸块333的高度。因此，第二散热部件340可以与第三半导体芯片400的底表面400b分隔开。第三绝缘图案530可以形成在第二和第三半导体芯片300和400之间。由于第二散热部件340与第三半导体芯片400的底表面分隔开，所以第三绝缘图案530也可以提供在第二散热部件340和第三半导体芯片400之间。在另一些实施例中，可以省略第三绝缘图案530。散热片350可以形成在第三半导体芯片400上。
参照图6H，模塑层500可以形成在基板100上以覆盖第一至第三半导体芯片200、300和400。在另一些实施例中，可以省略第一、第二和第三绝缘图案510、520和530，并且模塑层500还可以形成在基板100和第一半导体芯片200之间、在第一和第二半导体芯片200和300之间以及在第二和第三半导体芯片300和400之间。在此情况下，模塑层500可以提供在第一散热部件240和第二半导体芯片300之间以及在第二散热部件340和第三半导体芯片400之间。
在另一些实施例中，可以省略图6E的第一散热凸块243和图6F的第二散热凸块343。在此情况下，可以制造图5的半导体封装2。
参照图6I，可以类似于图6A和6B的半导体基板201制备半导体基板201i。然而，在此实施例中，可以不形成第一散热焊盘241。也就是说，半导体基板201i的导电层260可以被图案化使得不形成第一散热焊盘241。半导体基板201i还可以被加工为上述的半导体基板201。然而，在图6F中，第一散热凸块243可以形成在第一半导体芯片200的顶表面200a上，作为类似于图3A所示的第一散热部件240，而不是形成在第一散热焊盘241上。
[应用]
图7是示出包括根据某些实施例的半导体封装的封装模块的示例的示意图。图8是示出包括根据某些实施例的半导体封装的电子系统的示例的示意方框图。图9是示出包括根据某些实施例的半导体封装的存储卡的示例的示意方框图。
参照图7，封装模块1200可以包括采用四面扁平封装(QFP)技术封装的一个或多个第一半导体器件1220和第二半导体器件1230。半导体器件1220和1230可以包括根据前述实施例的半导体封装1、2和其它半导体封装中的至少一个。封装模块1200可以通过提供在板1210的一侧上的外部连接端子1240而连接到外部电子装置。
参照图8，电子系统1300可以包括控制器1310、输入/输出(I/O)装置1320以及存储器件1330。控制器1310、I/O装置1320和存储器件1330可以通过数据总线1350彼此通信。数据总线1350可以对应于电信号通过其传输的通道。例如，控制器1310可以包括微处理器、数字信号处理器、微控制器以及具有与其任何一个类似的功能的其它逻辑装置中的至少一个。控制器1310、I/O装置1320、存储器件1330、接口1340中的至少一个可以包括根据前述实施例的半导体封装1、2和其它半导体封装中的至少一个。I/O装置1320可以包括键区、键盘和显示装置中的至少一个。存储器件1330是存储数据的器件。存储器件1330可以存储数据和/或由控制器1310执行的指令。存储器件1330可以包括易失性存储器件和非易失性存储器件中的至少一个。在某些实施例中，存储器件1330可以包括闪存器件。例如，实施有该技术的闪存器件可以安装在诸如移动设备或膝上计算机的信息处理系统中。闪存器件可以被实现为固态盘(SSD)。在此情况下，电子系统1300可以在存储器件1330中稳定地存储大量数据。电子系统1300还可以包括接口单元1340，接口单元1340配置为将电数据传输到通讯网络或从通讯网络接收电数据。接口单元1340可以通过无线或电缆操作。例如，接口单元1340可以包括天线或无线/电缆收发器。尽管在附图中没有示出，但是电子系统1300还可以包括应用芯片组和/或照相机图像处理器(CIS)。
电子系统1300可以被实现为移动系统、个人计算机、工业计算机或多功能逻辑系统。例如，移动系统可以为个人数字助理(PDA)、便携式计算机、网络平板、无线电话、移动电话、膝上计算机、数字音乐播放器、存储卡或信息发送/接收系统中的一个。如果电子系统1300是能够进行无线通讯的设备，则电子系统1300可以用于诸如第三代通讯系统的通讯接口协议(例如，CDMA、GSM、NADC、E-TDMA、WCDMA、CDMA2000)中。
参照图9，存储卡1400可以包括非易失性存储器件1410和存储器控制器1420。非易失性存储器件1410和存储器控制器1420可以配置为存储数据或读取所存储的数据。存储器件1410和存储器控制器1420中的至少一个可包括根据前述实施例的半导体封装1、2和其他半导体封装中的至少一个。存储器控制器1420可以配置为响应于主机1430的读/写请求而从非易失性存储器件1410读取数据或将数据存储到其中。
根据某些实施例，散热部件可以设置在第一半导体芯片的顶表面上。当第一半导体芯片运行时，从热源产生的热可以通过第一半导体芯片传递到散热部件。因此，热可以更均匀地分布在第一半导体芯片中。
散热部件可以与安装在第一半导体芯片上的第二半导体芯片的底表面分隔开。因此，从第一半导体芯片的热源产生的热可以不传递到第二半导体芯片。换言之，裂缝不会在第二半导体芯片中引起，所以不会损坏第二半导体芯片的第二集成电路。第二集成电路的位置可以不受散热部件的位置的限制，而是可以被不同地改变。
散热部件、连接焊盘和对准标记可以通过相同的工艺形成，所以可以容易制造半导体封装。
实施例包括能够改善散热效率的半导体封装以及制造该半导体封装的方法。
实施例包括能够增大半导体芯片中包括的集成电路的布置的自由度的半导体封装以及制造该半导体封装的方法。
在实施例中，半导体封装可以包括：基板；第一半导体芯片，安装在基板上；第二半导体芯片，安装在第一半导体芯片的顶表面上；连接凸块，设置在第一和第二半导体芯片之间以将第二半导体芯片电连接到第一半导体芯片；以及散热焊盘，设置在第一半导体芯片的顶表面上并与第二半导体芯片的底表面分隔开。
在某些实施例中，半导体封装还可以包括：连接焊盘，设置在第一半导体芯片的顶表面上。连接焊盘可以与连接凸块接触。
在某些实施例中，散热焊盘可以包括与连接焊盘相同的材料。
在某些实施例中，散热焊盘的厚度可以等于连接焊盘的厚度。
在某些实施例中，第一半导体芯片可以包括贯穿通路，并且连接焊盘可以电连接到贯穿通路。
在某些实施例中，半导体封装还可以包括：对准标记，设置在第一半导体芯片的顶表面上。对准标记可以包括与散热焊盘相同的材料，并且对准标记的厚度可以等于散热焊盘的厚度。
在某些实施例中，半导体封装还可以包括：设置在散热焊盘上的散热凸块。散热凸块可以与第二半导体芯片的底表面分隔开。
在某些实施例中，半导体封装还可以包括：绝缘图案，提供在第一和第二半导体芯片之间且覆盖连接凸块的侧壁。绝缘图案可以提供在散热焊盘和第二半导体芯片之间。
在某些实施例中，第一半导体芯片可以包括邻近第一半导体芯片的底表面的热源。当从平面图观看时，散热焊盘可以交叠热源。
在某些实施例中，半导体封装还可以包括：安装在第二半导体芯片的顶表面上的第三半导体芯片；以及设置在第二半导体芯片的顶表面上且与第三半导体芯片的底表面分隔开的散热部件。
在某些实施例中，半导体封装还可以包括：上凸块，设置在第二和第三半导体芯片之间以将第三半导体芯片电连接到第二半导体芯片。散热部件的高度可以低于上凸块的高度。
在另一个方面中，半导体封装可以包括：基板；第一半导体芯片，安装在基板上；第二半导体芯片，设置在第一半导体芯片上；连接凸块，设置在第一和第二半导体芯片之间以将第二半导体芯片电连接到第一半导体芯片；第一焊盘，设置在第一半导体芯片的顶表面上且与连接凸块接触；以及第二焊盘，设置在第一半导体芯片的顶表面上且与第二半导体芯片的底表面分隔开。
在某些实施例中，第二焊盘可以包括与第一焊盘相同的材料，并且第二焊盘的厚度可以等于第一焊盘的厚度。
在某些实施例中，半导体封装还可以包括：设置在第二焊盘上的散热凸块。散热凸块可与第二半导体芯片的底表面分隔开。
在某些实施例中，半导体封装还可以包括：设置在第一半导体芯片的顶表面上的对准标记。对准标记可以包括与第一和第二焊盘相同的材料。
在某些实施例中，第二半导体芯片可以包括邻近第二半导体芯片的底表面的集成电路。当从平面图观看时，集成电路中的至少一个可以交叠第二焊盘。
在另一个实施例中，一种制造半导体封装的方法可以包括：制备包括散热焊盘的第一半导体芯片；将第一半导体芯片安装在基板上；以及将第二半导体芯片安装在第一半导体芯片的顶表面上。第二半导体芯片可以通过连接凸块电连接到第一半导体芯片。散热焊盘可以设置在第一半导体芯片的顶表面上，并可以与第二半导体芯片的底表面分隔开。
在某些实施例中，制备第一半导体芯片可以包括：在第一半导体芯片的顶表面上形成导电层；以及图案化导电层以形成散热焊盘、连接焊盘和对准标记。连接焊盘和对准标记可以与散热焊盘分隔开。
在某些实施例中，制备第一半导体芯片还可以包括：在散热焊盘上形成散热凸块。散热凸块的高度可以低于连接凸块。
在某些实施例中，安装第二半导体芯片还可以包括：使连接凸块与连接焊盘接触。连接凸块可以与散热焊盘分隔开。
尽管实施例已经参照特定的实施例进行了描述，但是对于本领域技术人员将是显然的，可以进行各种改变和修改，而没有脱离精神和范围。因此，应当理解，上述实施例不是进行限制，而是说明性的。因此，该范围将由权利要求书及其等同物的最宽可允许解释来确定，而不应被前述的描述限制或限定。
本申请要求于2014年9月11在韩国知识产权局提交的韩国专利申请No.10-2014-0120307的优先权，其公开内容通过引用整体结合于此。

Claims (20)

1.一种半导体封装，包括：
基板；
第一半导体芯片，安装在所述基板上；
第二半导体芯片，安装在所述第一半导体芯片的顶表面上；
连接凸块，设置在所述第一半导体芯片和所述第二半导体芯片之间以将所述第二半导体芯片电连接到所述第一半导体芯片；
第一散热部件，在所述第一半导体芯片和所述第二半导体芯片之间设置在所述第一半导体芯片的所述顶表面上并与所述第二半导体芯片的底表面分隔开；以及
绝缘图案，提供在所述第一半导体芯片和所述第二半导体芯片之间，并且设置在所述第一散热部件的最高表面和所述第二半导体芯片之间。
2.如权利要求1所述的半导体封装，其中所述第一散热部件包括散热焊盘。
3.如权利要求2所述的半导体封装，其中
所述第一散热部件还包括设置在所述散热焊盘上的散热凸块，并且
所述散热凸块与所述第二半导体芯片的所述底表面分隔开。
4.如权利要求2所述的半导体封装，还包括：
连接焊盘，设置在所述第一半导体芯片的所述顶表面上，
其中所述连接焊盘与所述连接凸块接触。
5.如权利要求4所述的半导体封装，其中所述散热焊盘包括与所述连接焊盘实质上相同的材料。
6.如权利要求4所述的半导体封装，其中所述散热焊盘的厚度实质上等于所述连接焊盘的厚度。
7.如权利要求2所述的半导体封装，还包括：
对准标记，设置在所述第一半导体芯片的所述顶表面上，
其中：
所述对准标记包括与所述散热焊盘实质上相同的材料，并且
所述对准标记的厚度实质上等于所述散热焊盘的厚度。
8.如权利要求1所述的半导体封装，其中：
所述第一半导体芯片包括贯穿通路，并且
所述连接凸块电连接到所述贯穿通路。
9.如权利要求1所述的半导体封装，其中所述第一散热部件包括直接设置在所述第一半导体芯片的顶表面上的散热凸块。
10.如权利要求1所述的半导体封装，其中：
所述绝缘图案覆盖所述连接凸块的侧壁。
11.如权利要求1所述的半导体封装，其中：
所述第一半导体芯片包括邻近所述第一半导体芯片的底表面的热源，并且
当从平面图观看时，所述第一散热部件交叠所述热源。
12.如权利要求11所述的半导体封装，其中：
所述热源被称为第一热源；
所述第一半导体芯片还包括邻近所述第一半导体芯片的底表面的第二热源，并且
当从平面图观看时，所述第一散热部件交叠所述第一热源和所述第二热源。
13.如权利要求1所述的半导体封装，还包括：
第三半导体芯片，安装在所述第二半导体芯片的顶表面上；
第二散热部件，设置在所述第二半导体芯片的所述顶表面上且与所述第三半导体芯片的底表面分隔开；以及
设置在所述第二半导体芯片和所述第三半导体芯片之间且设置在所述第二散热部件和所述第三半导体芯片之间的第三绝缘图案。
14.如权利要求13所述的半导体封装，还包括：
上凸块，设置在所述第二半导体芯片和所述第三半导体芯片之间以将所述第三半导体芯片电连接到所述第二半导体芯片，
其中所述第二散热部件的高度低于所述上凸块的高度。
15.如权利要求1所述的半导体封装，其中：
所述第二半导体芯片包括邻近所述第二半导体芯片的所述底表面的集成电路，并且
当从平面图观看时，所述集成电路中的至少一个交叠所述第一散热部件。
16.一种半导体封装，包括：
基板；
第一半导体芯片，设置在所述基板上；
第二半导体芯片，设置在所述第一半导体芯片上；
连接凸块，设置在所述第一半导体芯片和所述第二半导体芯片之间以将所述第二半导体芯片电连接到所述第一半导体芯片；以及
第一焊盘，设置在所述第一半导体芯片与所述连接凸块之间；
散热部件，在所述第一半导体芯片和所述第二半导体芯片之间设置在所述第一半导体芯片的顶表面上并与所述第二半导体芯片的底表面分隔开，其中所述散热部件包括第二焊盘；以及
绝缘图案，提供在所述第一半导体芯片和所述第二半导体芯片之间，且设置在所述散热部件的最高表面和所述第二半导体芯片之间。
17.如权利要求16所述的半导体封装，其中所述第二焊盘包括与所述第一焊盘相同的材料，并且
其中所述第二焊盘的厚度等于所述第一焊盘的厚度。
18.一种制造半导体封装的方法，该方法包括：
制备第一半导体芯片，该第一半导体芯片包括设置在该第一半导体芯片的顶表面上的图案化的导电层；
将所述第一半导体芯片安装在基板上；
将第二半导体芯片安装在所述第一半导体芯片的顶表面上，所述第二半导体芯片通过连接凸块电连接到所述第一半导体芯片；
形成设置在所述第一半导体芯片的所述顶表面上且与所述第二半导体芯片的底表面分隔开的散热部件；以及
形成提供在所述第一半导体芯片和所述第二半导体芯片之间且设置在所述散热部件的最高表面和所述第二半导体芯片之间的绝缘图案。
19.如权利要求18所述的方法，其中：
制备所述第一半导体芯片包括：
在所述第一半导体芯片的所述顶表面上形成导电层；以及
图案化所述导电层以形成散热焊盘；并且
所述散热部件包括所述散热焊盘。
20.如权利要求18所述的方法，其中：
制备所述第一半导体芯片包括：
在所述第一半导体芯片的所述顶表面上形成导电层；以及
图案化所述导电层以在所述导电层中形成开口；并且
形成所述散热部件包括在所述导电层中的所述开口中形成所述散热部件。
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