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CN105340078A - 封装上封装结构 - Google Patents

封装上封装结构 Download PDF

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Publication number
CN105340078A
CN105340078A CN201480017384.6A CN201480017384A CN105340078A CN 105340078 A CN105340078 A CN 105340078A CN 201480017384 A CN201480017384 A CN 201480017384A CN 105340078 A CN105340078 A CN 105340078A
Authority
CN
China
Prior art keywords
solder ball
package
encapsulation
substrate layer
nude film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201480017384.6A
Other languages
English (en)
Inventor
高华宏
刘宪明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Marvell World Trade Ltd
Mawier International Trade Co Ltd
Original Assignee
Mawier International Trade Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/176,695 external-priority patent/US20140151880A1/en
Application filed by Mawier International Trade Co Ltd filed Critical Mawier International Trade Co Ltd
Publication of CN105340078A publication Critical patent/CN105340078A/zh
Pending legal-status Critical Current

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    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本公开的实施例提供了一种封装上封装布置，包括包含衬底层(116)的第一封装(804，904)，衬底层包括顶侧(117a)和与顶侧相对的底侧(117b)，其中衬底层的顶侧限定基本平坦的表面(117a)，以及包括耦合至衬底层的底侧的第一裸片(118)。布置也包括第二封装(802，902)，包括多行焊料球(806，906)以及无源部件或有源部件(810，910，920)中的一个或两个中的至少一个。第二封装经由多行焊料球附接至第一封装的衬底层的顶侧的基本平坦的表面。有源部件和/或无源部件(810，910，920)附接至第一封装的衬底层的顶侧的基本平坦的表面。

Description

封装上封装结构
相关申请的交叉引用
本申请要求享有2014年2月10日提交的美国专利申请No.14/176,695的优先权，该美国专利申请要求享有2013年2月11日提交的美国临时申请No.61/763,285的优先权，该申请的全部说明书在此通过引用整体并入本文。该申请也是2012年8月13日提交的美国专利申请No.13/584,027的部分继续申请，其要求享有2011年8月19日提交的美国临时申请No.61/525,521的优先权，该申请的全部说明书在此通过引用整体并入本文。
技术领域
本公开的实施例涉及封装上封装的结构，并且更具体地涉及并入具有裸片朝下倒装的结构的基底封装的封装布置。
背景技术
在此提供背景技术描述的目的是大致展示本公开的上下文。目前称为发明人对于背景技术部分中描述的、以及可以另外在递交时获得现有技术资格的说明的特征方面的工作并未清楚地或者隐含地承认作为本公开的现有技术。
通常，在具有许多的多芯片封装布置中，封装布置被布置为封装上封装(PoP)布置或者多芯片模块(MCM)布置中的任一种。这些封装布置倾向于相当厚(例如大约1.7毫米至2.0毫米)。
PoP布置可以包括组合了相互层叠的两个或多个封装的集成电路。例如，PoP布置可以配置具有两个或多个存储器装置封装。PoP布置也可以配置具有混合逻辑存储堆叠，其包括在底部封装中的逻辑以及在顶部封装中的存储器，反之亦然。
通常，与位于PoP布置底部上的封装(在此称作“底部封装”)相关联的裸片将位于底部封装之上的封装(在此称作“顶部封装”)的占位面积限定为某个尺寸。额外地，该配置通常将顶部封装限制为两行外周焊料球。该封装布置1100的示例示出在图11中并且包括顶部封装1102和底部封装1104。如图可见，底部封装1104包括经由粘合剂1110附接至衬底1108的裸片1106。裸片1106经由采用引线1112的引线键合工艺而耦合至衬底1108。焊料球1114提供用于将封装布置1100耦合至另一衬底(未示出)，诸如例如印刷电路板(PCB)。顶部封装1102包括耦合至衬底1116的裸片1116。焊料球1120提供用于将顶部封装1102耦合至底部封装1104。顶部封装1102可以包括外壳1122，通常形式为密封剂，如果需要。如图可见，由于存在裸片1106和底部封装1104的外壳1124(通常形式为密封剂并且可以包括或不包括)，可以仅提供两行焊料球1120。因此，顶部封装可以需要具有更大的尺寸或占位面积以当顶部封装附接至底部封装时避免底部封装的裸片1106。该封装布置1100也可以存在顶部封装1102相对于裸片1106和/或外壳1124具有空隙的问题。
图11示出了封装布置1200的另一示例，其中已经采用模塑阵列工艺(MAP)形成了底部封装1204。底部封装1204类似于图11的底部封装1104并且包括密封剂1206。通常蚀刻密封剂1206以暴露焊料球1208。备选地，蚀刻密封剂1206，并且随后焊料球1208沉积在开口1210内。由于裸片1106和密封剂1206的存在，该封装布置1200再次仅允许在顶部封装1102的外周周围包括两行焊料球1120。该封装布置1200也可以存在顶部封装1102相对于裸片1106和密封剂1206具有空隙的问题，以及相对于开口1210对准的问题。
发明内容
在各个实施例中，本公开提供了一种封装上封装布置，包括第一封装，第一封装包含衬底层，衬底层包括(i)顶侧和(ii)与顶侧相对的底侧，其中衬底层的顶侧限定了基本平坦的表面，以及耦合至衬底层的底侧的第一裸片。封装上封装布置也包括第二封装，第二封装包括多行焊料球以及(i)有源部件或(ii)无源部件中的一个或两个中的至少一个。第二封装经由多行焊料球附接至第一封装的衬底层的顶侧的基本平坦的表面。(i)有源部件或(ii)无源部件的一个或两个的至少一个附接至第一封装的衬底层的顶侧的基本平坦的表面。
在各个实施例中，本公开也提供了一种方法，该方法提供包括衬底层的第一封装，其中衬底层包括(i)顶侧和(ii)与顶侧相对的底侧，其中衬底层的顶侧限定了基本平坦的表面，以及其中第一封装进一步包括耦合至衬底层的底侧的第一裸片。该方法进一步包括提供具有附接至第二封装的底侧的多行焊料球的第二封装，经由第二封装的多行焊料球将第二封装附接至第一封装的基本平坦的表面，以及将(i)有源部件或(ii)无源部件的中一个或两个中的至少一个附接至第一封装的衬底层的顶侧的基本平坦的表面。
各个实施例潜在地包括一个或多个以下优点。根据在此所述的各个实施例，封装布置可以提供增大的管脚数目。此外，可以对于使用根据在此所述各个实施例的封装布置的电子装置实现更高的速度。
附图说明
结合附图由以下详细说明将易于理解本公开的实施例。为了促进该说明，相同的附图标记标注相同的结构元件。在此借由示例的方式并且并非借由附图的图表中限定的方式而示出了实施例。
图1A示意性示出了包括裸片朝下倒装的PoP结构的示例性裸片布置的示例性封装布置。
图1B示意性示出了具有附接至底部封装的顶部封装的图1A的示例性封装布置。
图2示意性示出了另一示例性封装布置，包括具有暴露材料以提供用于散热路径的裸片朝下倒装的PoP结构的另一示例性裸片布置。
图3示意性示出了另一示例性封装布置，包括暴露以提供散热路径的裸片朝下倒装的PoP结构的另一示例性裸片布置。
图4示意性示出了另一示例性封装布置，包括具有穿硅通孔(TSV)的裸片朝下倒装的PoP结构的另一示例性裸片布置。
图5示意性示出了另一示例性封装布置，包括具有嵌入式印刷电路板(PCB)和/或插件的裸片朝下倒装的PoP结构的另一示例性裸片布置。
图6示意性示出了另一示例性封装布置，包括具有PCB/插件的裸片朝下倒装的PoP结构的另一示例性裸片布置。
图7是用于制造在此所述PoP结构的方法的工艺流程图。
图8示意性示出了另一示例性封装布置，包括示例性封装装置布置和无源和/或有源电子部件。
图9示意性示出了另一示例性封装布置，包括多个裸片和无源和/或有源电子部件。
图10是用于制造在此所述的PoP结构方法的另一工艺流程图。
图11示意性示出了示例性PoP封装布置。
图12示意性示出了另一示例性PoP封装布置。
具体实施方式
图1A示出了根据实施例的封装布置100，其中封装上封装(PoP)的封装布置包括顶部封装102和底部封装104。为了示意说明目的，封装示出为分离的项。顶部封装102包括衬底层106。顶部封装102内的裸片布置可以包括第一裸片108和第二裸片110，其中每个裸片108、110经由焊料球112附接至衬底层106。该配置可以包括在焊料球112和衬底层106之间间隙中的下层填料114。焊料球112通常位于接触焊盘或接触区域(未示出)处。裸片108、110可以经由裸片倒装操作而耦合至衬底层106。备选地，引线键合工艺和粘合层(未示出)可以用于将裸片108、110耦合至衬底层106。额外地，顶部封装102可以包括两个或多个单独的顶部封装102(未示出)，其中每个单独的顶部封装102包括一个或多个裸片。
根据各个实施例，第一裸片108和第二裸片110是存储器装置，并且根据实施例，第一裸片108和第二裸片110是用于移动装置的移动双数据率(mDDR)同步动态随机存取存储器(DRAM)。移动DDR也已知是低功耗DDR。然而，可以采用其他类型存储器装置，包括但不限于双数据率同步动态随机存取存储器(DDRSDRAM)、动态随机存取存储器(DRAM)、NOR或NAND闪存、静态随机存取存储器(SRAM)等等。
根据另一实施例，具有第一裸片108和第二裸片110的顶部封装102涉及专用产品，并且根据实施例，第一裸片108和/或第二裸片110可以表示用于移动装置的专用集成电路(ASIC)。
顶部封装102进一步包括多个焊料球115。多个焊料球115可以附接至顶部封装102的衬底层106的底侧。在图1A的实施例中，多个焊料球115形成了用于在底部封装104上在电学上和在物理上附接或堆叠顶部封装102的配置。
为了明晰，可以在此不示出和/或详述在顶部封装102内使用的材料以及顶部封装102内的其他部件。这些材料和部件在本领域中通常是已知的。
底部封装104包括衬底层116，衬底层116包括顶侧117a和底侧117b。如图1A中所示，顶侧117a限定了底部封装104的基本平坦的表面，也即基本上没有沟槽、凸块、缺口、凹陷等的基本平滑表面。在一个实施例中，顶侧117a的基本平坦的表面并不包含任何部件，这允许顶侧117a容纳(或支持)顶部封装102的各种设计和选择。因此，底部封装104的基本平坦的表面为顶部封装102的多个焊料球115提供了附接至底部封装104的便利方式，这允许设计顶部封装102(或多个单独的顶部封装102)以及由此设计封装布置100的更大灵活性。
底部封装104包括在裸片朝下倒装的结构中经由粘合层120附接至衬底层116的底侧117b的裸片118。在其他实施例中，如在此进一步所述，裸片118可以经由焊料球附接至衬底层116的底侧117b。
根据各个实施例，裸片118可以是存储器装置，诸如用于移动装置的移动双数据率(mDDR)同步动态随机存取存储器(DRAM)。可以采用其他类型存储器装置，包括但不限于双数据率同步动态随机存取存储器(DDRSDRAM)、动态随机存取存储器(DRAM)、NOR或NAND闪存、静态随机存取存储器(SRAM)等等。根据另一实施例，裸片118可以是逻辑装置以形成包括在底部封装104上的逻辑和在顶部封装102上的存储器的混合逻辑-存储器堆叠。
裸片118具有包括一个或多个键合焊盘122a、122b的表面。一个或多个键合焊盘122a、122b通常包括诸如例如铝或铜的导电材料。在其他实施例中可以使用其他合适的材料。裸片118经由耦合至对应键合焊盘122a、122b的键合引线126a、126b而耦合至位于衬底层116上的一个或多个衬底焊盘124a、124b。裸片118可以由模塑材料固定至底部封装104。在其他实施例中，裸片118可以经由倒装裸片或导电粘合剂而与衬底层116电互连。裸片118的电信号可以例如包括用于形成于裸片118上的集成电路(IC)装置(未示出)的输入/输出(I/O)信号和/或电源/接地。
根据实施例，底部封装104经由模塑阵列工艺(MAP)而形成。底部封装104进一步包括通常形式为密封剂的外壳128。蚀刻外壳128以暴露焊料球129。备选地，焊料球129在蚀刻外壳128之后添加至外壳128的蚀刻开口131中。焊料球130添加至焊料球129，并且可以用于将封装布置100耦合至衬底(未示出)，诸如例如印刷电路(PCB)、另一封装等等。备选地，单独的焊料球(组合的焊料球129和焊料球130)在蚀刻外壳128之后添加至蚀刻开口131中。焊料球130通常在底部封装104外周的侧边或周围处，由此形成了球栅阵列(BGA)。
为了明晰，可以不在此示出和/或描述在底部封装104内使用的材料以及底部封装104内的其他部件。这些材料和部件在本领域中通常是已知的。
图1B示出了具有附接至底部封装104的顶部封装102的封装布置100。在图1A和图1B的实施例中，多个焊料球115形成了用于将顶部封装102在电学上和在物理上附接或堆叠至底部封装104的配置。如前所述，顶部封装102可以包括附接至底部封装104的两个或多个单独的顶部封装。
本公开的额外实施例通常涉及封装布置，其包括具有裸片朝下倒装的结构的底部封装104的各个实施例并且示出在图2－图6中。为了简明，在此并未进一步讨论图1A和图1B中所示、与图2－图7中部件相同或类似的部件。
图2示出了封装布置200的另一实施例，封装布置200包括顶部封装102和底部封装204。在图2的实施例中，导热材料206被包括在裸片118的底侧上。在实施例中，导热材料206经由粘合层208附接至裸片118的底侧。导热材料206包括但不限于金属、硅或适用于良好导热性的任何材料。
底部封装204包括耦合至导热材料206的热界面材料(TIM)210。TIM210包括但不限于薄膜、油脂组合物、和下层填料。薄膜可以是超薄的导热材料，其可以通过沉积非晶材料而制备。油脂合成物可以包括具有高导热率和极好分配特性的合成物。普通TIM是白色膏体或热油脂，通常为采用氧化铝、氧化锌或氮化硼填充的硅树脂油。一些类型TIM使用微粒化或研磨粉化的银。另一类型TIM包括相变材料。相变材料通常在室温下为固体但是在工作温度下液化并且行为类似油脂。
下层填料可以基于所需物理特性而选择。因此，导热材料206提供了用于去往TIM210散热的路径。封装布置200可以耦合至衬底(未示出)，诸如例如PCB或另一封装布置。孔洞可以提供在衬底中用以容纳TIM210。
图3示出了包括顶部封装102和底部封装304的封装布置300的实施例。裸片118经由焊料球306附接至衬底层116。根据各个实施例，下层填料308提供在裸片118和衬底层116之间的焊料球306之中。下层填料308提供了对由焊料球306形成的焊接点的保护。其也防止了裸片118的内部层的断裂和分层。下层填料308可以是高纯度低应力的液体环氧树脂。通常，焊料球306尺寸越大，所需下层填料308越少。
底部封装304包括耦合至裸片118背面的热界面材料(TIM)310。TIM310包括但不限于如前所述的薄膜、油脂合成物、和下层填料。在图3的实施例中，暴露了裸片118的背面。裸片118的暴露背面提供了去往TIM310的散热路径。封装布置300可以耦合至诸如例如PCB或另一封装布置的衬底(未示出)。孔洞可以提供在衬底中以容纳TIM310。
图4示出了包括顶部封装102和底部封装404的封装布置400的实施例。裸片118经由焊料凸块306附接至衬底层116。下层填料308提供在位于底部封装404的裸片118和衬底层116之间的间隙中。下层填料308提供了对由焊料球306形成焊接点的保护。
在图4的实施例中，裸片118包括穿硅通孔(TSV)406。在实施例中，裸片118可以在外壳128内凹陷以帮助暴露裸片118的背面。TSV406是穿过裸片118至焊料球306的垂直电连接通孔(垂直互连通路)。在实施例中，底部封装404包括附接至底部封装404的额外焊料球408。额外焊料球408可以例如用于接地/电源和输入/输出。
一个或多个TSV406电耦合至键合焊盘(未示出)并且通常采用例如铜的导电材料填充以传送穿过裸片118的电信号。TSV406倾向于提供相对于键合引线的改进的性能，因为通孔的密度显著较高并且连接的长度与键合引线相比较短。裸片118的暴露背面提供用于底部封装404的散热。因此，封装布置400可以为使用封装布置400的电子装置提供增大的管脚数和更高的速度。
图5示出了包括顶部封装102和底部封装504的封装布置500的实施例。裸片118经由焊料凸块306附接至衬底层510。
在图5的实施例中，底部封装504包括附接至裸片118底侧的一个或多个PCB和/或插件506。根据各个实施例，使用热压工艺或焊料回流工艺将PCB/插件506键合至裸片118。也即，一个或多个导电结构(例如柱体、凸块、焊盘、再分布层)被形成在PCB/插件506和裸片118上以在PCB/插件506和裸片118之间形成键合。
在一些实施例中，裸片118和PCB/插件506均包括具有相同或相似热膨胀系数(CTE)的材料(例如硅)。对于裸片118和PCB/插件506使用具有相同或相似CTE的材料减小了与材料的加热和/或冷却失配相关联的应力。
PCB/插件506向裸片118提供了物理缓冲、支撑和增强剂，特别是在形成一个或多个层以将裸片118嵌入外壳128中期间。也即，如在此所述耦合至PCB/插件506的裸片118提供了受保护的集成电路结构，比单独裸片118在结构上对于与制造外壳128相关联的应力更有弹性，从而导致改进了产率和底部封装504的可靠性。
在实施例中，底部封装504包括额外焊料球512。附接至PCB/插件506的额外焊料球512可以用于例如接地/电源和输入/输出。
图6示出了包括顶部封装102和底部封装604的封装布置600的实施例。裸片118经由粘合层120附接至衬底层116。如图所示，裸片118经由引线键合工艺耦合至衬底层116。
焊料凸块606附接至裸片118的底侧。PCB或插件608附接至焊料球606。在实施例中，可以暴露或凹陷PCB/插件608。在实施例中，底部封装604包括额外焊料球610。额外焊料球610可以用于例如接地/电源和输入/输出。图6的实施例可以允许额外的管脚数并且经由PCB/插件608提供用于底部封装604散热的路径。
图7示出了根据本公开实施例的示例性方法700。在702处，方法700包括提供包括衬底层的第一封装，其中衬底层包括(i)顶侧和(ii)与顶侧相对的底侧，其中衬底层的顶侧限定了基本平坦的表面，以及其中第一封装进一步包括耦合至衬底层的底侧的裸片。
在704处，方法700包括提供具有附接至第二封装的底侧的多行焊料球的第二封装。
在706处，方法700包括经由第二封装的多行焊料球将第二封装附接至第一封装的基本平坦的表面。
图8示出了包括底部封装804的封装布置800。如图可见，底部封装804示出布置为等同或者类似于图1A和图1B中所示的底部封装104。然而，应该注意，如果需要，则底部封装804可以布置为等同或者类似于图2－图6中所示的底部封装204、304、404、504和604。为了简明，在此并未进一步讨论图1A和图1B中所示以及参照底部封装104所述的部件。
封装布置800包括一个或多个封装装置802，一个或多个封装装置802可以经由焊料球806耦合至底部封装804的衬底层116的顶侧117a。封装装置802可以可选地包括衬底层808，封装装置802包括的各种部件和/或裸片(未示出)可以经由各种方法附接其上以形成封装装置802。因此，封装装置802可以包括作为存储器装置的一个或多个裸片(未示出)。例如，封装装置可以类似于图1－图6中所示顶部封装102。封装装置802可以包括形式为用于移动装置的移动双数据率(mDDR)同步动态随机存取存储器(DRAM)的一个或多个裸片(未示出)。移动DDR也已知作为低功耗DDR。然而，可以采用其他类型存储器装置，包括但不限于双数据率同步动态随机存取存储器(DDRSDRAM)、动态随机存取存储器(DRAM)、NOR或NAND闪存、静态随机存取存储器(SRAM)等等。备选地，封装装置802的一个或多个裸片可以代表用于移动装置的专用集成电路(ASIC)。
封装布置800进一步包括一个或多个无源和/或有源电子部件810。无源和/或有源电子部件810可以以任何合适的方式附接至衬底116的顶侧117a。例如，无源和/或有源电子部件810可以经由引线812和焊料814附接至衬底116的顶侧117a。无源部件810的示例包括但不限于，电容器、电阻器、导体、变压器、换能器、传感器和天线。无源部件的另一示例包括但不限于网络，例如电阻器电容器(RC)电路和电感器电容器(LC)电路。有源部件810的示例包括但不限于半导体裸片、集成电路、二极管(例如发光二极管(LED)、激光二极管等)、光电器件和电源。来自封装装置802和/或无源/有源电子部件810的信号可以传送穿过衬底116。封装布置800可以包括相互层叠布置的多个底部封装804，如果需要。多个底部封装804可以布置为相互相同或不同。
图9示出了封装布置900的另一示例，类似于图8的封装布置800。再次，封装布置900示出为包括与图1A和图1B中所示底部封装104相同或类似布置的底部封装904。如果需要，则封装布置904可以布置为与图2－图6中所示的底部封装204、304、404、504和604相同或类似。为了简明，如图1A和图1B中所示并且参照底部封装104描述的部件在此不再进一步讨论。
封装布置900包括裸片902，裸片902采用焊料球906而被裸片倒装附接至底部封装904的衬底116的顶侧117a。一个或多个无源和/或有源部件910附接至底部封装904的衬底116的顶侧117a。无源和/或有源电子部件910可以以任何合适的方式附接至衬底116的顶侧117a。例如，无源和/或有源电子部件910可以经由引线912和焊料914附接至衬底116的顶侧117a。无源部件910的示例包括但不限于电容器、电阻器、导体、变压器、换能器、传感器和天线。无源部件的另一示例包括但不限于网络，例如电阻器电容器(RC)电路和电感器电容器(LC)电路。部件910的示例包括但不限于半导体裸片、集成电路、二极管(例如发光二极管(LED)、激光二极管等)、光电器件和电源。
封装布置900也包括裸片916，裸片916附接至底部封装904的衬底116的顶侧117a。裸片912经由引线918引线键合至底部封装904的衬底116的顶侧117a。粘合层920可以用于将裸片916附接至衬底116的顶侧117a。来自裸片902、无源/有源电子部件910和/或裸片916的信号可以传送穿过底部封装904的衬底116。如果需要，则封装布置900可以包括相互层叠布置的多个底部封装904。多个底部封装904可以布置为相互相同或者相互不同。
图10示出了根据本公开实施例的示例性方法1000。在1002处，方法1000包括提供包括衬底层的第一封装，其中衬底层包括(i)顶侧和(ii)与顶侧相对的底侧，其中衬底层的顶侧限定了基本上平坦的表面，以及其中第一封装进一步包括耦合至衬底层的底侧的裸片。
在1004处，方法1000包括提供第二封装，第二封装具有附接至第二封装的底表面的多行焊料球。
在1006处，方法1000包括经由第二封装的多行焊料球将第二封装附接至第一封装的基本平坦的表面。
在1008处，方法1000包括将(i)有源部件或(ii)无源部件的一个或两个的至少一个附接至第一封装的衬底层的顶侧的基本平坦的表面。
说明书可以使用基于透视的描述，诸如上/下、之上/之下、和/或、或者顶部/底部。这些描述仅仅用于促进讨论并且并非意在将在此所述的实施例的应用约束至任何特定朝向。
为了本公开的目的，短语“A/B”意味着A或B。为了本公开的目的，短语“A和/或B”意味着“(A)、(B)或者(A和B)”。为了本公开的目的，短语“A、B和C的至少一个”意味着“(A)、(B)、(C)、(A和B)、(A和C)、(B和C)或者(A、B和C)”。为了本公开的目的，短语“(A)B”意味着“(B)或(AB)”，也即A是任选的要素。
各个操作描述为以最有助于理解请求保护主题的方式依次执行的多个分立操作。然而，描述的顺序不应构造为暗示了这些操作必须按照顺序。实际上，这些操作可以不按照所展示的顺序而执行。所述操作可以以不同于所述实施例的顺序执行。各个额外操作可以执行和/或所述操作可以在额外实施例中省略。
说明书使用短语“在一个实施例中”、“在实施例中”或者类似语言，其可以每个涉及一个或多个相同或不同的实施例。此外，相对于本公开实施例所使用的术语“包括”、“包含”“具有”等是同义的。
术语裸片、集成电路、单块装置、半导体装置、裸片、和微电子装置通常在微电子领域中可互换使用。本发明可适用于如它们在本领域中通常所理解的以上所有。
本发明的其他特征方面涉及以下条款的一个或多个。
封装上封装布置进一步包括附接至第一封装的衬底层的顶侧的基本平坦的表面的第二裸片。
第二裸片引线键合至第一封装的衬底层的顶侧的基本平坦的表面。
第二裸片经由裸片倒装工艺附接至第一封装的衬底层的顶侧的基本平坦的表面。
封装上封装布置进一步包括位于第一裸片和衬底层之间的粘合层。粘合层将第一裸片附接至第二封装的衬底层。
封装上封装布置进一步包括位于第一裸片底侧上的键合焊盘，以及位于第二封装的衬底层的底侧上的衬底焊盘。裸片的键合焊盘经由引线耦合至衬底层的衬底焊盘以传送第一裸片的电信号。
多行焊料球包括第一焊料球，以及封装上封装布置进一步包括附接至衬底层的底侧的第二焊料球以将第一裸片电连接至第二封装的衬底层，以及包括位于第二焊料球和第二封装的衬底层之间的下层填料。
多行焊料球包括第一焊料球，以及封装上封装布置进一步包括附接至第二封装的底侧的第二焊料球，以及第二焊料球位于第二封装的外周周围以由此形成球栅阵列。
多行焊料球包括第一焊料球。衬底层包括第一衬底层。第一封装进一步包括邻接第一裸片布置的第二裸片。第一裸片和第二裸片的每一个经由第二焊料球连接至第一封装中的第二衬底层。
封装上封装布置进一步包括附接至第一裸片的底侧的热界面材料。
封装上封装布置进一步包括附接至热界面材料的导热材料。
热界面材料包括薄膜、油脂合成物或下层填料中的一个。
(i)插件或(ii)印刷电路板中的一个附接至裸片的底侧。
多行焊料球包括第一多行焊料球，封装上封装布置进一步包括包含第二多行焊料球的第三封装，第一封装经由第一多行焊料球附接至第二封装的基本平坦的表面，以及第三封装经由第二多行焊料球附接至第二封装的基本平坦的表面。
多行焊料球包括第一焊料球，并且封装上封装布置进一步包括附接至衬底层的底侧和第一裸片的顶侧的第二焊料球，以及包括位于第一裸片中的多个穿硅通孔，其中多个穿硅通孔分别在第二焊料球的至少一些、与附接至底部封装的底侧的多个第三焊料球之间延伸。
方法进一步包括将第二裸片附接至第一封装的衬底层的顶侧的基本平坦的表面。
将第一裸片附接至衬底层的底侧包括经由粘合层将第一裸片附接至衬底层的底侧。
多行焊料球包括第一焊料球，并且将第一裸片附接至衬底层的底侧包括经由第二焊料球将第一裸片附接至衬底层的底侧。
方法进一步在位于(i)第二焊料球之中和(ii)第一裸片与第一封装的衬底层的底侧之间的间隙之间提供下层填料。
方法进一步包括在第一裸片上提供键合焊盘，其中键合焊盘位于第一裸片的底侧上；在衬底层上提供衬底焊盘，其中衬底焊盘位于第一封装的衬底层的底侧上；以及经由引线键合工艺将第一裸片上的键合焊盘耦合至衬底层上的衬底焊盘以由此传送第一裸片的电信号。
多行焊料球包括第一焊料球，并且方法进一步包括将第二焊料球附接至第一封装的底侧，其中第二焊料球位于第一封装的右侧和左侧上。
方法进一步包括将热界面材料附接至第一裸片的底侧。
多行焊料球包括第一焊料球，并且方法进一步包括将衬底层的底侧上附接第二焊料球；经由第二焊料球将第一裸片附接至衬底层的底侧；以及在第一裸片中提供穿硅通孔以将第二焊料球连接至附接于第一封装的底侧的第三焊料球。
多行焊料球包括第一焊料球，并且方法进一步包括将第二焊料球附接至第一裸片的底侧；以及将(i)插件或(ii)印刷电路板的一个耦合至第二焊料球。
多行焊料球包括第一多行焊料球，并且方法进一步包括提供第三封装，具有附接至第三封装的底表面的第二多行焊料球，以及经由第二多行焊料球将第三封装附接至第一封装的基本平坦的表面。
尽管在此已经示出并描述了某些实施例，计算用于实现相同目的的广泛各种备选和/或等价实施例或实施方式可以替换所示和所述的实施例而并未脱离本公开的范围。本公开意在覆盖在此所述实施例的任何修改例或变形例。因此，明确有意设计的是，在此所述的实施例仅由权利要求及其等价方式而限定。

Claims (28)

1.一种封装上封装布置，包括：
第一封装，包括
衬底层，包括(i)顶侧和(ii)与所述顶侧相对的底侧，其中所述衬底层的所述顶侧限定基本平坦的表面，以及
第一裸片，耦合至所述衬底层的所述底侧；
第二封装，包括多行焊料球；以及
(i)有源部件或(ii)无源部件中的一个或两个中的至少一个，
其中，所述第二封装经由所述多行焊料球附接至所述第一封装的所述衬底层的所述顶侧的所述基本平坦的表面，以及
其中，所述(i)有源部件或(ii)无源部件中的一个或两个中的至少一个附接至所述第一封装的所述衬底层的所述顶侧的所述基本平坦的表面。
2.根据权利要求1所述的封装上封装布置，进一步包括：
第二裸片，附接至所述第一封装的所述衬底层的所述顶侧的所述基本平坦的表面。
3.根据权利要求2所述的封装上封装布置，其中：
所述第二裸片被引线键合至所述第一封装的所述衬底层的所述顶侧的所述基本平坦的表面。
4.根据权利要求2所述的封装上封装布置，其中：
所述第二裸片经由倒装裸片工艺被附接至所述第一封装的所述衬底层的所述顶侧的所述基本平坦的表面。
5.根据权利要求1所述的封装上封装布置，进一步包括：
粘合层，位于所述第一裸片和所述衬底层之间，
其中所述粘合层将所述第一裸片附接至所述第二封装的所述衬底层的所述底侧。
6.根据权利要求1所述的封装上封装布置，进一步包括：
键合焊盘，位于所述第一裸片的所述底侧上；以及
衬底焊盘，位于所述第二封装的所述衬底层的所述底侧上，
其中所述裸片的所述键合焊盘经由引线耦合至所述衬底层的所述衬底焊盘以传送所述第一裸片的电信号。
7.根据权利要求1所述的封装上封装布置，其中，所述多行焊料球包括第一焊料球，并且所述封装上封装布置进一步包括：
第二焊料球，附接至所述衬底层的所述底侧以将所述第一裸片电连接至所述第二封装的所述衬底层；以及
下层填料，位于所述第二焊料球与所述第二封装的所述衬底层之间。
8.根据权利要求1所述的封装上封装布置，其中，所述多行焊料球包括第一焊料球，并且所述封装上封装布置进一步包括：
第二焊料球，附接至所述第二封装的底侧；以及
第二焊料球位于所述第二封装的外周周围以由此形成球栅阵列。
9.根据权利要求1所述的封装上封装布置，其中：
所述多行焊料球包括第一焊料球；
所述衬底层包括第一衬底层；
所述第一封装进一步包括邻接所述第一裸片布置的第二裸片；以及
所述第一裸片和所述第二裸片中的每个经由第二焊料球连接至所述第一封装中的第二衬底层。
10.根据权利要求1所述的封装上封装布置，进一步包括：
热界面材料，附接至所述第一裸片的底侧。
11.根据权利要求10所述的封装上封装布置，进一步包括：
导热材料，附接至所述热界面材料。
12.根据权利要求11所述的封装上封装布置，其中，所述热界面材料包括薄膜、油脂合成物或下层填料中的一种。
13.根据权利要求1所述的封装上封装布置，进一步包括：
附接至所述裸片的底侧的(i)插件或(ii)印刷电路板中的一个。
14.根据权利要求1所述的封装上封装布置，其中：
所述多行焊料球包括第一多行焊料球；
所述封装上封装布置进一步包括第三封装，所述第三封装包括第二多行焊料球；
所述第一封装经由所述第一多行焊料球附接至所述第二封装的所述基本平坦的表面；以及
所述第三封装经由所述第二多行焊料球附接至所述第二封装的所述基本平坦的表面。
15.根据权利要求1所述的封装上封装布置，其中，所述多行焊料球包括第一焊料球并且所述封装上封装布置进一步包括：
第二焊料球，附接至所述衬底层的所述底侧和所述第一裸片的顶侧；以及
多个穿硅通孔，位于所述第一裸片中，其中所述多个穿硅通孔分别在所述第二焊料球中的至少一些之间延伸以及在附接至所述底部封装的底侧的多个第三焊料球之间延伸。
16.一种方法，包括：
提供包括衬底层的第一封装，其中所述衬底层包括(i)顶侧和(ii)与所述顶侧相对的底侧，其中所述衬底层的所述顶侧限定了基本平坦的表面，以及其中所述第一封装进一步包括耦合至所述衬底层的所述底侧的第一裸片；
提供第二封装，所述第二封装具有附接至所述第二封装的底表面的多行焊料球；
经由所述第二封装的所述多行焊料球将所述第二封装附接至所述第一封装的所述基本平坦的表面；以及
将(i)有源部件或(ii)无源部件中的一个或两个中的至少一个附接至所述第一封装的所述衬底层的所述顶侧的所述基本平坦的表面。
17.根据权利要求16所述的方法，进一步包括：
将第二裸片附接至所述第一封装的所述衬底层的所述顶侧的所述基本平坦的表面。
18.根据权利要求17所述的方法，其中，将所述第二裸片引线键合至所述第一封装的所述衬底层的所述顶侧的所述基本平坦的表面。
19.根据权利要求17所述的方法，其中，将所述第二裸片经由倒装裸片工艺附接至所述第一封装的所述衬底层的所述顶侧的所述基本平坦的表面。
20.根据权利要求16所述的方法，其中，将所述第一裸片附接至所述衬底层的所述底侧包括经由粘合层将所述第一裸片附接至所述衬底层的所述底侧。
21.根据权利要求16所述的方法，其中，所述多行焊料球包括第一焊料球，并且将所述第一裸片附接至所述衬底层的所述底侧包括经由第二焊料球将所述第一裸片附接至所述衬底层的所述底侧。
22.根据权利要求21所述的方法，进一步包括：
在位于(i)所述第二焊料球之中的间隙之间提供下层填料，和在位于(ii)所述第一裸片与所述第一封装的所述衬底层的所述底侧之间的间隙之间提供下层填料。
23.根据权利要求16所述的方法，进一步包括：
在所述第一裸片上提供键合焊盘，其中所述键合焊盘位于所述第一裸片的底侧上；
在所述衬底层上提供衬底焊盘，其中所述衬底焊盘位于所述第一封装的所述衬底层的所述底侧上；以及
经由引线键合工艺将所述第一裸片上的所述键合焊盘耦合至所述衬底层上的所述衬底焊盘以由此传送所述第一裸片的电信号。
24.根据权利要求16所述的方法，其中，所述多行焊料球包括第一焊料球，并且所述方法进一步包括：
将第二焊料球附接至所述第一封装的底侧；
其中所述第二焊料球位于所述第一封装的右侧和左侧上。
25.根据权利要求16所述的方法，进一步包括：
将热界面材料附接至所述第一裸片的底侧。
26.根据权利要求16所述的方法，其中，所述多行焊料球包括第一焊料球并且所述方法进一步包括：
在所述衬底层的所述底侧上附接第二焊料球；
经由所述第二焊料球将所述第一裸片附接至所述衬底层的所述底侧；以及
在所述第一裸片中提供穿硅通孔以将所述第二焊料球连接至附接于所述第一封装的底侧的第三焊料球。
27.根据权利要求16所述的方法，其中，所述多行焊料球包括第一焊料球，并且所述方法进一步包括：
将第二焊料球附接至所述第一裸片的底侧；以及
将(i)插件或(ii)印刷电路板中的一个耦合至所述第二焊料球。
28.根据权利要求16所述的方法，其中：
所述多行焊料球包括第一多行焊料球；以及
所述方法进一步包括
提供第三封装，所述第三封装具有附接至所述第三封装的底表面的第二多行焊料球，以及
经由所述第二多行焊料球将所述第三封装附接至所述第一封装的所述基本平坦的表面。
CN201480017384.6A 2013-02-11 2014-02-11 封装上封装结构 Pending CN105340078A (zh)

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