CN104967298B - A kind of ripple compensation for DC DC converters controls circuit - Google Patents

Abstract

The invention belongs to the technical field of electronic circuits, and in particular relates to a ripple compensation control circuit for a DC-DC converter. The circuit of the present invention adopts an on-chip compensation technology, by processing the potential information of the switch node SW point to generate AC ripple information that is in phase with the inductor current, and superimposing it on the feedback signal through the ripple compensation control circuit , so as to ensure that the output capacitor ripple with phase lag is weaker than the compensated ripple, and ensure the stable operation of the system; at the same time, it avoids the repeated design of the parameters of the traditional off-chip ripple compensation circuit under different applications, which increases the circuit scope of application.

Description

A Ripple Compensation Control Circuit for DC-DC Converter

technical field

The invention belongs to the technical field of electronic circuits, and in particular relates to a ripple compensation control circuit for a DC-DC converter.

Background technique

Compared with the traditional voltage mode control or current mode control, the control system based on output ripple has the characteristics of faster transient response and simple control loop, especially the ripple control based on constant on-time The potential of adaptive constant frequency characteristics has attracted much attention. However, due to the capacitive characteristics of the output capacitor, the output voltage has a certain phase lag characteristic with respect to the current information, so for all converter systems that directly use the output ripple for control, sufficient output capacitor ESR (equivalent series resistance ) value is a necessary condition for system stability. When the ESR is small, the switching converter system controlled by constant on-time will periodically appear multi-pulse phenomenon, which not only fails to reduce the ripple, but deteriorates the output ripple performance.

In high-performance electronic products, such as CPU, GPU and other high-end functional chips require the power supply voltage ripple to be small enough, and there are strict restrictions on the overall system integration, it is required to use low-ESR, small-volume chip tantalum capacitors or ceramics capacitance. In order to make the system get rid of the limitation of ESR, it is often necessary to compensate the ripple to make up for the lack of ESR ripple, so as to improve the stability of the system when low-value ESR is applied. The traditional compensation method often needs to use more external components to realize ripple compensation, but this will undoubtedly increase the complexity and cost of the system.

Contents of the invention

What the present invention aims to solve is to propose a ripple compensation control circuit for a DC-DC converter in view of the problem of poor stability existing in existing circuits.

To achieve the above object, the present invention adopts the following technical solutions:

A ripple compensation control circuit for a DC-DC converter, comprising a ripple generation circuit, a ripple sampling voltage-current conversion circuit, and a ripple superposition circuit;

As shown in Figure 2, the ripple generating circuit is composed of a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor Composed of resistor R8, first capacitor C1, second capacitor C2, third capacitor C3, fourth capacitor C4, and operational amplifier; external input signals pass through the first resistor R1, second resistor R2, fourth resistor R4, and fifth resistor in turn R5 is connected to the positive input terminal of the operational amplifier; the connection point of the first resistor R1 and the second resistor R2 is grounded after passing through the first capacitor C1; the connection point of the second resistor R2 and the fourth resistor R4 is grounded after passing through the third resistor R3 ; The connection point of the fourth resistor R4 and the fifth resistor R5 is grounded after passing through the second capacitor C2; the connection point of the fifth resistor R5 and the forward input end of the operational amplifier is grounded after passing through the third capacitor C3; the output of the operational amplifier and the operational amplifier The reverse input terminal is connected, and then grounded through the sixth resistor R6 and the seventh resistor R7 in sequence; the connection point of the sixth resistor R6 and the seventh resistor R7 is connected to the first ripple sampling voltage-current conversion circuit through the eighth resistor R8 Input terminal; the connection point of the eighth resistor R8 and the first input terminal of the ripple sampling voltage-current conversion circuit is grounded after passing through the fourth capacitor C4; the connection point of the second resistor R2, the third resistor R3 and the fourth resistor R4 is connected to the ripple sampling the second input terminal of the voltage-current conversion circuit;

As shown in FIG. 3, the ripple sampling voltage-current conversion circuit is composed of a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a sixth PMOS transistor. MP6, the seventh PMOS tube MP7, the eighth PMOS tube MP8, the ninth PMOS tube MP9, the tenth PMOS tube MP10, the eleventh PMOS tube MP11, the twelfth PMOS tube MP12, the thirteenth PMOS tube MP13, the fourteenth PMOS transistor MP14, fifteenth PMOS transistor MP15, sixteenth PMOS transistor MP16, first NMOS transistor MN1, second NMOS transistor MN2, third NMOS transistor MN3, fourth NMOS transistor MN4, fifth NMOS transistor MN5, sixth NMOS transistor MN6, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the first NPN transistor QN1, the second NPN transistor QN2, the first PNP transistor QP1, the second PNP transistor QP2 and the ninth resistor R9; The source of the first PMOS transistor MP1 is connected to the power supply, its grid and drain are interconnected, its grid is connected to the grid of the second PMOS transistor MP2, and its drain is connected to the source of the twelfth PMOS transistor MP12; The gate and drain of the PMOS transistor MP12 are interconnected, and its drain is connected to the drain of the second NMOS transistor MN2; the gate of the second NMOS transistor MN2 is connected to the gate of the first NMOS transistor MN1, and its source is grounded; The gate and the drain of the NMOS transistor MN1 are interconnected, the drain is connected to the external current I _B , and the source is grounded; the source of the second PMOS transistor MP2 is connected to the power supply, and the drain is connected to the emitter of the first PNP transistor QP1 ; The base of the first PNP transistor is the first input terminal of the ripple sampling voltage-current conversion circuit, and its collector is grounded; the connection point between the drain of the second PMOS transistor MP2 and the emitter of the first PNP transistor QP1 is connected to the first NPN The base of the first NPN transistor QN1; the collector of the first NPN transistor QN1 is connected to the drain of the third PMOS transistor MP3, and its emitter is connected to the drain of the third NMOS transistor MN3; the source of the third PMOS transistor MP3 is connected to the power supply, Its gate and drain are interconnected; the gate of the third NMOS transistor MN3 is interconnected with the gate of the first NMOS transistor MN1, the gate of the second NMOS transistor MN2 and the gate of the fourth NMOS transistor MN4; the third NMOS The source of the tube MN3 is grounded; the connection point between the emitter of the first NPN transistor QN1 and the drain of the third NMOS transistor MN3 is connected to the emitter of the second NPN transistor QN2 and the drain of the fourth NMOS transistor MN4 through the ninth resistor R9 Connection point; the collector of the second NPN transistor QN2 is connected to the drain of the fourth PMOS transistor MP4, and its base is connected to the connection point between the drain of the fifth PMOS transistor MP5 and the emitter of the second PNP transistor QP2; the fourth PMOS transistor The source of MP4 is connected to the power supply, and its gate and drain are interconnected; the base of the second PNP transistor QP2 is a ripple sampling voltage The second input terminal of the piezo-current conversion circuit has its collector grounded; the source of the fifth PMOS transistor MP5 is connected to the power supply, and its grid is connected to the grid of the second PMOS transistor MP2; the source of the sixth PMOS transistor MP6 is connected to the power supply, Its gate is connected to the gate of the third PMOS transistor MP3, and its drain is connected to the source of the thirteenth PMOS transistor MP13; the gate of the thirteenth PMOS transistor MP13 is connected to the gate of the fourteenth PMOS transistor MP14, and its drain connected to the drain of the fifth NMOS transistor MN5; the gate and drain of the fifth NMOS transistor MN5 are interconnected, the gate is connected to the gate of the sixth NMOS transistor MN6, and its source is grounded; the source of the sixth NMOS transistor MN6 Grounded, its drain connected to the drain of the fourteenth PMOS transistor MP14; the source of the fourteenth PMOS transistor MP14 connected to the drain of the seventh PMOS transistor and the drain of the eighth PMOS transistor MP8; the source of the seventh PMOS transistor MP7 The pole is connected to the power supply, and its grid is connected to the grid of the fourth PMOS transistor MP4; the source of the eighth PMOS transistor MP8 is connected to the power supply, and its grid is connected to the grid of the fifth PMOS transistor MP5; the source of the ninth PMOS transistor MP9 is connected to Power supply, its grid is connected to the grid of the third PMOS transistor MP3, its drain is connected to the source of the fifteenth PMOS transistor MP15; the grid of the fifteenth PMOS transistor MP15 is connected to the grid of the twelfth PMOS transistor MP12, its The drain is connected to the drain of the seventh NMOS transistor MN7; the gate and drain of the seventh NMOS transistor MN7 are interconnected, the gate is connected to the gate of the eighth NMOS transistor MN8, and the source is grounded; the gate of the eighth NMOS transistor MN8 The source is grounded, and its drain is connected to the drain of the sixteenth PMOS transistor MP16; the gate of the sixteenth PMOS transistor MP16 is connected to the gate of the fifteenth PMOS transistor MP15, and its source is connected to the drain of the tenth PMOS transistor MP10 and the drain of the eleventh PMOS transistor MP11; the source of the tenth PMOS transistor MP10 is connected to the power supply, and its grid is connected to the grid of the seventh PMOS transistor MP7; the source of the eleventh PMOS transistor MP11 is connected to the power supply, and its grid connected to the gate of the eighth PMOS transistor MP8; the connection point between the drain of the fourteenth PMOS transistor MP14 and the drain of the sixth NMOS transistor MN6 is the first output end of the ripple sampling voltage-current conversion circuit, and the drain of the sixteenth PMOS transistor MP16 The connection point between the pole and the drain of the eighth NMOS transistor MN8 is the second output terminal of the ripple sampling voltage-current conversion circuit;

As shown in FIG. 5, the ripple superposition circuit is composed of the seventeenth PMOS transistor MP17, the eighteenth PMOS transistor MP18, the nineteenth PMOS transistor MP19, the twentieth PMOS transistor MP20, the twenty-first PMOS transistor MP21, the The second is the second PMOS tube MP22, the twenty-third PMOS tube MP23, the twenty-fourth PMOS tube MP24, the twenty-fifth PMOS tube MP25, the twenty-sixth PMOS tube MP26, the twenty-seventh PMOS tube MP27, the twenty-first Eight PMOS transistors MP28, twenty-ninth PMOS transistors MP29, thirty PMOS transistors MP30, ninth NMOS transistors MN9, tenth NMOS transistors MN10, eleventh NMOS transistors MMN11, third PNP transistors QP3, fourth PNP transistors Transistor QP4, fifth PNP transistor QP5, sixth PNP transistor QP6, tenth resistor R10, eleventh resistor R11, twelfth resistor R12, thirteenth resistor R13, fourteenth resistor R14, fifteenth resistor R15, the sixteenth resistor R16, the seventeenth resistor R17, the eighteenth resistor R18, the nineteenth resistor R19, the twentieth resistor R20, the twenty-first resistor R21, the first current source I _B1 , the second current source I _B2 and the third current source I _B3 constitute; the source of the seventeenth PMOS transistor MP17 is connected to the power supply, its grid and drain are interconnected, and its drain is connected to the positive pole of the first current source I _B1 ; the first current source I The negative electrode of _B1 is grounded; the gate of the seventeenth PMOS transistor MP17, the gate of the eighteenth PMOS transistor MP18, and the gate of the nineteenth PMOS transistor MP19 are interconnected; the source of the eighteenth PMOS transistor MP18 is connected to the power supply, and The drain is connected to the drain of the nineteenth PMOS transistor MP19; the source of the nineteenth PMOS transistor MP19 is connected to the power supply, and its drain is connected to the drain of the twentieth PMOS transistor MP20; the source of the twentieth PMOS transistor MP20 is connected to the power supply , its drain is connected to the drain of the twenty-first PMOS transistor MP21; the source of the twenty-first PMOS transistor MP21 is connected to the power supply, its gate is connected to the gate of the twenty-second PMOS transistor MP22, and its drain is connected to the second The source of the eighteenth PMOS transistor MP28; the grid of the twenty-eighth PMOS transistor MP28 is connected to the grid of the twenty-ninth PMOS transistor MP29, and its drain is connected to the emitter of the sixth PNP transistor QP6; the sixth PNP transistor The base of QP6 is connected to the drain of the ninth NMOS transistor MN9, and its collector is grounded; the gate and drain of the ninth NMOS transistor MN9 are interconnected, and its source is grounded; the source of the twenty-second PMOS transistor MP22 is connected to the power supply , the drain of which is connected to the source of the twenty-ninth PMOS transistor MP29; the drain of the twenty-ninth PMOS transistor MP29 passes through the eleventh resistor R11 and the thirteenth resistor R13 in turn, and then is connected to the emitter of the fifth PNP transistor QP5 ; The connection point of the eleventh resistor R11 and the thirteenth resistor R13 is connected to the first output terminal of the ripple sampling voltage-current conversion circuit; the thirteenth resistor R13 and the fifth PNP transistor Q The connection point of the P5 emitter connects the drain of the twenty-third PMOS transistor MP23; the source of the twenty-third PMOS transistor MP23 connects to the power supply; the base of the fifth PNP type three-stage dry QP5 passes through the eighteenth resistor R18 and The fourteenth resistor R14 is connected to the feedback voltage VFB, and its collector is grounded; the connection point of the eighteenth resistor R18 and the fourteenth resistor R14 is connected to the drain of the tenth NMOS transistor MN10 through the twentieth resistor R20; the tenth NMOS The gate of the transistor MN10, the gate of the eleventh NMOS transistor MN11 and the gate of the ninth NMOS transistor MN9 are interconnected; the source of the tenth NMOS transistor MN10 is grounded; the drain of the eleventh NMOS transistor MN11 passes through the second The eleventh resistor R21 and the sixteenth resistor R16 are connected to the reference voltage Vref, and their source is grounded; the connection point of the twenty-first resistor R21 and the sixteenth resistor R16 is connected to the eighteenth resistor R18 and the tenth resistor through the fifth capacitor C5 The connection point of the four resistors R14; the connection point of the twenty-first resistor R21 and the sixteenth resistor R16 is connected to the base of the third PNP transistor QP3 through the nineteenth resistor R19; the emitter of the third PNP transistor QP3 passes through The fifteenth resistor R15 and the twelfth resistor R12 are connected to the drain of the thirtieth PMOS transistor MP30, and its collector is grounded; The gate of the PMOS transistor MP29 is interconnected; the source of the thirtieth PMOS transistor MP30 is connected to the drain of the twenty-fifth PMOS transistor MP25; the gate of the twenty-fifth PMOS transistor MP25 is connected to the gate of the twenty-sixth PMOS transistor MP26 pole, the gate of the twenty-first PMOS transistor MP21 and the gate of the twenty-second PMOS transistor MP22 are interconnected; the source of the twenty-fifth PMOS transistor MP25 is connected to the power supply; the emitter of the third PNP transistor QP3 is connected to the tenth The connection point of the fifth resistor R15 is connected to the second output terminal of the ripple sampling voltage-current conversion circuit; the connection point of the twelfth resistor R12 and the fifteenth resistor R15 is connected to the drain of the twenty-fourth PMOS transistor MP24; the twenty-fourth The grid of the PMOS transistor MP24, the grid of the twenty-third PMOS transistor MP23, the grid of the twentieth PMOS transistor MP20, and the grid of the twenty-seventh PMOS transistor MP27 are interconnected; the source of the twenty-fourth PMOS transistor MP24 The pole is connected to the power supply; the connection point of the twelfth resistor R12 and the fifteenth resistor R15 passes through the seventeenth resistor R17 and then connects to the emitter of the fourth PNP transistor QP4; the base of the fourth PNP transistor QP4 passes through the tenth resistor R10 The back is the output terminal of the ripple superposition circuit, and its collector is grounded; the source of the twenty-sixth PMOS tube MP26 is connected to the power supply, its grid and drain are interconnected, and its drain is connected to the positive pole of the second current source I _B2 ; The negative electrode of the second current source I _B2 is grounded; the source electrode of the twenty-seventh PMOS transistor MP27 is connected to the power supply, its grid and drain are interconnected, and its drain is connected to the positive electrode of the third current source I _B3 ; the third current source I The negative pole of _B3 is grounded.

The invention has the beneficial effects of overcoming the problems of complex structure and large occupied area in the traditional off-chip compensation method, reducing the overall cost of the converter, increasing the application range of the circuit, improving the circuit precision, and reducing the power consumption of the circuit.

Description of drawings

Fig. 1 is a system schematic diagram of the present invention;

Figure 2 is a schematic diagram of the on-chip ripple generation circuit;

Fig. 3 is the structural diagram of the ripple sampling voltage-current conversion circuit;

Fig. 4 is a schematic diagram of a ripple sampling waveform;

Fig. 5 is a structure diagram of a ripple superposition circuit;

FIG. 6 is a schematic diagram of a VFB DC level compensation waveform.

detailed description

The traditional off-chip slope compensation circuit uses discrete components to build a slope generating circuit at both ends of the converter inductance to achieve a ripple signal that meets the requirements and has the same frequency and phase as the inductor current, and is finally superimposed on the feedback signal end to ensure The system can work stably. However, the ramp signal generated by this circuit cannot reflect the real information of the inductor current, and the values of the compensation resistor and capacitor are usually large, so the applicability of this method is limited, and usually requires a large area, resulting in an increase in cost.

As shown in Figure 1, SW is the switch output node of the system, and the output V _OUT is divided by resistors Rf1 and Rf2 to obtain the feedback voltage V _FB . The present invention adopts a kind of on-chip compensation technology, obtains the sawtooth wave including DC information and inductance current information by filtering the potential information of SW, and uses the DC component extraction circuit to extract its DC component (the average value of SW point reflects the output voltage V _OUT ); and then use the subtraction circuit to make a difference to extract its AC component, that is, to obtain the required ripple information in the same direction as the inductor current. Then add it to the feedback signal V _FB through the ripple superposition circuit, so as to ensure that the ripple of the output capacitor with phase lag is weaker than the ripple after compensation, so as to ensure the stable operation of the system; at the same time, it avoids the traditional on-chip The parameters of the external ripple compensation circuit need to be designed repeatedly, which increases the scope of application of the circuit.

A ripple compensation control circuit for a DC-DC converter of the present invention specifically includes a ripple generation circuit, a ripple sampling voltage-current conversion circuit, and a ripple superposition circuit. The technology of the present invention will be described in detail below in conjunction with the accompanying drawings plan:

As shown in Figure 2, the ripple generating circuit is composed of a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor Composed of resistor R8, first capacitor C1, second capacitor C2, third capacitor C3, fourth capacitor C4, and operational amplifier; external input signals pass through the first resistor R1, second resistor R2, fourth resistor R4, and fifth resistor in turn R5 is connected to the positive input terminal of the operational amplifier; the connection point of the first resistor R1 and the second resistor R2 is grounded after passing through the first capacitor C1; the connection point of the second resistor R2 and the fourth resistor R4 is grounded after passing through the third resistor R3 ; The connection point of the fourth resistor R4 and the fifth resistor R5 is grounded after passing through the second capacitor C2; the connection point of the fifth resistor R5 and the forward input end of the operational amplifier is grounded after passing through the third capacitor C3; the output of the operational amplifier and the operational amplifier The reverse input terminal is connected, and then grounded through the sixth resistor R6 and the seventh resistor R7 in sequence; the connection point of the sixth resistor R6 and the seventh resistor R7 is connected to the first ripple sampling voltage-current conversion circuit through the eighth resistor R8 Input terminal; the connection point of the eighth resistor R8 and the first input terminal of the ripple sampling voltage-current conversion circuit is grounded after passing through the fourth capacitor C4; the connection point of the second resistor R2, the third resistor R3 and the fourth resistor R4 is connected to the ripple sampling the second input terminal of the voltage-current conversion circuit;

As shown in FIG. 3, the ripple sampling voltage-current conversion circuit is composed of a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a sixth PMOS transistor. MP6, the seventh PMOS tube MP7, the eighth PMOS tube MP8, the ninth PMOS tube MP9, the tenth PMOS tube MP10, the eleventh PMOS tube MP11, the twelfth PMOS tube MP12, the thirteenth PMOS tube MP13, the fourteenth PMOS transistor MP14, fifteenth PMOS transistor MP15, sixteenth PMOS transistor MP16, first NMOS transistor MN1, second NMOS transistor MN2, third NMOS transistor MN3, fourth NMOS transistor MN4, fifth NMOS transistor MN5, sixth NMOS transistor MN6, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the first NPN transistor QN1, the second NPN transistor QN2, the first PNP transistor QP1, the second PNP transistor QP2 and the ninth resistor R9; The source of the first PMOS transistor MP1 is connected to the power supply, its grid and drain are interconnected, its grid is connected to the grid of the second PMOS transistor MP2, and its drain is connected to the source of the twelfth PMOS transistor MP12; The gate and drain of the PMOS transistor MP12 are interconnected, and its drain is connected to the drain of the second NMOS transistor MN2; the gate of the second NMOS transistor MN2 is connected to the gate of the first NMOS transistor MN1, and its source is grounded; The gate and the drain of the NMOS transistor MN1 are interconnected, the drain is connected to the external current I _B , and the source is grounded; the source of the second PMOS transistor MP2 is connected to the power supply, and the drain is connected to the emitter of the first PNP transistor QP1 ; The base of the first PNP transistor is the first input terminal of the ripple sampling voltage-current conversion circuit, and its collector is grounded; the connection point between the drain of the second PMOS transistor MP2 and the emitter of the first PNP transistor QP1 is connected to the first NPN The base of the first NPN transistor QN1; the collector of the first NPN transistor QN1 is connected to the drain of the third PMOS transistor MP3, and its emitter is connected to the drain of the third NMOS transistor MN3; the source of the third PMOS transistor MP3 is connected to the power supply, Its gate and drain are interconnected; the gate of the third NMOS transistor MN3 is interconnected with the gate of the first NMOS transistor MN1, the gate of the second NMOS transistor MN2 and the gate of the fourth NMOS transistor MN4; the third NMOS The source of the tube MN3 is grounded; the connection point between the emitter of the first NPN transistor QN1 and the drain of the third NMOS transistor MN3 is connected to the emitter of the second NPN transistor QN2 and the drain of the fourth NMOS transistor MN4 through the ninth resistor R9 Connection point; the collector of the second NPN transistor QN2 is connected to the drain of the fourth PMOS transistor MP4, and its base is connected to the connection point between the drain of the fifth PMOS transistor MP5 and the emitter of the second PNP transistor QP2; the fourth PMOS transistor The source of MP4 is connected to the power supply, and its gate and drain are interconnected; the base of the second PNP transistor QP2 is a ripple sampling voltage The second input terminal of the piezo-current conversion circuit has its collector grounded; the source of the fifth PMOS transistor MP5 is connected to the power supply, and its grid is connected to the grid of the second PMOS transistor MP2; the source of the sixth PMOS transistor MP6 is connected to the power supply, Its gate is connected to the gate of the third PMOS transistor MP3, and its drain is connected to the source of the thirteenth PMOS transistor MP13; the gate of the thirteenth PMOS transistor MP13 is connected to the gate of the fourteenth PMOS transistor MP14, and its drain connected to the drain of the fifth NMOS transistor MN5; the gate and drain of the fifth NMOS transistor MN5 are interconnected, the gate is connected to the gate of the sixth NMOS transistor MN6, and its source is grounded; the source of the sixth NMOS transistor MN6 Grounded, its drain connected to the drain of the fourteenth PMOS transistor MP14; the source of the fourteenth PMOS transistor MP14 connected to the drain of the seventh PMOS transistor and the drain of the eighth PMOS transistor MP8; the source of the seventh PMOS transistor MP7 The pole is connected to the power supply, and its grid is connected to the grid of the fourth PMOS transistor MP4; the source of the eighth PMOS transistor MP8 is connected to the power supply, and its grid is connected to the grid of the fifth PMOS transistor MP5; the source of the ninth PMOS transistor MP9 is connected to Power supply, its grid is connected to the grid of the third PMOS transistor MP3, its drain is connected to the source of the fifteenth PMOS transistor MP15; the grid of the fifteenth PMOS transistor MP15 is connected to the grid of the twelfth PMOS transistor MP12, its The drain is connected to the drain of the seventh NMOS transistor MN7; the gate and drain of the seventh NMOS transistor MN7 are interconnected, the gate is connected to the gate of the eighth NMOS transistor MN8, and the source is grounded; the gate of the eighth NMOS transistor MN8 The source is grounded, and its drain is connected to the drain of the sixteenth PMOS transistor MP16; the gate of the sixteenth PMOS transistor MP16 is connected to the gate of the fifteenth PMOS transistor MP15, and its source is connected to the drain of the tenth PMOS transistor MP10 and the drain of the eleventh PMOS transistor MP11; the source of the tenth PMOS transistor MP10 is connected to the power supply, and its grid is connected to the grid of the seventh PMOS transistor MP7; the source of the eleventh PMOS transistor MP11 is connected to the power supply, and its grid connected to the gate of the eighth PMOS transistor MP8; the connection point between the drain of the fourteenth PMOS transistor MP14 and the drain of the sixth NMOS transistor MN6 is the first output end of the ripple sampling voltage-current conversion circuit, and the drain of the sixteenth PMOS transistor MP16 The connection point between the pole and the drain of the eighth NMOS transistor MN8 is the second output terminal of the ripple sampling voltage-current conversion circuit;

As shown in FIG. 5, the ripple superposition circuit is composed of the seventeenth PMOS transistor MP17, the eighteenth PMOS transistor MP18, the nineteenth PMOS transistor MP19, the twentieth PMOS transistor MP20, the twenty-first PMOS transistor MP21, the The second is the second PMOS tube MP22, the twenty-third PMOS tube MP23, the twenty-fourth PMOS tube MP24, the twenty-fifth PMOS tube MP25, the twenty-sixth PMOS tube MP26, the twenty-seventh PMOS tube MP27, the twenty-first Eight PMOS transistors MP28, twenty-ninth PMOS transistors MP29, thirty PMOS transistors MP30, ninth NMOS transistors MN9, tenth NMOS transistors MN10, eleventh NMOS transistors MMN11, third PNP transistors QP3, fourth PNP transistors Transistor QP4, fifth PNP transistor QP5, sixth PNP transistor QP6, tenth resistor R10, eleventh resistor R11, twelfth resistor R12, thirteenth resistor R13, fourteenth resistor R14, fifteenth resistor R15, the sixteenth resistor R16, the seventeenth resistor R17, the eighteenth resistor R18, the nineteenth resistor R19, the twentieth resistor R20, the twenty-first resistor R21, the first current source I _B1 , the second current source I _B2 and the third current source I _B3 constitute; the source of the seventeenth PMOS transistor MP17 is connected to the power supply, its grid and drain are interconnected, and its drain is connected to the positive pole of the first current source I _B1 ; the first current source I The negative electrode of _B1 is grounded; the gate of the seventeenth PMOS transistor MP17, the gate of the eighteenth PMOS transistor MP18, and the gate of the nineteenth PMOS transistor MP19 are interconnected; the source of the eighteenth PMOS transistor MP18 is connected to the power supply, and The drain is connected to the drain of the nineteenth PMOS transistor MP19; the source of the nineteenth PMOS transistor MP19 is connected to the power supply, and its drain is connected to the drain of the twentieth PMOS transistor MP20; the source of the twentieth PMOS transistor MP20 is connected to the power supply , its drain is connected to the drain of the twenty-first PMOS transistor MP21; the source of the twenty-first PMOS transistor MP21 is connected to the power supply, its gate is connected to the gate of the twenty-second PMOS transistor MP22, and its drain is connected to the second The source of the eighteenth PMOS transistor MP28; the grid of the twenty-eighth PMOS transistor MP28 is connected to the grid of the twenty-ninth PMOS transistor MP29, and its drain is connected to the emitter of the sixth PNP transistor QP6; the sixth PNP transistor The base of QP6 is connected to the drain of the ninth NMOS transistor MN9, and its collector is grounded; the gate and drain of the ninth NMOS transistor MN9 are interconnected, and its source is grounded; the source of the twenty-second PMOS transistor MP22 is connected to the power supply , the drain of which is connected to the source of the twenty-ninth PMOS transistor MP29; the drain of the twenty-ninth PMOS transistor MP29 passes through the eleventh resistor R11 and the thirteenth resistor R13 in turn, and then is connected to the emitter of the fifth PNP transistor QP5 ; The connection point of the eleventh resistor R11 and the thirteenth resistor R13 is connected to the first output terminal of the ripple sampling voltage-current conversion circuit; the thirteenth resistor R13 and the fifth PNP transistor Q The connection point of the P5 emitter connects the drain of the twenty-third PMOS transistor MP23; the source of the twenty-third PMOS transistor MP23 connects to the power supply; the base of the fifth PNP type three-stage dry QP5 passes through the eighteenth resistor R18 and The fourteenth resistor R14 is connected to the feedback voltage VFB, and its collector is grounded; the connection point of the eighteenth resistor R18 and the fourteenth resistor R14 is connected to the drain of the tenth NMOS transistor MN10 through the twentieth resistor R20; the tenth NMOS The gate of the transistor MN10, the gate of the eleventh NMOS transistor MN11 and the gate of the ninth NMOS transistor MN9 are interconnected; the source of the tenth NMOS transistor MN10 is grounded; the drain of the eleventh NMOS transistor MN11 passes through the second The eleventh resistor R21 and the sixteenth resistor R16 are connected to the reference voltage Vref, and their source is grounded; the connection point of the twenty-first resistor R21 and the sixteenth resistor R16 is connected to the eighteenth resistor R18 and the tenth resistor through the fifth capacitor C5 The connection point of the four resistors R14; the connection point of the twenty-first resistor R21 and the sixteenth resistor R16 is connected to the base of the third PNP transistor QP3 through the nineteenth resistor R19; the emitter of the third PNP transistor QP3 passes through The fifteenth resistor R15 and the twelfth resistor R12 are connected to the drain of the thirtieth PMOS transistor MP30, and its collector is grounded; The gate of the PMOS transistor MP29 is interconnected; the source of the thirtieth PMOS transistor MP30 is connected to the drain of the twenty-fifth PMOS transistor MP25; the gate of the twenty-fifth PMOS transistor MP25 is connected to the gate of the twenty-sixth PMOS transistor MP26 pole, the gate of the twenty-first PMOS transistor MP21 and the gate of the twenty-second PMOS transistor MP22 are interconnected; the source of the twenty-fifth PMOS transistor MP25 is connected to the power supply; the emitter of the third PNP transistor QP3 is connected to the tenth The connection point of the fifth resistor R15 is connected to the second output terminal of the ripple sampling voltage-current conversion circuit; the connection point of the twelfth resistor R12 and the fifteenth resistor R15 is connected to the drain of the twenty-fourth PMOS transistor MP24; the twenty-fourth The grid of the PMOS transistor MP24, the grid of the twenty-third PMOS transistor MP23, the grid of the twentieth PMOS transistor MP20, and the grid of the twenty-seventh PMOS transistor MP27 are interconnected; the source of the twenty-fourth PMOS transistor MP24 The pole is connected to the power supply; the connection point of the twelfth resistor R12 and the fifteenth resistor R15 passes through the seventeenth resistor R17 and then connects to the emitter of the fourth PNP transistor QP4; the base of the fourth PNP transistor QP4 passes through the tenth resistor R10 The back is the output terminal of the ripple superposition circuit, and its collector is grounded; the source of the twenty-sixth PMOS tube MP26 is connected to the power supply, its grid and drain are interconnected, and its drain is connected to the positive pole of the second current source I _B2 ; The negative electrode of the second current source I _B2 is grounded; the source electrode of the twenty-seventh PMOS transistor MP27 is connected to the power supply, its grid and drain are interconnected, and its drain is connected to the positive electrode of the third current source I _B3 ; the third current source I The negative pole of _B3 is grounded.

Working principle of the present invention is:

The schematic diagram of the ripple generation circuit of the present invention is shown in Figure 2. The module first divides the SW signal through the first-order filter of the RC_Filter to obtain V _{SW_F1} that contains ripples similar to the inductor current. After the third-order filter divides the voltage to obtain the same V _out is proportional and relatively stable V _{SW_F3} , and V _{SW_DC} is obtained through the buff in the form of unity gain negative feedback connection and the RC filter composed of R8 and C4 (used to filter out high-frequency burrs). As shown in Figure 4, the DC component of V _{SW_F1} is V _{SW_F3} , and the AC component is assumed to be v _ripple . According to Figure 2, the first output V _{SW_DC} and the second output V _{SW_F1} of the ripple generating circuit can be obtained:

Finally, the difference between V _{SW_DC} and V _{SW_F1} is made by a voltage-current converter to obtain currents I _OUT1 and I _OUT2 including ripple information, which are sent to the ripple superposition module.

The specific structure of the voltage-current conversion circuit in Fig. 2 is shown in Fig. 3 . This circuit converts the difference of V _{SW_DC} and V _{SW_F1} into a ripple current containing inductance information. Assuming that the voltage of SW_F1 is slightly greater than SW_DC, the emitter currents of transistors QN1 and QN2 are I ₂ and I ₁ respectively; the currents on MN3 and MN4 are mirrored by the current mirror 1:1, and its size is I ₀ , then:

I ₁ =I ₀ +I _R9 ; I ₂ =I ₀ -I _R9 ;

There is a current mirror image ratio relationship with

I _B is the external input current;

and

can get

so

That is, I _OUT1 ＝I _OUT2 ＝i _ripple +I _B +△I

According to the above analysis, the waveform schematic diagram of the ripple current shown in Figure 4 can be obtained, and it can be seen from the formula that the magnitude of the generated ripple current can be changed by changing the size of the resistor R9. Finally, the obtained ripple current including the inductor current information is superimposed on the feedback signal V _FB . Among them, the current I _B is used in the post-superposition circuit to ensure that the same DC level is superimposed on V _FB and _VRef , and ΔI is used for V _FB DC level compensation to ensure the accuracy of the output.

The circuit diagram of the ripple superposition module is shown in Figure 5. The currents of the current sources I _B1 , I _B2 , and I _B3 are all I _B , and the resistors R18, R19, R20, and R21 are used to determine the static operating point of the circuit. R14, R16, and C5 form a filter network to filter out high-frequency noise. After the system is powered on, V _FB and V _{SS_OUT are} low at this time, transistor QP3 is turned off, QP4 is turned on, and VSS_OUT replaces V _Ref to participate in the comparison of the subsequent stage to achieve soft start and avoid excessive inrush current. In terms of parameter design, the resistance of R7 is slightly lower than that of R3 to ensure that V1 is slightly greater than V2 at the beginning of the soft start, and then V _{SS_OUT} rises, V2 exceeds V1, and the comparator in the latter stage is flipped to ensure the first On_Time trigger of the system. As the voltage of V _{SS_OUT} rises gradually, the transistor QP3 is gradually turned on; when V _{SS_OUT} is greater than the V _Ref signal, QP4 is turned off, and the soft start ends.

In order to eliminate the influence of the base current of the pnp tube on V _Ref and V _FB , the present invention generates a base current close to the size of QP4 and QP3 at the place where the triode QP5 is generated by adding an extra branch, through the current mirrors MN9, MN10, and MN11. The base current of QP5 and QP3 is compensated to ensure the accuracy of V _FB sampling. After the soft start, when the circuit is working normally, it can be known from the current relationship in the schematic diagram of the sampling module that the current flowing through the triode QP5 and QP3 is 3I _B +i _ripple +ΔI, and R18=R19, and the triode QP6 and QP5 , QP3 are the same, let its current amplification factor be β, so:

V _EB5 =V _EB3 ; V _R18 =V _R19

The current on resistor R18 is The mirror image of the current on the resistor R20 through the current mirror MN9, MN10, MN11 is Then the current flowing to the V _FB external voltage dividing resistor Rf2 is:

I _B 'is used to eliminate the error caused by V _{SW_DC} from the voltage dividing resistor in the previous stage, and its size is equivalent to the size of △I. Selecting the appropriate resistor R and transistor amplification factor β can ignore the influence caused by I _Rf2 ' on V _FB and ensure the accuracy of the output. According to the current relationship in Figure 5, it can also be obtained:

V _R13 ＝(i _ripple +2I _B +△I)×R13

V _R15 = 2I _B × R15

Then the expressions of outputting V ₁ and V ₂ are:

V ₁ ＝V _FB +V _R18 +V _EB5 +V _R13

V ₂ ＝V _Ref +V _R19 +V _EB3 +V _R15

And R13=R15, so

V ₁ -V ₂ ＝V _FB +(i _ripple +△I)×R13-V _Ref ＝V _FB +△V+i _ripple ×R13-V _Ref

in

The voltages V ₁ and V ₂ are respectively sent to the input terminals of the subsequent comparator to complete the comparison of the superimposed signal of the ripple information of V _FB and the inductor circuit in the same direction with V _Ref to ensure the stability of the system. The average value of the valley-triggered COT output is actually slightly larger than V _Ref in the present invention, which causes an error in the output DC value. From the superimposed waveform in Figure 6, it can be seen that when V ₁ and V ₂ are compared, it is actually V _FB +△V+i _ripple ×R13 that is compared with V _Ref , and the output can be guaranteed by setting parameters reasonably precision.

The invention has the beneficial effects of designing an on-chip feedback ripple compensation circuit to get rid of the dependence of the COT control system on the size of the output capacitor ESR, and widen the optional range of output capacitor components. The on-chip compensation technology adopted in the present invention avoids the off-chip large resistance and large capacitance required by the traditional slope compensation technology, and increases the scope of application of the circuit; at the same time, the compensation ripple includes the information of the inductor current ripple, ensuring The stability of the circuit is improved; in addition, the method of DC level compensation improves the DC error of the traditional COT and improves the circuit accuracy.

Claims (1)

1. a kind of ripple compensation for DC-DC converter controls circuit, including line wave generation circuit, ripple sampled voltage electric current Change-over circuit and ripple supercircuit；

The line wave generation circuit is by by first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C3, the 4th electric capacity C4, operational amplifier are constituted；External input signal passes sequentially through first resistor R1, second resistance R2, the 4th resistance R4, the 5th electricity Resistance R5 is followed by the positive input of operational amplifier；The tie point of first resistor R1 and second resistance R2 is by after the first electric capacity C1 Ground connection；The tie point of second resistance R2 and the 4th resistance R4 after 3rd resistor R3 by being grounded；4th resistance R4 and the 5th resistance The tie point of R5 after the second electric capacity C2 by being grounded；The tie point of the 5th resistance R5 and operational amplifier positive input is by the It is grounded after three electric capacity C3；The output of operational amplifier is connected with the reverse input end of operational amplifier, and passes sequentially through the 6th electricity It is grounded after resistance R6 and the 7th resistance R7；The tie point of the 6th resistance R6 and the 7th resistance R7 is followed by ripple and adopts by the 8th resistance R8 The first input end of sample voltage-current converter circuit；8th resistance R8 and ripple sampled voltage current converter circuit first input end Tie point by after the 4th electric capacity C4 be grounded；The tie point of second resistance R2,3rd resistor R3 and the 4th resistance R4 connects ripple Second input of sampled voltage current converter circuit；

The ripple sampled voltage current converter circuit by the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, the 7th PMOS MP7, the 8th PMOS MP8, the 9th PMOS MP9, the tenth PMOS MP10, the 11st PMOS MP11, the 12nd PMOS MP12, the 13rd PMOS MP13, 14th PMOS MP14, the 15th PMOS MP15, the 16th PMOS MP16, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, Eight NMOS tube MN8, the first NPN type triode QN1, the second NPN type triode QN2, the first PNP type triode QP1, the 2nd PNP Type triode QP2 and the 9th resistance R9 is constituted；The source electrode of the first PMOS MP1 connects power supply, its grid and drain interconnection, its grid The grid of the second PMOS MP2 is connect, its drain electrode connects the source electrode of the 12nd PMOS MP12；The grid of the 12nd PMOS MP12 and Drain interconnection, its drain electrode connects the drain electrode of the second NMOS tube MN2；The grid of the second NMOS tube MN2 connects the grid of the first NMOS tube MN1 Pole, its source ground；The grid and drain interconnection of the first NMOS tube MN1, its drain electrode meet foreign current I_B, its source ground；The The source electrode of two PMOS MP2 connects power supply, and its drain electrode connects the emitter stage of the first PNP type triode QP1；First PNP type triode Base stage is the first input end of ripple sampled voltage current converter circuit, its grounded collector；Second PMOS MP2 drains and the The tie point of one PNP type triode QP1 emitter stages connects the base stage of the first NPN type triode QN1；First NPN type triode QN1's Colelctor electrode connects the drain electrode of the 3rd PMOS MP3, and its emitter stage connects the drain electrode of the 3rd NMOS tube MN3；The source electrode of the 3rd PMOS MP3 Power supply is connect, its grid and drain interconnection；The grid of the grid of the 3rd NMOS tube MN3 and the first NMOS tube MN1, the second NMOS tube The gate interconnection of the grid of MN2 and the 4th NMOS tube MN4；The source ground of the 3rd NMOS tube MN3；First NPN type triode QN1 Emitter stage and the 3rd NMOS tube MN3 drain electrode tie point by the 9th resistance R9 be followed by the second NPN type triode QN2 emitter stages and The tie point of the 4th NMOS tube MN4 drain electrodes；The colelctor electrode of the second NPN type triode QN2 connects the drain electrode of the 4th PMOS MP4, its Base stage connects the tie point of the 5th PMOS MP5 drain electrodes and the second PNP type triode QP2 emitter stages；The source electrode of the 4th PMOS MP4 Power supply is connect, its grid and drain interconnection；The base stage of the second PNP type triode QP2 is ripple sampled voltage current converter circuit Second input, its grounded collector；The source electrode of the 5th PMOS MP5 connects power supply, and its grid connects the grid of the second PMOS MP2 Pole；The source electrode of the 6th PMOS MP6 connects power supply, and its grid connects the grid of the 3rd PMOS MP3, and its drain electrode connects the 13rd PMOS The source electrode of MP13；The grid of the 13rd PMOS MP13 connects the grid of the 14th PMOS MP14, and its drain electrode connects the 5th NMOS tube The drain electrode of MN5；The grid and drain interconnection of the 5th NMOS tube MN5, its grid connect the grid of the 6th NMOS tube MN6, and its source electrode connects Ground；The source ground of the 6th NMOS tube MN6, its drain electrode connects the drain electrode of the 14th PMOS MP14；14th PMOS MP14's Source electrode connects the drain electrode of the 7th PMOS and the drain electrode of the 8th PMOS MP8；The source electrode of the 7th PMOS MP7 connects power supply, its grid Connect the grid of the 4th PMOS MP4；The source electrode of the 8th PMOS MP8 connects power supply, and its grid connects the grid of the 5th PMOS MP5； The source electrode of the 9th PMOS MP9 connects power supply, and its grid connects the grid of the 3rd PMOS MP3, and its drain electrode connects the 15th PMOS The source electrode of MP15；The grid of the 15th PMOS MP15 connects the grid of the 12nd PMOS MP12, and its drain electrode connects the 7th NMOS tube The drain electrode of MN7；The grid and drain interconnection of the 7th NMOS tube MN7, its grid connect the grid of the 8th NMOS tube MN8, and its source electrode connects Ground；The source ground of the 8th NMOS tube MN8, its drain electrode connects the drain electrode of the 16th PMOS MP16；16th PMOS MP16's Grid connects the grid of the 15th PMOS MP15, and its source electrode connects the drain electrode of the tenth PMOS MP10 with the 11st PMOS MP11's Drain electrode；The source electrode of the tenth PMOS MP10 connects power supply, and its grid connects the grid of the 7th PMOS MP7；11st PMOS MP11 Source electrode connect power supply, its grid connects the grid of the 8th PMOS MP8；14th PMOS MP14 drains and the 6th NMOS tube MN6 The tie point of drain electrode is the first output end of ripple sampled voltage current converter circuit, the 16th PMOS MP16 drain electrodes and the 8th The tie point of NMOS tube MN8 drain electrodes is the second output end of ripple sampled voltage current converter circuit；

The ripple supercircuit is by the 17th PMOS MP17, the 18th PMOS MP18, the 19th PMOS MP19, second Ten PMOS MP20, the 21st PMOS MP21, second are two PMOS MP22, the 23rd PMOS MP23, the 20th Four PMOS MP24, the 25th PMOS MP25, the 26th PMOS MP26, the 27th PMOS MP27, the 20th Eight PMOS MP28, the 29th PMOS MP29, the 30th PMOS MP30, the 9th NMOS tube MN9, the tenth NMOS tube MN10, the 11st NMOS tube MMN11, the 3rd PNP type triode QP3, the 4th PNP type triode QP4, the 5th PNP type triode QP5, the 6th PNP type triode QP6, the tenth resistance R10, the 11st resistance R11, the 12nd resistance R12, the 13rd resistance R13, 14th resistance R14, the 15th resistance R15, the 16th resistance R16, the 17th resistance R17, the 18th resistance R18, the 19th Resistance R19, the 20th resistance R20, the 21st resistance R21, the first current source I_B1, the second current source I_B2With the 3rd current source I_B3Constitute；The source electrode of the 17th PMOS MP17 connects power supply, its grid and drain interconnection, and its drain electrode meets the first current source I_B1's Positive pole；First current source I_B1Negative pole ground connection；The grid of the 17th PMOS MP17, the grid of the 18th PMOS MP18 and The gate interconnection of 19 PMOS MP19；The source electrode of the 18th PMOS MP18 connects power supply, and its drain electrode connects the 19th PMOS The drain electrode of MP19；The source electrode of the 19th PMOS MP19 connects power supply, and its drain electrode connects the drain electrode of the 20th PMOS MP20；20th The source electrode of PMOS MP20 connects power supply, and its drain electrode connects the drain electrode of the 21st PMOS MP21；21st PMOS MP21's Source electrode connects power supply, and its grid connects the grid of the 22nd PMOS MP22, and its drain electrode connects the source electrode of the 28th PMOS MP28； The grid of the 28th PMOS MP28 connects the grid of the 29th PMOS MP29, and its drain electrode meets the 6th PNP type triode QP6 Emitter stage；The base stage of the 6th PNP type triode QP6 connects the drain electrode of the 9th NMOS tube MN9, its grounded collector；9th NMOS The grid and drain interconnection of pipe MN9, its source ground；The source electrode of the 22nd PMOS MP22 connects power supply, and its drain electrode connects second The source electrode of 19 PMOS MP29；The drain electrode of the 29th PMOS MP29 passes sequentially through the electricity of the 11st resistance R11 and the 13rd Resistance R13 is followed by the emitter stage of the 5th PNP type triode QP5；The tie point of the 11st resistance R11 and the 13rd resistance R13 connects line First output end of ripple sampled voltage current converter circuit；13rd resistance R13 and the 5th PNP type triode QP5 emitter stages Tie point connects the drain electrode of the 23rd PMOS MP23；The source electrode of the 23rd PMOS MP23 connects power supply；5th positive-negative-positive three-level The base stage of dry QP5 passes sequentially through the 18th resistance R18 and the 14th resistance R14 is followed by feedback voltage V FB, its grounded collector； The tie point of the 18th resistance R18 and the 14th resistance R14 is followed by the leakage of the tenth NMOS tube MN10 by the 20th resistance R20 Pole；The gate interconnection of the grid, the grid of the 11st NMOS tube MN11 and the 9th NMOS tube MN9 of the tenth NMOS tube MN10；Tenth The source ground of NMOS tube MN10；The drain electrode of the 11st NMOS tube MN11 passes sequentially through the electricity of the 21st resistance R21 and the 16th Resistance R16 is followed by reference voltage V ref, its source ground；The tie point of the 21st resistance R21 and the 16th resistance R16 is by the Five electric capacity C5 connect the tie point of the 18th resistance R18 and the 14th resistance R14；21st resistance R21 and the 16th resistance R16 Tie point the base stage of the 3rd PNP type triode QP3 is connect by the 19th resistance R19；The transmitting of the 3rd PNP type triode QP3 Pole passes sequentially through the drain electrode that the 15th resistance R15 and the 12nd resistance R12 is followed by the 30th PMOS MP30, and its colelctor electrode connects Ground；The grid of the 30th PMOS MP30 and the gate interconnection of the 28th PMOS MP28 and the 29th PMOS MP29； The source electrode of the 30th PMOS MP30 connects the drain electrode of the 25th PMOS MP25；The grid of the 25th PMOS MP25, The grid of the grid, the grid of the 21st PMOS MP21 and the 22nd PMOS MP22 of 26 PMOS MP26 is mutual Even；The source electrode of the 25th PMOS MP25 connects power supply；The company of the 3rd PNP type triode QP3 emitter stages and the 15th resistance R15 Contact connects the second output end of ripple sampled voltage current converter circuit；The connection of the 12nd resistance R12 and the 15th resistance R15 Point connects the drain electrode of the 24th PMOS MP24；The grid of the 24th PMOS MP24, the grid of the 23rd PMOS MP23 Pole, the grid of the 20th PMOS MP20, the gate interconnection of the 27th PMOS MP27；The source of the 24th PMOS MP24 Pole connects power supply；The tie point of the 12nd resistance R12 and the 15th resistance R15 is followed by the 4th positive-negative-positive three by the 17th resistance R17 The emitter stage of pole pipe QP4；The base stage of the 4th PNP type triode QP4 is by the output after the tenth resistance R10 for ripple supercircuit End, its grounded collector；The source electrode of the 26th PMOS MP26 connects power supply, its grid and drain interconnection, and its drain electrode connects second Current source I_B2Positive pole；Second current source I_B2Negative pole ground connection；The source electrode of the 27th PMOS MP27 connects power supply, its grid With drain interconnection, its drain electrode meets the 3rd current source I_B3Positive pole；3rd current source I_B3Negative pole ground connection.