CN203982245U - The high PSRR low-voltage-drop linear voltage regulator of a kind of high bandwidth - Google Patents
The high PSRR low-voltage-drop linear voltage regulator of a kind of high bandwidth Download PDFInfo
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- CN203982245U CN203982245U CN201420346692.0U CN201420346692U CN203982245U CN 203982245 U CN203982245 U CN 203982245U CN 201420346692 U CN201420346692 U CN 201420346692U CN 203982245 U CN203982245 U CN 203982245U
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Abstract
The utility model discloses the high PSRR low-voltage-drop linear voltage regulator of a kind of high bandwidth, this linear voltage regulator comprises voltage input end Vin, reference voltage end Vref, error amplifier EA and power tube MP, wherein, this linear voltage regulator also includes feed forward circuit and adder circuit, described feed forward circuit is connected between voltage input end Vin and the grid G of power tube MP by adder circuit, and described power tube MP is PMOS power tube MP, positive terminal at error amplifier EA is connected to feedback resistance, is parallel with and produces capacitor C Z zero point on feedback resistance.The utility model remains unchanged the grid G of PMOS power tube Mp and source S voltage, thereby improves PSRR performance, and can eliminate the second limit in system the zero point that adjustment produces capacitor C Z generation zero point, strengthens the stability of system.
Description
Technical field
The utility model relates to a module of power management chip in portable communications system, is specifically related to the high PSRR low-voltage-drop linear voltage regulator of a kind of high bandwidth.
Background technology
Low-voltage-drop linear voltage regulator (LDO) is a key modules of power management chip in portable communications system, conventionally its voltage derives from switch DC-DC converter, it eliminates the output ripple of switch DC-DC converter, and provide a burning voltage, but the progress along with technology, switch DC-DC converter noise spectrum is increasing, needs the LDO of the high PSRR of high bandwidth.
The LDO design of high PSRR (PSRR) is power management study hotspot always, in order to improve PSRR, researcher provides a lot of solutions, first, can give on LDO power supply a RC wave filter is provided, the power supply of LDO own is carried out to filtering, thereby improve PSRR, therefore the method has increased a resistance, thereby can improve the leakage voltage of LDO.Secondly, can adopt NMOS (N-type Metal-oxide-semicondutor) power tube framework, but in order to make the conducting of NMOS power tube, generally need to adopt charge pump (charge pump) circuit, thereby increase system architecture complicacy.Defect based on said method, this patent adopts power supply feed-forward technique, has proposed the LDO of the high PSRR of a kind of high bandwidth.
Sino-British noun intertranslation in the utility model:
LDO: low-voltage-drop linear voltage regulator, PSRR: Power Supply Rejection Ratio, NMOS:N type Metal-oxide-semicondutor, PMOS:n type substrate, p raceway groove, by the mobile metal-oxide-semiconductor that transports electric current in hole, charge pump: charge pump circuit.
Utility model content
The purpose of this utility model is to overcome the problem that prior art exists, and provides a kind of high bandwidth high PSRR low-voltage-drop linear voltage regulator.
For realizing above-mentioned technical purpose, reach above-mentioned technique effect, the utility model is achieved through the following technical solutions:
The high PSRR low-voltage-drop linear voltage regulator of a kind of high bandwidth, mainly comprise voltage input end Vin, reference voltage end Vref, error amplifier EA and power tube MP, this linear voltage regulator also includes feed forward circuit and adder circuit, and described feed forward circuit is connected between voltage input end Vin and the grid G of power tube MP by adder circuit.
Further, described feed forward circuit comprises operational amplifier FA, resistance R F1, resistance R F2, the positive terminal (+) of described operational amplifier FA connects described voltage output end Vout, the end of oppisite phase (-) of described operational amplifier FA connects described voltage input end Vin by resistance R F1, and between its end of oppisite phase (-) and output terminal, be connected with resistance R F2, described voltage input end Vin connects the source S of power tube MP.
Further, described totalizer 2 comprises linear power amplifier SA, resistance R S1, resistance R S2, resistance R S3, the end of oppisite phase (-) of described linear power amplifier SA connects the output terminal of described operational amplifier FA by resistance R S1, the output terminal of described linear power amplifier SA connects the grid G of described power tube MP.
Further, the output terminal of described error amplifier EA connects the positive terminal (+) of described linear power amplifier SA, the end of oppisite phase (-) of described error amplifier EA connects described reference voltage end Vref, the positive terminal (+) of described error amplifier EA is contact resistance R1 and resistance R 2 respectively, the other end of resistance R 1 connects voltage output end Vout, described voltage output end Vout connects the drain D of described power tube MP, the other end ground connection of resistance R 2.
Further, described resistance R 1, resistance R 2 forms feedback resistances, at described feedback resistance, partly builds zero point, at the two ends of described resistance R 1, produces capacitor C Z a zero point in parallel.
Preferably, described power tube MP is PMOS power tube MP.
The beneficial effects of the utility model are as follows:
1, power supply feed-forward technique.By power supply, feedover, power-supply fluctuation is significantly reduced the impact of power tube, thereby improve PSRR.
2, adopt PMOS power tube.The method system architecture is comparatively simple, does not need needed charge pump in NMOS power tube, than being easier to, realizes.
3, zero compensation technology.By partly building zero point at feedback resistance, the inferior limit in bucking-out system, thus system PM parameter is increased substantially, strengthened system stability.
Above-mentioned explanation is only the general introduction of technical solutions of the utility model, in order to better understand technological means of the present utility model, and can be implemented according to the content of instructions, below with preferred embodiment of the present utility model and coordinate accompanying drawing to be described in detail as follows.Embodiment of the present utility model is provided in detail by following examples and accompanying drawing thereof.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide further understanding of the present utility model, forms the application's a part, and schematic description and description of the present utility model is used for explaining the utility model, does not form improper restriction of the present utility model.In the accompanying drawings:
The LDO structural representation that Fig. 1 provides for the utility model embodiment;
Fig. 2 is the simulation curve figure of the PSRR of the utility model embodiment LDO.
Embodiment
Below with reference to the accompanying drawings and in conjunction with the embodiments, describe the utility model in detail.
Shown in Fig. 1, wherein Vin end is the voltage input end of the present embodiment linear voltage regulator LDO, and Vout end is voltage output end, and Vref end is reference voltage end, and IL is load current.The concrete structure of the present embodiment linear voltage regulator LDO comprises:
Operational amplifier FA, it has positive terminal (+), end of oppisite phase (-) and output terminal, its positive terminal (+) connects described voltage output end Vout, its end of oppisite phase (-) connects described voltage input end Vin by resistance R F1, between its end of oppisite phase (-) and output terminal, be connected with resistance R F2, wherein, resistance R F1, resistance R F2 and operational amplifier FA form feed forward circuit 1;
Linear power amplifier SA, it has positive terminal (+), end of oppisite phase (-) and output terminal, its end of oppisite phase (-) connects the output terminal of described operational amplifier FA by resistance R S1, the common end of oppisite phase (-) that connects described linear power amplifier SA in one end of resistance R S1, resistance R S2, resistance R S3, the other end of resistance R S2 connects the output terminal of linear power amplifier SA, the other end ground connection of resistance R S3, wherein, resistance R S1, resistance R S2, resistance R S3, linear power amplifier SA form totalizer 2;
Error amplifier EA, it has positive terminal (+), end of oppisite phase (-) and output terminal, its output terminal connects the positive terminal (+) of described linear power amplifier SA, its end of oppisite phase (-) connects described reference voltage end Vref, its positive terminal (+) is contact resistance R1 and resistance R 2 respectively, the other end of resistance R 1 connects described voltage output end Vout, the other end ground connection of resistance R 2, resistance R 1, resistance R 2 forms feedback resistance 3, wherein, in these feedback resistance 3 parts, build zero point, inferior limit in bucking-out system, significantly improve system PM parameter, strengthen system stability, concrete is produces capacitor C Z a zero point in parallel at the two ends of resistance R 1,
PMOS power tube MP, has source S, grid G and drain D, and its source S connects voltage input end Vin, and its drain D connects described voltage output end Vout, and its grid G connects the output terminal of described linear power amplifier SA.
Between described voltage output end Vout and earth terminal, also comprise a road load capacitance CL, and the dead resistance Resr of load capacitance CL, You Yi road load between described voltage output end Vout and earth terminal.
In the utility model, the feed forward circuit 1 being formed by resistance R F1, resistance R F2 and operational amplifier FA, when voltage input end Vin changes, voltage input end Vin directly acts on the source S of PMOS power tube MP, meanwhile, voltage input end Vin also acts on the grid G of PMOS power tube Mp by feed forward circuit 1, the grid G of PMOS power tube Mp and source S voltage are remained unchanged, thereby improves PSRR performance;
In this linear voltage regulator LDO framework, the grid G stray capacitance of PMOS power tube Mp (being load capacitance CL) is larger, but the output impedance of linear power amplifier SA is less, thereby limit is far away, the output impedance of error amplifier EA is large, but output capacitance is less, limit is also smaller, thereby whole linear voltage regulator LDO systematic comparison is easily stable, for further strengthening system stability, in the resistance R 1 of this patent in feedback resistance 3, produce capacitor C Z a zero point in parallel, produce capacitor C Z this zero point and will produce a zero point, by adjusting this zero point, can eliminate the second limit in system, the stability of enhancing system.
Shown in Fig. 2 and table 1, LDO performance index increase substantially, in the bandwidth range of 10MHZ, all be low to moderate-80db of the parameter of PSRR, can meet the application of most of occasions, and the performance index such as the leakage voltage of LDO and load capacity all there is no to reduce, and system architecture is simple.
Following table 1 is the main performance index of the present embodiment neutral line voltage stabilizer LDO:
The main performance index of table 1:LDO
| Input voltage | 2.5V |
| Leakage voltage | 1.0V@Iout＝200mA |
| Output voltage | 1.2V |
| Output voltage precision | ±2％ |
| Maximum output current | 200mA |
The foregoing is only preferred embodiment of the present utility model, be not limited to the utility model, for a person skilled in the art, the utility model can have various modifications and variations.All within spirit of the present utility model and principle, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection domain of the present utility model.
Claims (6)
1. the high PSRR low-voltage-drop linear voltage regulator of high bandwidth, mainly comprise voltage input end Vin, reference voltage end Vref, error amplifier EA and power tube MP, it is characterized in that, this linear voltage regulator also includes feed forward circuit 1 and totalizer 2 circuit, and described feed forward circuit 1 is connected between voltage input end Vin and the grid G of power tube MP by totalizer 2 circuit.
2. the high PSRR low-voltage-drop linear voltage regulator of high bandwidth according to claim 1, it is characterized in that, described feed forward circuit 1 comprises operational amplifier FA, resistance R F1, resistance R F2, the positive terminal (+) of described operational amplifier FA connects described voltage output end Vout, the end of oppisite phase (-) of described operational amplifier FA connects described voltage input end Vin by resistance R F1, and between its end of oppisite phase (-) and output terminal, be connected with resistance R F2, described voltage input end Vin connects the source S of power tube MP.
3. the high PSRR low-voltage-drop linear voltage regulator of high bandwidth according to claim 2, it is characterized in that, described totalizer 2 comprises linear power amplifier SA, resistance R S1, resistance R S2, resistance R S3, the end of oppisite phase (-) of described linear power amplifier SA connects the output terminal of described operational amplifier FA by resistance R S1, the output terminal of described linear power amplifier SA connects the grid G of described power tube MP.
4. the high PSRR low-voltage-drop linear voltage regulator of high bandwidth according to claim 3, it is characterized in that, the output terminal of described error amplifier EA connects the positive terminal (+) of described linear power amplifier SA, the end of oppisite phase (-) of described error amplifier EA connects described reference voltage end Vref, the positive terminal (+) of described error amplifier EA is contact resistance R1 and resistance R 2 respectively, the other end of resistance R 1 connects voltage output end Vout, described voltage output end Vout connects the drain D of described power tube MP, the other end ground connection of resistance R 2.
5. the high PSRR low-voltage-drop linear voltage regulator of high bandwidth according to claim 4, it is characterized in that, described resistance R 1, resistance R 2 forms feedback resistances 3, in described feedback resistance 3 parts, builds zero point, at the two ends of described resistance R 1, produces capacitor C Z a zero point in parallel.
6. the high PSRR low-voltage-drop linear voltage regulator of high bandwidth according to claim 1, is characterized in that, described power tube MP is PMOS power tube MP.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420346692.0U CN203982245U (en) | 2014-06-24 | 2014-06-24 | The high PSRR low-voltage-drop linear voltage regulator of a kind of high bandwidth |
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| CN201420346692.0U CN203982245U (en) | 2014-06-24 | 2014-06-24 | The high PSRR low-voltage-drop linear voltage regulator of a kind of high bandwidth |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104049667A (en) * | 2014-06-24 | 2014-09-17 | 吴江圣博瑞信息科技有限公司 | High-bandwidth high-PSRR low-pressure-drop linear voltage regulator |
| CN109308086A (en) * | 2017-07-28 | 2019-02-05 | 恩智浦美国有限公司 | For improving the electric current and voltage adjusting method of Electro Magnetic Compatibility |
-
2014
- 2014-06-24 CN CN201420346692.0U patent/CN203982245U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104049667A (en) * | 2014-06-24 | 2014-09-17 | 吴江圣博瑞信息科技有限公司 | High-bandwidth high-PSRR low-pressure-drop linear voltage regulator |
| CN109308086A (en) * | 2017-07-28 | 2019-02-05 | 恩智浦美国有限公司 | For improving the electric current and voltage adjusting method of Electro Magnetic Compatibility |
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| DD01 | Delivery of document by public notice |
Addressee: Wujiang Shengborui Information Technology Co., Ltd. Document name: Notification to Pay the Fees |
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| CF01 | Termination of patent right due to non-payment of annual fee |
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| CF01 | Termination of patent right due to non-payment of annual fee |