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CN104885217A - 两个或多个晶元的多晶元堆叠 - Google Patents

两个或多个晶元的多晶元堆叠 Download PDF

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Publication number
CN104885217A
CN104885217A CN201380067609.4A CN201380067609A CN104885217A CN 104885217 A CN104885217 A CN 104885217A CN 201380067609 A CN201380067609 A CN 201380067609A CN 104885217 A CN104885217 A CN 104885217A
Authority
CN
China
Prior art keywords
microelectronic element
contact
module
microelectronic
contacts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201380067609.4A
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English (en)
Inventor
韦勒·佐尼
贝尔加桑·哈巴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adeia Semiconductor Solutions LLC
Original Assignee
Tessera LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/658,401 external-priority patent/US8952516B2/en
Application filed by Tessera LLC filed Critical Tessera LLC
Publication of CN104885217A publication Critical patent/CN104885217A/zh
Pending legal-status Critical Current

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745Mounting details of integrated circuit chips
    • G06K19/07747Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
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    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
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Abstract

一种微电子封装(1310)可包括具有第一表面和第二表面(1341,1342)的衬底(1340),以及第一微电子元件和第二微电子元件(1320,1330)。衬底(1340)可具有在第一表面(1341)处的多个衬底触点(1347a,1347b)和在第二表面(1342)处的多个端子(1350)。微电子元件(1320,1330)的元件触点(1324,1334)可与相应的衬底触点(1347a,1347b)相联接。第二微电子元件(1330)的前表面(1331)可部分地覆盖且附接至第一微电子元件(1320)的后表面(1322)。第一微电子元件(1320)的元件触点(1324)可布置在面阵中且与衬底触点(1347a)倒装芯片键合。第二微电子元件(1330)的元件触点(1334)可通过导电块(1375)与衬底触点(1347b)相联接。

Description

两个或多个晶元的多晶元堆叠
相关申请的交叉引用
本申请是2012年10月23日提交的美国专利申请No.13/658,401的继续申请,美国专利申请No.13/658,401是2011年11月29日提交的美国专利申请No.13/306,203的部分继续申请,美国专利申请No.13/306,203要求2011年4月21日提交的美国临时专利申请No.61/477,820的权益,其公开内容通过引用并入本文。以下的共同所有的申请通过引用并入本文,包括:均在2011年4月21日申请的美国临时专利申请61/477,877、61/477/883以及61/477,967。
背景技术
本发明涉及堆叠微电子组件,制造这种组件的方法,以及用于这种组件的部件。
半导体芯片通常设为单独的预封装单元。标准芯片具有带有大的前面的扁平矩形体,该前面具有连接到芯片的内部电路的触点。每个单独的芯片典型地安装在封装中,封装再安装在电路板例如印制电路板上,封装将芯片的触点连接到电路板的导体。在很多常规的设计中,芯片封装在电路板中占用的面积比芯片本身的面积大很多。
如参考具有前面的扁平芯片的本公开中所使用的“芯片的面积”应被理解为指的是所述前面的面积。在“倒装芯片”设计中,芯片的前面面对封装衬底的面,即,通过焊球或其他连接元件将芯片载体与芯片上的触点直接键合到芯片载体的触点。通过覆盖芯片的前面的端子又可以将芯片载体键合到电路板。“倒装芯片”设计提供相对紧凑的布置;每个芯片占用的电路板的面积等于或稍大于芯片的前面的面积,例如在共同转让的美国专利5,148,265、5,148,266和5,679,977中的某些实施例中所公开的,其全部公开内容通过引用并入本文。
某些创新的安装技术提供的紧密度接近或等于常规倒装芯片键合的紧密度。可以在等于或稍大于芯片本身的面积的电路板的面积中容置单个芯片的封装通常被称为“芯片级封装”。
除了最小化被微电子组件占用的电路板的平面面积,还需要生产一种垂直于电路板平面的整体高度或尺寸较小的芯片封装。这种薄的微电子封装允许将其中安装有封装的电路板紧挨着相邻结构放置,由此减小包含电路板的产品的整体尺寸。
已经提出用于在单个封装或模块中设置多个芯片的各种提议。在常规的“多芯片模块”中,芯片并排地安装在单个封装衬底上,然后可以将该封装衬底安装至电路板。这种方法只是提供芯片所占用的电路板的总面积的有限减小。总面积仍然大于模块中各个芯片的总表面积。
还已经提出将多个芯片封装在“堆叠”布置(即多个芯片放置成一个在另一个之上的布置)中。在堆叠布置中,可以将多个芯片安装在比芯片的总面积小的电路板的面积中。例如,在上述的美国专利5,679,977、5,148,265以及5,347,159的某些实施例中公布了一些堆叠芯片布置,其全部公开内容通过引用并入本文。也通过引用并入本文的美国专利4,941,033公开一种布置,其中芯片一个在另一个之上地堆叠,且通过与芯片相关联的所谓的“布线膜”上的导体彼此互连。
尽管多芯片封装已取得一定发展,但为了使其尺寸最小化及提高其性能,仍需要进一步的改进。本发明的特点将通过以下描述的微电子组件的构造实现。
发明内容
根据本发明的方面,一种微电子封装可包括具有相对的第一表面及第二表面的衬底,以及具有面对衬底的第一表面的前表面的第一微电子元件和第二微电子元件。衬底可具有在第一表面处的多个衬底触点和在第二表面处的多个端子,用于将微电子封装连接至封装外部的至少一个部件。每个微电子元件具有在其前表面处的多个元件触点。每个微电子元件的元件触点可与相应的衬底触点相联接。第二微电子元件的前表面可部分地覆盖且附接至第一微电子元件的后表面。第一微电子元件的元件触点可布置在面阵中且与第一组衬底触点倒装芯片键合。第二微电子元件的元件触点可通过导电块与第二组衬底触点相联接。
在一个特定示例中,第二微电子元件的元件触点可突出于第一微电子元件的侧边缘之外。在一个实施例中,第一微电子元件和第二微电子元件中的至少一个包括存储器元件。在一个示例性实施例中,微电子封装还可包括从至少一些衬底触点延伸至端子的多个引线。该引线可用于携载地址信号以在第一微电子元件和第二微电子元件中的至少一个中对存储器元件寻址。在一个示例中,至少一些端子可用于携载各个端子与第一微电子元件和第二微电子元件中的每个之间的信号或参考电位中的至少一个。
在一个实施例中,微电子封装还可包括多个第三微电子元件,每个第三微电子元件电连接至衬底。在一个特定示例中,多个第三微电子元件可布置成堆叠结构,每个第三微电子元件具有与一个相邻的第三微电子元件的前表面或后表面相面对的前表面或后表面。在一个实施例中,多个第三微电子元件可布置成平面结构,每个第三微电子元件具有与一个相邻的第三微电子元件的外围表面相面对的外围表面。
在一个示例性实施例中,第二微电子元件可包括易失性RAM,每个第三微电子元件可包括非易失性闪存,且第一微电子元件可包括主要用于控制外部组件与第二微电子元件和第三微电子元件之间的数据传送的处理器。在一个示例中,第二微电子元件可包括易失性帧缓冲存储器元件,每个第三微电子元件可包括非易失性闪存,且第一微电子元件可包括图形处理器。
在一个特定实施例中,一种系统可包括多个上述微电子封装、电路板和处理器。微电子封装的端子与电路板的板触点电连接。每个微电子封装可用于在时钟周期内传送N个并行数据位,处理器可用于在时钟周期内传送M个并行数据位,且M大于或等于N。在一个特定示例中,一种系统可包括一个上述微电子封装,以及电连接至该微电子封装的一个或多个其他电子部件。在一个实施例中,系统还可包括壳体,上述微电子封装和其他电子部件安装至该壳体。
根据本发明的另一方面,一种模块可包括具有第一表面和第二表面的模块卡,第一微电子元件和第二微电子元件具有面对模块卡的第一表面的前表面。模块卡可具有多个平行的暴露的边缘触点,该边缘触点邻近第一表面和第二表面中的至少一个的边缘,用于当模块插入插口时,与插口相应的触点对接。模块卡可具有在第一表面上的多个卡触点。每个微电子元件可具有在其前表面处的多个元件触点。每个微电子元件的元件触点可与相应的卡触点相联接。第二微电子元件的前表面可部分地覆盖且附接至第一微电子元件的后表面。第一微电子元件的元件触点可布置在面阵中且与第一组卡触点倒装芯片键合。第二微电子元件的元件触点通过导电块与第二组卡触点相联接。
在一个示例性实施例中,第二微电子元件的元件触点可突出于第一微电子元件的侧边缘之外。在一个示例中,边缘触点可暴露在模块卡的第一表面或第二表面中的至少一个处。在一个特定实施例中,第一微电子元件和第二微电子元件中的至少一个可包括存储器元件。在一个实施例中,模块可包括从至少一些卡触点延伸至边缘触点的多个引线。该引线可用于携载地址信号以在第一微电子元件和第二微电子元件中的至少一个中对存储器元件寻址。在一个特定示例中,至少一些边缘触点可用于携载各个边缘触点与第一微电子元件和第二微电子元件中的每个之间的信号或参考电位中的至少一个。
在一个特定示例中,模块还可包括多个第三微电子元件,每个第三微电子元件电连接至模块卡。在一个示例中,多个第三微电子元件可布置成堆叠结构,每个第三微电子元件具有与一个相邻的第三微电子元件的前表面或后表面相面对的前表面或后表面。在一个特定实施例中,多个第三微电子元件可布置成平面结构,每个第三微电子元件具有与一个相邻的第三微电子元件的外围表面相面对的外围表面。
在一个实施例中,第二微电子元件可包括易失性RAM,每个第三微电子元件可包括非易失性闪存,且第一微电子元件可包括主要用于控制外部组件与第二微电子元件和第三微电子元件之间的数据传送的处理器。在一个特定示例中,第二微电子元件可包括易失性帧缓冲存储器元件,每个第三微电子元件可包括非易失性闪存,且第一微电子元件可包括图形处理器。
在一个示例性实施例中,一种系统可包括多个上述的模块、电路板和处理器。模块的暴露的触点插入至与电路板电连接的对接插口。每个模块用于在时钟周期内传送N个并行数据位,处理器用于在时钟周期内传送M个并行数据位,且M大于或等于N。在一个示例中,一种系统可包括上述的模块,以及电连接至该模块的一个或多个其他电子部件。在一个特定实施例中,系统还可包括壳体,上述模块和其他电子部件安装至该壳体。
附图说明
图1A是根据本发明实施例的堆叠微电子组件的示意性剖视图;
图1B是沿着图1A中的线1B-1B的图1A的堆叠组件的仰剖视图;
图1C是沿着图1B中的线1C-1C的图1B的堆叠组件的侧剖视图;
图2是根据另一个实施例的具有倒装芯片键合的微电子元件的堆叠微电子组件的示意性剖视图;
图3是根据另一个实施例的具有面朝上的微电子元件的堆叠微电子组件的示意性剖视图;
图4是根据另一个实施例的具有模块卡中单个开口以供线键合延伸穿过附接至两个微电子元件的堆叠微电子组件的示意性剖视图。
图5是根据另一个实施例的具有引线键合的堆叠微电子组件的示意性剖视图;
图6是根据另一个实施例的具有加长的焊料触点的堆叠微电子组件的示意性剖视图;
图7A是根据另一个实施例的具有带有位于其边缘附近的触点的微电子元件的堆叠微电子组件的示意性剖视图;
图7B是沿着图7A中的线7B-7B的图7A的堆叠封装的仰剖视图;
图7C是示出用于图7B中的一部分的触点的可选布置的局部视图;
图8是图1B的堆叠组件的仰剖视图的变型,其中一个微电子元件具有方向为大致垂直于另一个微电子元件的多行中心触点的多行中心触点;
图9A是根据另一个实施例的具有引线框架的堆叠微电子组件的示意性剖视图;
图9B是沿着图9A中的线9B-9B的图9A的堆叠组件的仰剖视图;
图9C是沿着图9B中的线9C-9C的图9B的堆叠组件的侧剖视图;
图10A是根据另一个实施例的具有多个堆叠微电子元件(未示出密封剂)的堆叠微电子组件的示意性俯视图;
图10B是沿着图10A中的线10B-10B的图10A的堆叠组件的侧剖视图;
图10C是根据另一个实施例的具有多个相互相邻的微电子元件的堆叠微电子组件的示意性俯视图;
图11是根据另一个实施例的包括两个相互键合的模块卡的堆叠微电子组件的示意性立体图;
图12是根据一个实施例的包括多个模块的系统的示意图;
图13A是根据另一个实施例的堆叠微电子封装的示意性剖视图;
图13B是沿着图13A中的线13A-13A的图13A所示的堆叠封装的仰剖视图;
图14A至图14E是由图13A中阴影部分14显示的图13A的堆叠微电子封装的一部分的变型的局部剖视图;
图15是根据另一个实施例的具有延长的焊料触点的堆叠微电子封装的示意性剖视图;
图16是根据本发明的一个实施例的一种系统的示意图。
具体实施方式
参考图1A至图1C,根据本发明的实施例的模块10可包括第一微电子元件20、第二微电子元件30和具有暴露的边缘触点50的模块卡40。第一密封剂60可覆盖微电子元件20和30,以及模块卡40的一部分。
在一些实施例中,第一微电子元件20和第二微电子元件30中的至少一个可为半导体芯片、晶片或类似的。例如,第一微电子元件20和第二微电子元件30中的一个或两个可包括存储器元件,如DRAM。正如在此所用的,“存储器元件”是指多个存储单元布置成阵列,与电路一起用于存储和从中检索数据,例如用于通过电接口的传输数据。在一个特定示例中,模块10可包括在单列直插内存模块(SIMM)或双列直插式内存模块(DIMM)中。
第一微电子元件20可具有前表面21,远离前表面21的后表面22,以及在前表面和后表面之间延伸的侧边缘23。电触点24暴露在第一微电子元件20的前表面21处。正如在此所述的,第一微电子元件20的电触点24也可指代“芯片触点”。如在本发明所使用的,导电元件“暴露在”结构的表面处的状态表示导电元件可用于与在垂直于结构的表面方向上从结构外部朝着结构的表面移动的理论点接触。因此,暴露在结构的表面处的端子或其他导电元件可从这样的表面突出;可与这样的表面平齐;或者可相对于这样的表面凹入并通过结构中的孔或凹入部暴露。第一微电子元件20的触点24暴露在第一微电子元件的中心区域25内的前表面21处。例如,触点24可布置成邻近前表面21的中心的一行或平行的两行。
第二微电子元件30可具有前表面31,远离前表面31的后表面32,以及在前表面和后表面之间延伸的侧边缘33。电触点34暴露在第一微电子元件30的前表面31处。正如在此所述的,第二微电子元件30的电触点34也可指代“芯片触点”。第二微电子元件30的触点34暴露在第二微电子元件的中心区域35内的前表面31处。例如,触点34可布置成邻近前表面31的中心的一行或平行的两行。
如图1A和1C所示,第一微电子元件20和第二微电子元件30相互堆叠。在一些实施例中,第二微电子元件30的前表面31和第一微电子元件20的后表面22相互面对。第二微电子元件30的前表面31的至少一部分可覆盖第一微电子元件20的后表面22的至少一部分。第二微电子元件30的中心区域35的至少一部分可以突出超过第一微电子元件20的侧边缘23。相应地,第二微电子元件30的触点34可放置在突出超过第一微电子元件20的侧边缘23的位置处。
微电子组件10可进一步包括具有相对地面对的第一表面41和第二表面42的模块卡40。一个或多个导电触点44可暴露在模块卡40的第二表面42处。模块卡40可进一步包括一个或多个孔,例如第一孔45和第二孔46。如图1A和图1C所示,第一微电子元件20和第二微电子元件30各自的前表面21和31可面对模块卡40的第一表面41。
模块卡40可部分地或全部地由任何适当的介质材料制成。例如,模块卡40可包括相对刚性的板状材料,例如纤维增强环氧树脂的厚层,例如,Fr-4板或Fr-5板。不论使用何种材料,模块卡40可包括单层的或多层的介质材料。在特定实施例中,模块卡40基本上可由具有低于百万分之三十每摄氏度(“30ppm/℃”)的热膨胀系数的材料组成。
如图1所示,模块卡40可延伸超过第一微电子元件20的侧边缘23和第二微电子元件30的侧边缘33。模块卡40的第一表面41可与第一微电子元件20的前表面21并列。
在图1A至图1C描述的实施例中,模块卡40包括基本上与第一微电子元件20的中心区域25对齐的第一孔45和基本上与第二微电子元件30的中心区域35对齐的第二孔46,由此分别通过第一孔和第二孔接触触点24和34。第一孔45和第二孔46可在模块卡40的第一表面41和第二表面42之间延伸。如图1B所示,孔45和46可与各个第一微电子元件20和第二微电子元件30的相应芯片触点24或34对齐。
模块卡40也可包括暴露在其第二表面42处的导电触点44和在触点44与暴露的边缘触点50之间延伸的导电迹线55。导电迹线55将触点44电联结至暴露的边缘触点50。在特定实施例中,触点44可为各个迹线55的端部。
在特定实施例中,模块卡40可具有多个平行的暴露的边缘触点50,这些触点50邻近第一表面41和第二表面42中至少一个的内插边缘43,用于当模块10插入插口(图12所示)时,与该插口相应的触点对接。如图1B所示,可对内插边缘43进行定位,使得孔45和46中的每一个具有在背离模块卡40的内插边缘43的方向上延伸的长度L。一些或所有的边缘触点50可暴露在模块卡40的第一表面41或第二表面42中的一个或两个处。
暴露的边缘触点50和内插边缘43可被设计尺寸以插入系统其他连接器的相应的插口(图12),例如,可设置在主板上。这种暴露的边缘触点50可适合在这种插口连接器内与多个相应的弹簧触点(图12)对接。这种弹簧触点可设置在每个槽的单边或多边上,以与相应的暴露的边缘触点50对接。在一个示例中,至少一些边缘触点50可用于携载各个边缘触点与第一微电子元件20和第二微电子元件30中的每个之间的信号或参考电位中的至少一个。
如图1A至图1C所示,电连接或引线70可将第一微电子元件20的触点24和第二微电子元件30的触点34连接至暴露的边缘触点50。引线70可包括线键合71和72,以及导电迹线55。在一个实施例中,引线70可考虑用于将微电子元件20和30都电连接至模块卡40。在特定示例中,引线70可用于携载地址信号以在第一微电子元件20和第二微电子元件30中的至少一个中对存储器元件寻址。
正如在此所使用的,“引线”是在两个导电元件之间延伸的电连接的一部分或全部,例如引线70包括线键合71和导电迹线55。该导电迹线55从第一微电子元件20的一个触点24延伸穿过第一孔45至一个暴露的边缘触点50。
在一个示例中,模块10可包括多个在孔45和46内从第一微电子20和第二微电子元件30中至少一个的芯片触点24和34延伸至暴露的边缘触点50的引线70。在特定示例中,引线70可包括在模块卡40上的导电迹线55和从导电迹线延伸至第一微电子20和第二微电子元件30中至少一个的芯片触点24和34的线键合71、72。
在图1B所示,引线70的导电迹线55可沿模块卡40的第二表面42延伸。在特定示例中,引线70的导电迹线55可沿着模块卡40的第一表面41延伸,或引线的导电迹线可沿着模块卡的第一表面41和第二表面42延伸。导电迹线55的部分可沿着模块卡40的表面41或42在大致平行于孔45和46的长度L的方向上从各个触点24和34延伸至暴露的边缘触点50。在特定实施例中,导电迹线55可以沿着模块卡40的表面41或42的方式布置,使得引线70在各个触点24和34与暴露的边缘触点50之间的长度可被最小化。
线键合71和72中的每一个可延伸穿过各个第一孔45或第二孔46,且可将各个触点24或34电联结至模块卡40的相应触点44。线键合71和72的形成过程可包括通过孔45、46将键合工具插入,以将导电触点24、34电连接至模块卡40的相应导电触点44。
在特定实施例中,线键合71和72中的每个可为包括多个方向上相互大致平行的线键合的多线键合。这种包括多个线键合71、72的多线键合结构可提供在触点24或34与模块卡40的相应触点44之间的平行导电通路。
间隔片12可位于第二微电子元件30的前表面31和模块卡40的第一表面41的一部分之间。这种间隔片12可以由例如介质材料(例如硅二极管)、半导体材料(例如硅)、或一层或多层的粘合剂制成。如果间隔件12包括粘合剂,粘合剂可以将第二微电子元件30连接至模块卡40。在一个实施例中,间隔片12在基本垂直于模块卡40的第一表面41的竖直方向V上可具有与第一微电子元件20的在前表面21和后表面22之间的的厚度T2基本相等的厚度T1。
在特定实施例中,间隔片12可被具有面对模块卡40的第一表面41的缓冲芯片代替。在一个示例中,这种缓冲芯片可倒装芯片键合至暴露在模块卡40的第一表面41处的触点。这种缓冲芯片可用于帮助提供微电子元件20、30中的每一个关于模块10的外部部件的阻抗隔离。
一个或多个粘合剂层14可位于第一微电子元件20和模块卡40之间,第一微电子元件20和第二微电子元件30之间,第二微电子元件30和间隔片12之间,以及间隔片12和模块卡40之间。这种粘合剂层14可包括用于将模块10的上述部件相互键合的粘合剂。在特定实施例中,一个或多个粘合剂层14可在模块卡40的第一表面41和第一微电子元件20的第一表面21之间延伸。在一个实施例中,一个或多个粘合剂层14可将第二微电子元件30的前表面31的至少一部分附接至第一微电子元件20的后表面22的至少一部分。
在一个示例中,每个粘合剂层14可部分地或全部地由晶元粘贴粘合剂制成,且可由低弹性模量材料(例如硅酮弹性体)组成。在一个实施例中,晶元粘贴粘合剂可为兼容的。在另一个示例中,如果两个微电子元件20和30是由相同材料形成的常规半导体芯片,每个粘合剂层14可部分地或全部地由一薄层高弹性模量粘合剂或焊料制成,这是因为,响应于温度变化,微电子元件将趋于一致地扩张或收缩。无论使用何种材料,每个粘合剂层14可在其中包括单个层或多个层。在间隔片12由粘合剂制成的特定实施例中,位于间隔片12、第二微电子元件30和模块卡40之间的粘合剂层14可被省略。
模块10也可包括第一密封剂60和第二密封剂65。第一密封剂60可覆盖,例如,第一微电子元件20和第二微电子元件30的各自的后表面22和32,以及模块卡40的第一表面41的部分。在特定实施例中,第一密封剂60可为包胶模(overmold)。一个或多个密封剂65可覆盖第一微电子元件20和第二微电子元件30的暴露在各自的孔45和46之内的前表面21和31,模块卡40的第二表面42的部分,触点24、34和44,以及延伸在各个触点24、34与相应的触点44之间的线键合71和72。在特定实施例中,第二密封剂65可覆盖延伸在芯片触点24、34与模块卡40之间的引线70的部分。
在一种根据特定实施例的工艺中,第一密封剂60可注射到第一微电子元件20和第二微电子元件30的各自的后表面22和32上,以及模块卡40的第一表面41上。在一种根据一个示例的工艺中,第二密封剂65可注射进第一孔45和第二孔46内,使得引线70在芯片触点24、34和模块卡40之间的部分被第二密封剂覆盖。
图2是关于图1A至图1C所述的实施例的变型。在此变型中,模块210与上述的模块10相同,除了第一微电子元件220倒装芯片键合至模块卡240的第一表面241上,而不是线键合至模块卡的第二表面。
导电触点224暴露在第一微电子元件220的前表面221处。导电触点或芯片触点224可通过例如导电块273电连接至暴露在模块卡240的第一表面241处的导电触点247。导电块273可包括具有较低熔融温度的易熔金属,例如,焊料,锡或包括多种金属的低熔混合物。可选地,导电块273可包括可湿性金属,例如,铜或其他具有高于焊料或其他易熔金属的熔融温度的贵金属或者非贵金属。在特定实施例中,导电块273可包括散布在介质中的导电材料,例如,导电胶、金属填充胶、焊料填充胶、各向同性的导电胶或各向异性的导电胶。
导电迹线(未在图2中示出)可沿着模块卡240的第一表面241从导电触点247延伸至在模块卡的内插边缘(例如图1B和图1C示出的内插边缘43)处的暴露的边缘触点。正如在上述的模块10中,第二微电子元件230的芯片触点234可通过延伸穿过模块卡的孔246的线键合272电连接至模块卡240的相应的导电触点244。导电迹线也可沿着模块卡240的第二表面242从导电触点244延伸至在模块卡的内插边缘(例如图1B和图1C示出的内插边缘43)处的暴露的边缘触点。
图3是关于图1A至图1C所述的实施例的另一种变型。在此变型中,模块310与上述的模块10相同,除了第一微电子元件320放置成其后表面322面对模块卡340的第一表面341,以及其前表面321的至少部分面对且部分地覆盖第二微电子元件330的前表面331的至少部分。第一微电子元件320的后表面322可通过一个或多个粘合剂层(例如图1A和图1C所示的粘合剂层14)附接至模块卡340的第一表面341。导电触点324a和324b(共同地为导电触点324)可暴露在第一微电子元件320的前表面321处。第一微电子元件320的芯片触点324可包括导电触点324a和/或324b的任何结构。
第一微电子元件320的导电触点324a可暴露在第一微电子元件的中心区域325内的第一表面321处。例如,触点324a可布置成邻近前表面321的中心的一行或平行的两行。导电触点324a可通过例如线键合371a电连接至暴露在模块卡340的第一表面341处的导电触点347。
第一微电子元件320的导电触点324b可暴露在第一微电子元件的侧边缘323附近的前表面321处。例如,触点324b可布置成邻近第一微电子元件320的侧边缘323的一行或平行的两行。导电触点324b可(通过,例如线键合371b)电连接至暴露在模块卡340的第一表面341处的导电触点347。
同图2类似,导电迹线(未在图3中示出)可分别沿着模块卡340的第一表面341和第二表面342从导电触点347和344延伸至在模块卡的内插边缘处(例如图1B和图1C所示的内插边缘43)的暴露的边缘触点。
尽管图3所示的实施例示出第二微电子元件330通过线键合372电连接至模块卡340,但是在其他实施例中,第二微电子元件可通过各种其他方式电连接至模块卡,包括例如,引线键合(如图5所示)或利用焊料的倒装芯片键合(如图6和图7所示)。
图4是根据图1A至图1C所述的实施例的另一种变型。在此变型中,模块410与上述的模块10相同,除了第一微电子元件410和第二微电子元件420通过延伸穿过在模块卡的第一表面441和第二表面442之间延伸的共同的孔446的各个线键合471和472电连接至模块卡440,而不是让每个微电子元件通过延伸穿过模块卡的各个分开的孔的线键合电连接至模块卡。
如图4所示,第一微电子元件420的导电触点424可暴露在第一微电子元件的侧边缘423附近的前表面421处。例如,触点424可布置成邻近第一微电子元件420的侧边缘423的行。导电触点424可通过例如线键合471电连接至暴露在模块卡440的第二表面442的导电触点444。
第二微电子元件430的导电触点434可暴露在第二微电子元件的中心区域435内的前表面431处。例如,触点434可布置成接近前表面431的中心的行。导电触点434可通过例如线键合472电连接至暴露在模块卡440的第二表面442的导电触点444。
在图4所示的实施例中,模块410可包括单个第二密封剂465。例如,第二密封剂465可覆盖,暴露在单个共同孔446之内的微电子元件420和430各自的前表面421和431的部分,模块卡440的第二表面442的部分,触点424、434和444,以及在各个触点424、434与相应的触点444之间延伸的线键合471和472。
图5是根据图1A至图1C所述的实施例的另一种变型。在此变型中,模块510与上述的模块10相同,除了第一微电子元件520倒装芯片键合至模块卡540的第一表面541(同图2所示的方式),且第二微电子元件530通过从导电迹线延伸至芯片触点534的引线键合574a和574b(共同地为引线键合574)而不是通过线键合电连接至模块卡540。
如图5所示,第二微电子元件530的导电触点534a和534b(共同地为导电触点534)可暴露在第二微电子元件的中心区域535内的前表面531处。例如,触点534可布置成邻近前表面531的中心的一行或平行的两行。一些导电触点534a可通过例如引线键合574a电连接至暴露在模块卡540的第二表面542的导电触点544。其他的导电触点534b可通过例如引线键合574b电连接至暴露在模块卡540的第一表面541的导电触点547。如图5所示,导电触点544和547可为各个引线键合574a和引线键合574b的导电触点部分。
形成引线键合574的工艺可大致如共同转让的美国专利5,915,752和5,489,749中描述的,其公开内容通过引用并入本文。在引线键合过程中,每个引线570可通过工具(如热超声键合工具)被向下移位与相应的导电触点534接合。这种键合工具可通过孔546插入,以将引线570电连接至相应的导电触点534。引线570的脆弱部分可能会在此过程中断裂。
图6是关于图1A至图1C所述的实施例的另一种变型。在此变型中,模块610与上述的模块10相同,除了第一微电子元件620倒装芯片键合至模块卡640的第一表面641(同图2所示的方式),且第二微电子元件630通过在第二微电子元件的导电触点634与暴露在模块卡的第一表面处的导电触点647之间延伸的导电块675,而不是通过线键合倒装芯片键合至模块卡的第一表面。在特定实施例中,模块卡640可能没有延伸穿过在其第一表面641和第二表面642之间的孔(如图1A所示的孔45和46)的引线。
同上述的模块10类似,第二微电子元件630的导电触点634可暴露在第二微电子元件的中心区域635内的前表面631处。例如,触点634可布置成邻近前表面631的中心的一行或平行的两行。
导电块675可为,例如,细长的焊料连接,焊球或参考导电块273的上述任何其他材料。这种导电块675可延伸穿过间隔片612与第一微电子元件620的侧边缘623之间的空隙,以将第二微电子元件630与模块卡640电连接。
图7A和图7B是关于图6所述的实施例的另一种变型。在此变型中,模块710与上述的模块610相同,除了第二微电子元件730通过在位于邻近第二微电子元件的侧边缘733的导电触点734与暴露在模块卡的第一表面处的导电触点747之间延伸的导电块775倒装芯片键合至模块卡740的第一表面741,而不是让导电块在暴露在第二微电子元件的中心区域内的第二微电子元件的前表面处的导电触点之间延伸。
第一微电子元件720可具有在第一微电子元件的第一表面721处的多个元件触点724。元件触点724可与第一组衬底触点747a联接,使得元件触点与衬底触点倒装芯片键合。如图7B所示,元件触点724和第一组衬底触点747a中的每个可布置成面阵结构。
在特定示例中,第二微电子元件730的前表面731处的触点734可布置成邻近第二微电子元件的侧边缘733的列,使得触点734可突出超过第一微电子元件720的侧边缘723。元件触点734可与第二组衬底触点747b联接,使得元件触点与衬底触点倒装芯片键合。
尽管触点724,734和747布置成图示的触点平行列,但是本发明也考虑了触点的其他布置方式。例如,尽管图7B没有显示出来,但是至少一个触点可设置在相邻的触点列之间。在另一示例中(例如图7C所示),触点可包括一列触点,其中列轴719延伸穿过这列触点724中的大部分,即这列触点724中的大部分相对于列轴719居中。但是,在这种列中,一个或多个触点724可能不会相对于列轴719居中,比如触点724’这种情况。在此情况下,尽管这个(或这些)触点可能没有相对于列轴719居中,但因为离特定列的轴719比其离其他列的轴更近,所以这些一个或多个触点724’可看作是特定列的部分。列轴719可延伸穿过上述未相对于列轴居中的一个或多个触点,或在一些情况下,未居中的触点可能离列轴更远,使得列轴719可能甚至不穿过该列的这些未居中的触点。在一列或甚至多列中可能有一个、几个或很多触点没有相对于各自列的轴居中。
另外,微电子元件720、730和衬底740很可能包含成组而非成列的触点724,734,747,例如触点的环状、多边形状或甚至分散式分布的布置。
在一个实施例中,同上述模块610类似,模块卡740可以没有延伸穿过其第一表面741和第二表面742之间的孔的引线。
图8是关于图1B所述的实施例的另一种变型。在此变型中,模块810与上述的模块10相同,除了第一微电子元件820的多行导电触点824可大体上垂直于第二微电子元件830的多行导电触点834。在这个实施例中,第二孔846(类似于图1B所示的第二孔46)可具有在背离模块卡840的内插边缘843的方向上延伸的长度L。第一孔845可具有在大体平行于模块卡840的内插边缘843且大体垂直于第二孔846的长度L的方向上延伸的长度L’。
引线870可包括与图1B所示的导电迹线55的图案相同的导电迹线855a的图案。引线870可进一步包括从暴露在模块卡840的第二表面842处的导电触点844b延伸至暴露的边缘触点850的导电迹线855a的可选图案。在特定实施例中,导电迹线855b中的一些可在第一孔845的侧边缘848周围延伸。
图9是关于图1A至图1C所述的实施例的一种变型。在此变型中,模块910与上述的模块10相同,除了第一微电子元件920和第二微电子元件930安装在引线框架980上,而不是安装在模块卡上(例如图1A所示的模块卡40)。在特定实施例中,第一微电子元件920和第二微电子元件930各自的前表面921和931可面对引线框架980的第一表面981,且每个微电子元件电连接至引线框架。
美国专利No.7,176,506和No.6,765,287示出且描述了引线框架结构的示例,其公开内容通过引用并入本文。通常,引线框架(例如引线框架980)是一种由导电金属(如铜)层形成的结构,且图案化成包括多个引线或导电迹线部分985的片段。在示例性实施例中,第一微电子元件920和第二微电子元件930中的至少一个可直接安装在引线上,该引线可在微电子元件之下延伸。在这个实施例中,微电子元件上的触点924、934可通过焊球或类似的电连接至各个引线。然后引线可用于形成与多种其他导电结构的电连接,用于携载到达或来自第一微电子元件920和第二微电子元件930的电子信号电位。当结构组件完整时(包括在其上形成密封剂960),临时元件,比如框架(未示出),可从引线框架980的引线中去除,以形成单独的引线或导电迹线部分985。
第一微电子元件920可通过在第一微电子元件的前表面921与引线框架的第一表面981之间延伸的一个或多个粘合剂层914附接至引线框架980。这种粘合剂层914可类似于以上参考图1A至图1C描述的粘合剂层14。间隔片912可附接至引线框架980,一个或多个粘合剂层914在间隔片的前表面913和引线框架的第一表面981之间延伸。第二微电子元件930的前表面931的至少部分可部分地覆盖第一微电子元件920的后表面922以及间隔片912的后表面915。第二微电子元件930的前表面931可通过一个或多个粘合剂层914附接至第一微电子元件920的后表面922以及间隔片912的后表面915。
如图9A至9C所示,电连接或引线970可将第一微电子元件920的触点924和第二微电子元件930的触点934连接至暴露的模块触点950。引线970可包括线键合971和972,以及引线框架980的导电迹线部分985。在特定示例中,引线970可用于携载地址信号以在第一微电子元件920和第二微电子元件930中的至少一个中对存储器元件寻址。
在一个示例中,引线框架980可限定在引线框架的第一表面981与相对于第一表面981的第二表面982之间延伸的第一间隙945和第二间隙946。第一间隙945可与第一微电子元件920的芯片触点924对齐,使得线键合971可在芯片触点924与引线框架的第二表面982之间延伸穿过第一间隙。第二间隙946可与第二微电子元件930的芯片触点934对齐,使得线键合972可在芯片触点934与引线框架的第二表面982之间延伸穿过第二间隙。
模块910也可包括覆盖第一微电子元件920、第二微电子元件930和部分引线框架980的密封剂960,使得暴露的模块触点950可暴露在密封剂的内插部分961的下表面962处。密封剂960也可覆盖触点924、934,以及在各个触点924、934与引线框架980之间延伸的线键合971、972。当模块910插入插口时,密封剂960的内插部分961可具有与相应的插口(图12所示)对接的合适的尺寸和形状。
在特定实施例中,模块910可具有邻近第一表面981和第二表面982中至少一个的内插边缘983的多个平行的暴露的模块触点950,用于当模块910插入插口时,与插口(图12所示)的相应的触点对接。模块触点950中的一些或全部可暴露在引线框架980的第一表面981和第二表面982中的一个或两个上。
图10A和图10B是关于图2所述的实施例的一种变型。在此变型中,模块1010与上述的模块210相同,除了模块1010还包括安装在模块卡1040上的一叠第三微电子元件1090。
同图2类似,第一微电子元件1020倒装芯片键合至模块卡1040的第一表面1041。第一微电子元件1020的导电触点或芯片触点1024可通过例如导电块1073电连接至暴露在模块卡1040的第一表面1041处的导电触点1047。第二微电子元件1030的芯片触点1034可通过延伸穿过模块卡的孔1046的线键合1072电连接至模块卡1040的相应的导电触点1044。导电迹线(未在图10A和图10B中示出)可沿着模块卡1040的第一表面1041和/或第二表面1042从导电触点1044和1047延伸至暴露在模块卡的内插边缘(例如边缘1043或边缘1043a)处的边缘触点1050。如图10B所示,边缘触点1050可暴露在第一表面1041处,或第二表面1042处,或第一表面和第二表面处。
这叠第三微电子元件1090可为任意数目,包括,例如图10B所示的两个第三微电子元件1090a和1090b。第三微电子元件1090可通过互连结构相互连接,和/或与边缘触点1050连接。例如,下第三微电子元件1090a可通过倒装芯片键合、线键合、引线键合或其他互连结构与暴露在模块卡1040的表面处的触点连接。一个或多个上第三微电子元件1090b可通过延伸穿过下第三微电子元件1090a的导电通孔、线键合、引线键合或其他互连结构与模块卡1040的触点连接。
在示例性实施例中,模块1010可配置为用作固态存储驱动。在这种示例中,第一微电子元件1020可包括主要用于执行逻辑功能的半导体芯片,例如固态驱动控制器,且第二微电子元件1030可包括存储器存储元件,例如易失性RAM(如DRAM)。第三微电子元件1090可包括存储器存储元件,例如非易失性闪存。第一微电子元件1020可包括专用处理器,专用处理器用于解除系统(例如图12的系统1200)的中央处理单元对出入包括在第二微电子元件1030和第三微电子元件1090中的存储器存储元件的数据的传输的管理。这种包括固态驱动控制器的第一微电子元件1020可以提供至和从系统(例如系统1100)的母板(例如,图12所示的电路板1202)上的数据总线的直接存储访问。
在另一实施例中,模块1010可配置为用作图形模块,例如可插入笔记本电脑的PCI显卡插槽。在这种示例中,第一微电子元件1020可包括主要用于执行逻辑功能的半导体芯片,例如图形处理器,且第二微电子元件1030可包括存储器存储元件,例如易失性RAM(如DRAM),其可用作计算图形绘制的易失性帧缓冲器。每个第三微电子元件1090可包括存储器存储元件(例如非易失性闪存)。
图10C是关于图10A和图10B所述的实施例的一种变型。在此变型中,模块1010’与上述的模块1010相同,除了模块1010’包括安装在模块卡1040上的相互相邻的而非堆叠的多个第三微电子元件1090’。同模块1010类似,第三微电子元件1090’可通过任何互连结构(例如倒装芯片键合、线键合、引线键合或其他互连结构)与暴露在模块卡1040的表面处的触点相连。模块1010’可用于与模块1010相同的示例性功能,例如固态内存驱动或图形模块。
图11描述了包括根据上述任一实施例的第一模块1110a和第二模块1110b(例如图1A至图1C所述的模块10)的部件1100。第一模块1110a和第二模块1110b可通过至少一个层1165相互键合,使得模块的各个模块卡1140的第二表面1142相互面对。在特定实施例中,上述至少一个层1165可为单个共同的密封剂(如图1A和1B所示的第二密封剂65)。在另一示例中,上述至少一个层1165可为类似于参考图1A至图1C所述的粘合剂层14的一个或多个粘合剂层。
部件1100可具有邻近部件的内插边缘1143的一行或多行平行的暴露的边缘触点1150。第一模块1110a和第二模块1110b中的每一个可具有一行暴露在各个模块卡1140的第一表面1141处的边缘触点1150,使得当部件1100插入插口时,这种边缘触点可以适合于与插口(类似于图12所示的插口)的相应的触点对接。
参考图1A至图10所述的模块和部件可用于构建多种电子系统,例如图12所示的系统1200。例如,根据本发明进一步实施例的系统1200包括上述的多个模块或部件1206,以及其他电子部件1208和1210。
系统1200可包括多个插口1205,每个插口包括在插口一侧或两侧的多个触点1207,使得每个插口1205可适合于与相应的模块或部件1206的相应的暴露的边缘触点或暴露的模块触点对接。在所示的示例性系统1200中,系统可包括电路板或主板1202(例如柔性印刷电路板),电路板包括将模块或部件1206彼此互连的很多个导体1204,在图12中仅示出其中一个导体。然而,这只是示例性的;可以使用用于制造模块或部件1206之间的电连接的任何适当的结构。
在特定实施例中,系统1200还可包括处理器(如半导体芯片1208),使得每个模块或部件1206可用于在时钟周期内传送N个并行数据位,且处理器可用于在时钟周期内传送M个并行数据位,M大于或等于N。
在一个示例中,系统1200可包括用于在时钟周期内传送32个并行数据位的处理器芯片1208,且该系统也可包括四个模块1206(例如参考图1A至1C所述的模块10),每个模块1206用于在时钟周期内传送8个并行数据位(即每个模块1206可包括第一微电子元件和第二微电子元件,两个微电子元件中的每个用于在时钟周期内传送4个并行数据位)。
在另一个示例中,系统1200可包括用于在个时钟周期内传送64个并行数据位的处理器芯片1208,且该系统也可包括四个模块1206(例如参考图12所述的部件1000),每个模块1206用于在时钟周期内传送16个并行数据位(即每个模块1206可包括两组第一微电子元件和第二微电子元件,四个微电子元件中的每一个用于在时钟周期内传送4个并行数据位)。
在图12所述的示例中,部件1208是半导体芯片且部件1210是显示屏,但任何其他部件可用于系统1200中。当然,尽管为了说明的清楚性,在图12中仅示出了两个额外的部件1208和1210,但系统可以包括任何数量的这种部件。
模块或部件1206和部件1208及1210安装在共用的壳体1201(以虚线示意地示出)中,并在必要时彼此电互连以形成期望的电路。壳体1201被示为在例如移动电话或个人数字助理中可用的类型的便携式壳体,屏幕1210可以暴露在壳体的表面处。在结构1206包括感光元件(例如成像芯片)的实施例中,还可以设置透镜1211或其他光学装置用于将光导向到该结构。此外,图12所示的简化的系统只是示例性的;可以使用上述的结构制造其他系统,包括通常被认为是固定结构的系统,例如台式电脑、路由器等。
图13A和图13B是关于图7A和图7B所述的实施例的一种变型。在此变型中,微电子封装1310与上述的模块710相同,除了微电子封装1310包括安装至衬底1340而非模块卡的微电子元件1320和1330,且微电子封装1310具有用于与部件而非边缘触点互连的端子1350。在一个实施例中,同上述模块710类似,衬底1340可以没有延伸穿过衬底的孔的引线。
第一微电子元件1320可具有面对衬底1340的第一表面1341的前表面1321。第一微电子元件1320可具有在第一微电子元件的前表面1321处的多个元件触点1324。元件触点1324可与第一组衬底触点1347a联接,使得元件触点与衬底触点倒装芯片键合。如图13B所示,元件触点1324和第一组衬底触点1347a都可布置成面阵结构。
第二微电子元件1330可具有面对衬底1340的第一表面1341的前表面1331。第二微电子元件1330的前表面1331可部分地覆盖第一微电子元件1320的后表面1322,且可例如通过粘合剂层1314附接至后表面1322。
第二微电子元件1330可具有在其前表面1331处的多个元件触点1334。元件触点1334可与第二组衬底触点1347b联接,使得元件触点与衬底触点倒装芯片键合。如图13B所示,元件触点1334和第二组衬底触点1347b都可布置成列结构。
尽管触点1324、1334和1347布置成示出的平行的触点列,但是如以上参考图7A-7C所述的,本发明也考虑了触点的其他布置方式。
衬底1340可进一步包括在第二表面1342处的多个端子1350,用于将微电子封装1310连接至封装外部的一个部件。导电块1351可布置在端子1350的暴露的表面上。这种导电块1351可为,例如,焊球或参考导电块273上述任何其他材料。在一个示例中,外部部件可为在下文参考图16描述的电路板(如电路板1602)。
触点1324和1334可通过例如各个导电块1373和1375电连接至各组衬底触点1347a和1347b。导电块1373可为,例如,焊球或参考导电块273的上述任何其他材料。导电块1375可为,例如,细长的焊料连接,焊球或参考导电块273的上述任何其他材料。
如图14A所示,在图13A和图13B的实施例的变型中,导电块1375和/或导电块1373可至少部分由导电接线柱1475代替。导电接线柱可包括沉积(如涂覆或电镀)在开口之内的部分,第二微电子元件的触点1434暴露在开口内。例如,导电接线柱1475可在延伸至少部分穿过密封剂1460的相应的孔1476中通过沉积金属或其他导电材料(如导电基体材料)而形成,且利用了例如美国专利公开No.2012/0126389所述的工艺,其公开内容通过引用并入本文。
在另一个变型中,如图14B所示,接线柱可包括多个突出远离第二微电子元件1430的元件触点1434而朝向相应的衬底触点1447b的截头锥形接线柱1477。每个接线柱1477基本上包括大体刚性的导电材料,例如,金属(如铜或铝)。在一个实施例中,接线柱1477可由刻蚀一种结构(例如附接至触点的连续的或非连续的金属片)形成。导电块1473可设置在接线柱1477和衬底触点1447b之间以提供其间的电连接。如图14B所示,接线柱1477可为锥形,使得每个接线柱具有大于邻近衬底触点1447b的第二宽度的邻近元件触点1434的第一宽度。
参见图14C,在图14B的实施例的变型中,接线柱可包括多个突出远离衬底触点1447b而朝向相应的第二微电子元件1430的元件触点1434的截头锥形接线柱1478。导电块1473可设置在接线柱1478和元件触点1434之间以提供其间的电连接。如图14C所示,接线柱1478可为锥形,使得每个接线柱具有大于邻近元件触点1434的第二宽度的邻近衬底触点1447b的第一宽度。
参见图14D,在另一个变型中,至少一些导电块1375可被导电接线柱1479a和1479b代替,接线柱1479a从第二微电子元件1430的元件触点1434朝向一些相应的衬底触点1447b延伸,且接线柱1479b从衬底触点朝向接线柱1479a延伸。导电块1473可设置在导电接线柱1479a和1479b之间以提供其间的电连接。如图14D所示,线柱1479a和1479b都可以是锥形,使得每个接线柱具有大于邻近导电块1473的第二宽度的邻近元件触点1434或衬底触点1447b的第一宽度。
参见图14E,在图14B的实施例的另一个变型中,细长的焊料连接1480可设置在衬底触点1447b与第二微电子元件1430的相应的元件触点1434之间的接线柱1477周围,以提供接线柱和衬底触点之间的电连接。图14B、14C和14D的任一实施例所示的导电块1473可被在元件触点1434和衬底触点1447b之间的各个接线柱1477,1478和1479周围延伸的被细长的焊料连接1480代替。
图15是关于图6所述的实施例的一种变型。在此变型中,微电子封装1510与上述的模块610相同,除了微电子封装1510包括安装至衬底1540而非模块卡的微电子元件1520和1530,且微电子封装1510具有暴露在第二表面1542处的用于将封装1510与另一部件互连的端子1550,而不是图6所示实施例中的边缘触点。在一个实施例中,同上述模块610类似,衬底1540可以没有延伸穿过衬底的孔的引线。
类似于上述模块10,第二微电子元件1530的导电触点1534可暴露在第二微电子元件的中心区域1535内的前表面1531处。例如,触点1534可布置成成邻近前表面1531的中心的一行或平行的两行。
导电块1575可为,例如,细长的焊料连接,焊球或参考导电块273的上述任何其他材料。这种导电块1575可延伸穿过间隔片1512与第一微电子元件1520的侧边缘1523之间的空隙,以将第二微电子元件1530与衬底1540电连接。
图15所示的导电块1575可被元件触点1534和衬底触点1547b(如图14A至14E所示)之间的任一可选连接代替。
参考图13A至图15所述的任一微电子封装可包括额外的微电子元件,例如图10A和10B所示的第三微电子元件1090a和1090b(共同地为第三微电子元件1090),以及图10C所示的第三微电子元件1090’。
在特定实施例中,微电子封装1310(或1510)可包括,在类似于图10B所示的微电子元件布置的构造中,安装在衬底1340的第一表面1341上的一叠第三微电子元件1090。在这种实施例中,第三微电子元件1090a和1090b都具有面对衬底的第一表面1341的表面,该表面与微电子元件1320和1330的前表面1321和1331所面对的衬底的表面相同。这种包括第三微电子元件1090的衬底1340还可具有第二表面1342处的用于与另一部件互连的端子1350,而不是图10B所示的边缘触点。在这种实施例中,这一堆叠中可有任何数目的第三微电子元件1090,包括,例如图10B所示的实施例中的两个第三微电子元件1090a和1090b。
在一个示例中,微电子封装1310(或1510)可包括,在类似于图10C所示的微电子元件布置的构造中,安装在衬底1340的第一表面1341上的相邻的而非堆叠的多个第三微电子元件1090’。在这种实施例中,每个第三微电子元件1090’可具有面对衬底的第一表面1341的一个表面,该表面与微电子元件1320和1330的前表面1321和1331所面对的衬底的表面相同。这种包括第三微电子元件1090’的衬底1340还可具有第二表面1342处的用于与另一部件互连的端子1350,而不是图10C所示的边缘触点。在这种实施例中,这一堆叠中可有任何数目的第三微电子元件1090’,包括,例如图10C所示的实施例中的四个第三微电子元件1090’。
参考图1A至图15所述的模块和微电子封装可被用来构造多种电子系统,例如图16所示的系统1600。例如,根据本发明的进一步实施例的系统1600包括一个或多个模块或部件1606(例如上述微电子封装1310)以及其他电子部件1608和1610。
在所示的示例性系统1600中,系统可包括电路板、主板或扩展板1602(例如柔性印刷电路板),电路板包括将模块或部件1606彼此互连的很多个导体1604,在图16中仅示出其中一个导体。这种电路板1602可传输到达或来自包括在系统1600内的微电子封装和/或微电子组件的信号。然而,这只是示例性的;可以使用用于制造模块或部件1606之间的电连接的任何适当的结构。
在特定实施例中,系统1600还可包括处理器(如半导体芯片1608),使得每个模块或部件1606可用于在时钟周期内传送N个并行数据位,且处理器可用于在时钟周期内传送M个并行数据位,M大于或等于N。
在图16所述的示例中,部件1608是半导体芯片且部件1610是显示屏,但任何其他部件可用于系统1600中。当然,尽管为了说明的清楚性,在图16中仅示出了两个额外的部件1608和1610,但系统1600可以包括任何数量的这种部件。
模块或部件1606和部件1608及1610可安装在共用的壳体1601(以虚线示意地示出)中,并在必要时彼此电互连以形成期望的电路。壳体1601被示为在例如移动电话或个人数字助理中可用的类型的便携式壳体,屏幕1610可以暴露在壳体的表面处。在结构1606包括感光元件(例如成像芯片)的实施例中,还可以设置透镜1611或其他光学装置用于将光导向到该结构。此外,图16所示的简化的系统只是示例性的;可以使用上述的结构制造其他系统,包括通常被认为是固定结构的系统,例如台式电脑、路由器等。
根据本发明的模块或部件的一个潜在优势在于(例如图1A至图1C所示的模块10,其中第一微电子元件的表面覆盖第二微电子元件的后表面的至少一部分)可用于提供,将一个特定的暴露的边缘触点(例如暴露的边缘触点50)与暴露在一个特定的微电子元件(例如第一微电子元件20)的前表面处的一个特定的电触点(例如电触点24)电连接的较短的引线。在相邻引线之间的寄生电容是相当大的,尤其是在具有高触点密度和小间距的微电子组件中。在具有较短的引线70的微电子组件中(如模块10),可以减小寄生电容,尤其是相邻引线间的寄生电容。
根据本发明的模块或部件的另一个潜在优势在于,如上所述,其可用于提供相似长度的引线(如引线70),例如将数据输入/输出信号端子(例如暴露的边缘触点50)与第一微电子元件20和第二微电子元件30的各自的前表面处的电触点24、34电连接。在系统(例如包括多个模块或部件1206的系统1200)中,具有相对相似长度的引线70,可以允许每个微电子元件和暴露的边缘触点之间的数据输入/输出信号的传播延迟可以相对地高度匹配。
根据本发明的模块或部件的另一个潜在优势在于,如上所述,其可用于提供相似长度的引线(如引线70),然后,例如,可将共享时钟信号端子和/或共享数据选通信号端子(例如,暴露的边缘触点50)与第一微电子元件20和第二微电子元件30的各自的前表面处的电触点24、34电连接。数据选通信号端子或时钟信号端子或两者可以具有至各个微电子元件20和微电子元件30的大致相同的加载和导电路径长度,而且至每个微电子元件的路径长度可相对较短。
在前述的任一或所有模块或部件中,第一微电子元件或第二微电子元件中的一个或多个的后表面可在完成制作后至少部分地暴露在微电子组件的外表面处。因此,在参考图1A至1C所述的组件中,第一微电子元件20和第二微电子元件30的各自的后表面22和32中的一个或两个可部分地或完全暴露在已完成的模块10内。虽然包胶模(如第一密封剂60)或其他密封或封装结构可接触或被设置成邻近微电子元件,但是后表面22和32可被部分地或完全暴露。
在上述任一实施例中,微电子组件可包括由金属、石墨或任何其他合适的导热材料制成的散热器。在一个实施例中,散热器包括邻近第一微电子元件设置的金属层。金属层可暴露在第一微电子元件的后表面上。可选地,散热器可包括至少覆盖第一微电子元件的后表面的包胶模或密封剂。
尽管已经参考特定实施例对本发明进行了描述,应该理解的是这些实施例仅仅是对本发明的原理和应用的说明。因此,应理解的是,在不脱离通过所附权利要求限定的本发明的精神和范围的情况下,可以对上述说明性实施例进行各种修改以及可以设计其他布置。
应理解的是,各个从属权利要求及其中列举的特征可以以不同的方式与原始权利要求中的特征相结合。还应理解的是,结合各个实施例描述的特征可与所述实施例的其他特征共享。
工业实用性
本发明具有广泛的工业实用性,包括但不限于微电子封装及微电子封装的制造方法。
权利要求书(按照条约第19条的修改)
1.一种微电子封装,包括:
衬底,所述衬底具有相对的第一表面和第二表面,以及在所述第一表面处的多个衬底触点和在所述第二表面处的多个端子,用于将所述微电子封装连接到所述封装外部的至少一个部件;以及
第一微电子元件和第二微电子元件,所述第一微电子元件和第二微电子元件分别具有面对所述衬底的第一表面的前表面,每个微电子元件具有在其所述前表面处的多个元件触点,每个微电子元件的所述元件触点与相应的所述衬底触点相联接,所述第二微电子元件的所述前表面部分覆盖且附接至所述第一微电子元件的后表面,所述第二微电子元件的所述元件触点暴露在所述第二微电子元件的所述前表面的中心区域内,
其中所述第一微电子元件的所述元件触点布置在面阵中且与第一组所述衬底触点倒装芯片键合,所述第二微电子元件的所述元件触点通过导电块与第二组所述衬底触点相联接。
2.根据权利要求1所述的微电子封装,其中所述第二微电子元件的所述元件触点突出于所述第一微电子元件的侧边缘之外。
3.根据权利要求1所述的微电子封装,其中所述第一微电子元件和第二微电子元件中的至少一个包括存储器元件。
4.根据权利要求3所述的微电子封装,还包括从至少一些所述衬底触点延伸至所述端子的多个引线,其中所述引线可用于携载地址信号以在所述第一微电子元件和第二微电子元件中的至少一个中对所述存储器元件寻址。
5.根据权利要求1所述的微电子封装,其中至少一些所述端子可用于携载所述各个端子与所述第一微电子元件和第二微电子元件中的每个之间的信号或参考电位中的至少一个。
6.根据权利要求1所述的微电子封装,还包括多个第三微电子元件,每个第三微电子元件电连接至所述衬底。
7.根据权利要求6所述的微电子封装,其中所述多个第三微电子元件布置成堆叠结构,每个所述第三微电子元件具有与一个相邻的所述第三微电子元件的前表面或后表面相面对的前表面或后表面。
8.根据权利要求6所述的微电子封装,其中所述多个第三微电子元件布置成平面结构,每个所述第三微电子元件具有与一个相邻的所述第三微电子元件的外围表面相面对的外围表面。
9.根据权利要求6所述的微电子封装,其中所述第二微电子元件包括易失性RAM,每个所述第三微电子元件包括非易失性闪存,且所述第一微电子元件包括主要用于控制外部组件与所述第二微电子元件和第三微电子元件之间的数据传送的处理器。
10.根据权利要求6所述的微电子封装,其中所述第二微电子元件包括易失性帧缓冲存储器元件,每个所述第三微电子元件包括非易失性闪存,且所述第一微电子元件包括图形处理器。
11.根据权利要求1所述的微电子封装,其中第二微电子元件的所述元件触点布置成邻近所述第二微电子元件的所述前表面的中心的一行或平行的两行。
12.根据权利要求1所述的微电子封装,其中所述导电块为细长的焊料连接。
13.一种系统,包括多个根据权利要求1所述的微电子封装、电路板和处理器,所述微电子封装的所述端子与所述电路板的板触点电连接,每个微电子封装用于在时钟周期内传送N个并行数据位,所述处理器用于在时钟周期内传送M个并行数据位,M大于或等于N。
14.一种系统,包括根据权利要求1所述的微电子封装,以及电连接至所述微电子封装的一个或多个其他电子部件。
15.根据权利要求14所述的系统,还包括壳体,所述微电子封装和所述其他电子部件安装至所述壳体。
16.一种模块,包括:
模块卡,所述模块卡具有第一表面,第二表面和多个平行的暴露的边缘触点,所述边缘触点邻近所述第一表面和第二表面中的至少一个的边缘,用于当所述模块插入插口时,与插口相应的触点对接,所述模块卡具有在所述第一表面上的多个卡触点;以及
第一微电子元件和第二微电子元件,所述第一微电子元件和第二微电子元件分别具有面对所述模块卡的所述第一表面的前表面,每个微电子元件具有在其所述前表面处的多个元件触点,每个微电子元件的所述元件触点与相应的所述卡触点相联接,所述第二微电子元件的所述前表面部分覆盖且附接至所述第一微电子元件的后表面,所述第二微电子元件的所述元件触点暴露在所述第二微电子元件的所述前表面的中心区域内,
其中所述第一微电子元件的所述元件触点布置在面阵中且与第一组所述卡触点倒装芯片键合,所述第二微电子元件的所述元件触点通过导电块与第二组所述卡触点相联接。
17.根据权利要求16所述的模块,其中所述第二微电子元件的所述元件触点突出于所述第一微电子元件的侧边缘之外。
18.根据权利要求16所述的模块,其中所述边缘触点暴露在所述模块卡的所述第一表面或第二表面中的至少一个处。
19.根据权利要求16所述的模块,其中所述第一微电子元件和第二微电子元件中的至少一个包括存储器元件。
20.根据权利要求19所述的模块,还包括从至少一些所述卡触点延伸至所述边缘触点的多个引线,其中所述引线可用于携载地址信号以在所述第一微电子元件和第二微电子元件中的至少一个中对所述存储器元件寻址。
21.根据权利要求16所述的模块,其中至少一些所述边缘触点可用于携载所述各个边缘触点与所述第一微电子元件和第二微电子元件中的每个之间的信号或参考电位中的至少一个。
22.根据权利要求16所述的模块,还包括多个第三微电子元件,每个第三微电子元件电连接至所述模块卡。
23.根据权利要求22所述的模块,所述多个第三微电子元件布置成堆叠结构,每个所述第三微电子元件具有与一个相邻的所述第三微电子元件的前表面或后表面相面对的前表面或后表面。
24.根据权利要求22所述的模块,所述多个第三微电子元件布置成平面结构,每个所述第三微电子元件具有与一个相邻的所述第三微电子元件的外围表面相面对的外围表面。
25.根据权利要求22所述的模块,其中所述第二微电子元件包括易失性RAM,每个所述第三微电子元件包括非易失性闪存,且所述第一微电子元件包括主要用于控制外部组件与所述第二微电子元件和第三微电子元件之间的数据传送的处理器。
26.根据权利要求22所述的模块,其中所述第二微电子元件包括易失性帧缓冲存储器元件,每个所述第三微电子元件包括非易失性闪存,且所述第一微电子元件包括图形处理器。
27.根据权利要求16所述的模块,其中第二微电子元件的所述元件触点布置成邻近所述第二微电子元件的所述前表面的中心的一行或平行的两行。
28.根据权利要求16所述的模块,其中所述导电块为细长的焊料连接。
29.一种系统,包括多个根据权利要求16所述的模块、电路板和处理器,所述模块的所述暴露的触点插入至与所述电路板电连接的对接插口,每个模块用于在时钟周期内传送N个并行数据位,所述处理器用于在时钟周期内传送M个并行数据位,且M大于或等于N。
30.一种系统,包括根据权利要求16所述的模块,以及电连接至所述模块的一个或多个其他电子部件。
31.根据权利要求30所述的系统,还包括壳体,所述模块和所述其他电子部件安装至所述壳体。

Claims (27)

1.一种微电子封装,包括:
衬底,所述衬底具有相对的第一表面和第二表面,以及在所述第一表面处的多个衬底触点和在所述第二表面处的多个端子,用于将所述微电子封装连接到所述封装外部的至少一个部件;以及
第一微电子元件和第二微电子元件,所述第一微电子元件和第二微电子元件分别具有面对所述衬底的第一表面的前表面,每个微电子元件具有在其所述前表面处的多个元件触点,每个微电子元件的所述元件触点与相应的所述衬底触点相联接,所述第二微电子元件的所述前表面部分覆盖且附接至所述第一微电子元件的后表面,
其中所述第一微电子元件的所述元件触点布置在面阵中且与第一组所述衬底触点倒装芯片键合,所述第二微电子元件的所述元件触点通过导电块与第二组所述衬底触点相联接。
2.根据权利要求1所述的微电子封装,其中所述第二微电子元件的所述元件触点突出于所述第一微电子元件的侧边缘之外。
3.根据权利要求1所述的微电子封装,其中所述第一微电子元件和第二微电子元件中的至少一个包括存储器元件。
4.根据权利要求3所述的微电子封装,还包括从至少一些所述衬底触点延伸至所述端子的多个引线,其中所述引线可用于携载地址信号以在所述第一微电子元件和第二微电子元件中的至少一个中对所述存储器元件寻址。
5.根据权利要求1所述的微电子封装,其中至少一些所述端子可用于携载所述各个端子与所述第一微电子元件和第二微电子元件中的每个之间的信号或参考电位中的至少一个。
6.根据权利要求1所述的微电子封装,还包括多个第三微电子元件,每个第三微电子元件电连接至所述衬底。
7.根据权利要求6所述的微电子封装,其中所述多个第三微电子元件布置成堆叠结构,每个所述第三微电子元件具有与一个相邻的所述第三微电子元件的前表面或后表面相面对的前表面或后表面。
8.根据权利要求6所述的微电子封装,其中所述多个第三微电子元件布置成平面结构,每个所述第三微电子元件具有与一个相邻的所述第三微电子元件的外围表面相面对的外围表面。
9.根据权利要求6所述的微电子封装,其中所述第二微电子元件包括易失性RAM,每个所述第三微电子元件包括非易失性闪存,且所述第一微电子元件包括主要用于控制外部组件与所述第二微电子元件和第三微电子元件之间的数据传送的处理器。
10.根据权利要求6所述的微电子封装,其中所述第二微电子元件包括易失性帧缓冲存储器元件,每个所述第三微电子元件包括非易失性闪存,且所述第一微电子元件包括图形处理器。
11.一种系统,包括多个根据权利要求1所述的微电子封装、电路板和处理器,所述微电子封装的所述端子与所述电路板的板触点电连接,每个微电子封装用于在时钟周期内传送N个并行数据位,所述处理器用于在时钟周期内传送M个并行数据位,M大于或等于N。
12.一种系统,包括根据权利要求1所述的微电子封装,以及电连接至所述微电子封装的一个或多个其他电子部件。
13.根据权利要求12所述的系统,还包括壳体,所述微电子封装和所述其他电子部件安装至所述壳体。
14.一种模块,包括:
模块卡,所述模块卡具有第一表面,第二表面和多个平行的暴露的边缘触点,所述边缘触点邻近所述第一表面和第二表面中的至少一个的边缘,用于当所述模块插入插口时,与插口相应的触点对接,所述模块卡具有在所述第一表面上的多个卡触点;以及
第一微电子元件和第二微电子元件,所述第一微电子元件和第二微电子元件分别具有面对所述模块卡的所述第一表面的前表面,每个微电子元件具有在其所述前表面处的多个元件触点,每个微电子元件的所述元件触点与相应的所述卡触点相联接,所述第二微电子元件的所述前表面部分覆盖且附接至所述第一微电子元件的后表面,
其中所述第一微电子元件的所述元件触点布置在面阵中且与第一组所述卡触点倒装芯片键合,所述第二微电子元件的所述元件触点通过导电块与第二组所述卡触点相联接。
15.根据权利要求14所述的模块,其中所述第二微电子元件的所述元件触点突出于所述第一微电子元件的侧边缘之外。
16.根据权利要求14所述的模块,其中所述边缘触点暴露在所述模块卡的所述第一表面或第二表面中的至少一个处。
17.根据权利要求14所述的模块,其中所述第一微电子元件和第二微电子元件中的至少一个包括存储器元件。
18.根据权利要求17所述的模块,还包括从至少一些所述卡触点延伸至所述边缘触点的多个引线,其中所述引线可用于携载地址信号以在所述第一微电子元件和第二微电子元件中的至少一个中对所述存储器元件寻址。
19.根据权利要求14所述的模块,其中至少一些所述边缘触点可用于携载所述各个边缘触点与所述第一微电子元件和第二微电子元件中的每个之间的信号或参考电位中的至少一个。
20.根据权利要求14所述的模块,还包括多个第三微电子元件,每个第三微电子元件电连接至所述模块卡。
21.根据权利要求20所述的模块,所述多个第三微电子元件布置成堆叠结构,每个所述第三微电子元件具有与一个相邻的所述第三微电子元件的前表面或后表面相面对的前表面或后表面。
22.根据权利要求20所述的模块,所述多个第三微电子元件布置成平面结构,每个所述第三微电子元件具有与一个相邻的所述第三微电子元件的外围表面相面对的外围表面。
23.根据权利要求20所述的模块,其中所述第二微电子元件包括易失性RAM,每个所述第三微电子元件包括非易失性闪存,且所述第一微电子元件包括主要用于控制外部组件与所述第二微电子元件和第三微电子元件之间的数据传送的处理器。
24.根据权利要求20所述的模块,其中所述第二微电子元件包括易失性帧缓冲存储器元件,每个所述第三微电子元件包括非易失性闪存,且所述第一微电子元件包括图形处理器。
25.一种系统,包括多个根据权利要求14所述的模块、电路板和处理器,所述模块的所述暴露的触点插入至与所述电路板电连接的对接插口,每个模块用于在时钟周期内传送N个并行数据位,所述处理器用于在时钟周期内传送M个并行数据位,且M大于或等于N。
26.一种系统,包括根据权利要求1所述的模块,以及电连接至所述模块的一个或多个其他电子部件。
27.根据权利要求26所述的系统,还包括壳体,所述模块和所述其他电子部件安装至所述壳体。
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