CN104167993A - Differential low-power consumption and low noise amplifier with active transconductance enhancement and noise counteraction technology adopted - Google Patents

Abstract

The invention provides a differential low-power low-noise amplifier using active transconductance enhancement and noise cancellation technology, which includes a main common-gate amplifier stage (1), an active transconductance-enhanced amplifier stage (2), a balanced amplifier Balance transformer (3) and load impedance (4). The present invention adopts the cascading mode of the active transconductance enhancement stage and the main common grid amplifier stage to enhance the transconductance of the main common grid amplifier tube, and also adopts the transconductance enhancement technology for the active transconductance enhanced amplifier tube, Higher equivalent transconductance is realized with low power consumption; when the first-stage and second-stage amplifying circuits have the same gain, the noise contribution of the main common-gate amplifying stage can be suppressed. The use of differential structure makes the circuit have stronger interference ability to environmental noise. The invention realizes low noise factor and low power consumption through the combination of transconductance secondary enhancement and noise cancellation technology.

Description

A Differential Low Power Low Noise Amplifier Using Active Transconductance Enhancement and Noise Cancellation

technical field

The invention relates to a differential low-power low-noise amplifier using active transconductance enhancement and noise cancellation technology, which has the characteristics of low noise figure and low power consumption, and belongs to the technical field of radio frequency integrated circuits.

Background technique

The low noise amplifier is the key module of the receiver in the wireless transmission system. Its main function is to amplify the weak signal received by the antenna from the air and transmit it to the subsequent stage while maintaining low noise. Because it is at the forefront of radio frequency reception, the low noise amplifier has a significant impact on the performance of the entire receiver. Matching input and output ports, low noise figure, sufficient gain, proper power consumption and linearity are the basic requirements for LNA design.

Traditional low-noise amplifiers generally use source inductance feedback technology, but require on-chip inductors and occupy too much area. Although traditional common-gate amplifiers can easily achieve input matching and lower power consumption, their noise figure is relatively large. Inductorless low noise amplifiers have begun to appear in the last few years. They can generally be divided into two categories: the first are common-source amplifiers with resistive or active feedback, and the second are common-gate amplifiers combined with transconductance enhancement or noise cancellation. However, these structures have certain compromises in performance such as gain, noise, linearity, and power consumption.

Common-gate amplifiers are more linear because they provide less voltage gain than parallel feedback amplifiers. Moreover, the common-gate amplifier can effectively use the gate terminal to realize the transconductance enhancement technology. Figure 1, reference [1] (Saghyun Woo, Woonyun Kim Chang-Ho Lee, Kyutae Lim, Joy Laskar, ―A 3.6mW differential common-gate CMOS LNA with positive-negative feedback,‖ISSCC 2009/SESSION 12/RF BUILDING BLOCKS/ 12.2.) This transconductance enhancement structure is often used to reduce power consumption.

Although the linearity of the common gate amplifier is better, the noise performance is worse than the amplifier with parallel feedback. Therefore, the use of a common-gate amplifier structure has to overcome the problem of noise deterioration. Figure 2, reference [2] (Chih-Fan Liao, Shen-Iuan Liu, ―A Broadband Noise-Canceling CMOS LNA for 3.1–10.6-GHz UWB Receivers, ‖ IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.42, NO. 2, FEBRUARY 2007.) Provided a noise-cancelling common-gate amplifier structure, which can effectively reduce the noise of the common-gate amplifier.

In order to overcome the performance shortcomings of LNAs, a low-noise amplifier with wideband, inductance and low power consumption is proposed. Figure 3, reference [3] (Hongrui Wang, Li Zhang, and Zhiping Yu, ―A Wideband InductorlessLNA With Local Feedback and Noise Canceling for Low-Power Low-Voltage Applications,‖IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS , VOL.57, NO.8, AUGUST 2010.) It uses both transconductance enhancement and noise cancellation technology to achieve the goal of low power consumption and low noise. However, the single-ended circuit is adopted in this paper, and its anti-interference ability to environmental noise is not strong.

Contents of the invention

The purpose of the present invention is to provide a differential low-power low-noise amplifier using active transconductance enhancement and noise cancellation technology, which solves the problems of high noise factor and high power consumption of the existing low-power common-gate low-noise amplifier. The amplifier of the invention adopts a differential structure to make the circuit have stronger interference ability to environmental noise, and realizes the performance of low noise figure and low power consumption through the combination of transconductance secondary enhancement and noise canceling technology. The design can be used in RF transceiver CMOS integrated circuits.

For this reason, the present invention provides following technical scheme:

The technical solution of the present invention: a differential low-power low-noise amplifier using active transconductance enhancement and noise cancellation technology, which includes a main common-gate amplifier stage 1, an active transconductance-enhanced amplifier stage 2, and a balanced unbalanced transformer 3 and load impedance 4; the input signal enters from the input port of the balanced unbalanced transformer 3, and its differential output port is directly coupled with the source end of the active transconductance-enhanced amplifier stage 2 and the source end of the main common-gate amplifier stage 1, and also Capacitively coupled to the gate terminal of the active transconductance enhanced amplifier stage 2; the active transconductance enhanced amplifier stage 2 adopts a symmetrical structure of NMOS and PMOS, and the NMOS structure adopts the cascode form; the active transconductance enhanced amplifier stage The drain terminal of 2 is capacitively coupled to the gate of the main common-gate amplifier stage 1; the load impedance 4 is connected to the drain of the cascode tube of the main common-gate amplifier stage 1 and active transconductance-enhanced amplifier stage 2; the output of the circuit The terminal is located at the drain of the main common gate amplifier stage 1.

Among them, the main common-gate amplifier stage 1 uses two identical N-type transistors NM1 and NM5 as input amplifier tubes, the gate terminals of NM1 and NM5 are respectively connected to the bias voltage through a large resistor, and the two ends of the capacitor C1 are respectively connected to the gate of NM1 Pole, drains of NM2 and PM4, and source of NM3, the two ends of capacitor C2 are respectively connected to the input positive signal and the gate of PM4, and the two ends of capacitor C3 are respectively connected to the input positive signal and the gate of NM2, active transconductance Enhanced amplifier stage 2 uses N-type transistor NM2 and P-type transistor PM4 as input amplifier tubes, the positive signal of the differential signal is coupled to the gate terminals of NM2 and PM4 through a capacitor, the negative signal of the differential signal is directly connected to the source terminal of NM2, PM4 The source terminal of NM3 is connected to the power supply, and an N-type transistor NM3 with a cascode structure is added to NM2. The source terminal of NM3 is connected to the drain terminals of NM2 and PM4, the gate terminal is connected to the bias voltage through a large resistor, and the drain terminal is connected to The load resistors Z1 and Z3, the gate terminals of PM4 and NM2 are respectively connected to the bias voltage through a large resistance; the single-ended input terminal ① of the balanced unbalanced transformer 3 is connected to the signal source, and the balanced output terminal ③ is directly coupled to the source level of NM1 and NM6 The source of NM2 and PM4 is coupled to the gate of NM2 and PM4 through capacitance, the other balanced output ④ is directly coupled to the source of NM2 and the source of NM5 and coupled to the gate of NM6 and PM8 through capacitance, the second terminal ② and The fifth terminal ⑤ is grounded; the load impedance 4 is composed of impedances Z1, Z2, Z3 and Z4, the two ends of Z1 are respectively connected to the power supply and the drain of NM3, and the two ends of Z2 are respectively connected to the drain of NM1 and the drain of NM3.

The advantage of the present invention compared with prior art is:

1. Compared with the single-ended structure, the use of differential structure has advantages in eliminating the influence of parasitic effects, which makes the circuit have stronger anti-interference ability to environmental noise;

2. The method of active transconductance enhancement is used to enhance the transconductance of the main common-gate amplifier twice, and the transconductance enhancement technology is also used for the active transconductance enhancement tube to achieve a larger equivalent transconductance with low power consumption , which reduces the power consumption of the circuit;

3. Reasonable design of the resistance of each load can basically eliminate the noise of the main common grid amplifier tube and improve the noise performance of the whole circuit.

4. The cascode structure is adopted to enhance the reverse isolation. If the cascode structure is not used, there is no impact on the noise, but the power consumption can continue to be reduced.

5. The present invention compromises various indicators and increases power consumption in order to reduce noise. However, compared with the existing circuit structure, the performance of low noise and high isolation is achieved.

Description of drawings

Fig. 1 is the existing low-noise amplifier that adopts transconductance enhancement;

Fig. 2 is an existing common-gate low-noise amplifier adopting a noise elimination structure;

Fig. 3 is an existing low-power low-noise amplifier that adopts transconductance enhancement and noise elimination;

Fig. 4 is the differential low-power low-noise amplifier adopting active transconductance enhancement and noise cancellation technology in the present invention;

Fig. 5 is the simulated contrast figure of the noise figure (NF) of amplifier with frequency variation and the noise figure of existing common gate amplifier among the present invention;

Fig. 6 is the simulation figure of the voltage gain (S21) of amplifier changing with frequency among the present invention;

Fig. 7 is a simulation diagram of the scattering coefficient (S11) of the amplifier in the present invention as it varies with frequency.

Detailed ways

The present invention will be further illustrated below in conjunction with the accompanying drawings and specific embodiments, and it should be understood that these embodiments are only for illustrating the present invention and are not intended to limit the scope of the present invention. After reading the present invention, modifications to various equivalent forms of the present invention by those skilled in the art fall within the scope defined by the appended claims of the present application.

As shown in Figure 4: the main common-gate amplifier stage 1 uses two identical N-type transistors NM1 and NM5 as input amplifier tubes, the gate terminals of NM1 and NM5 are respectively connected to the bias voltage through a large resistor, and the two ends of the capacitor C1 are respectively Connect to the gate of NM1, the drains of NM2 and PM4, and the source of NM3. The two ends of capacitor C2 are respectively connected to the input positive signal and the gate of PM4. The two ends of capacitor C3 are respectively connected to the input positive signal and the gate of NM2. Active transconductance enhanced amplifier stage 2 uses N-type transistor NM2 and P-type transistor PM4 as input amplifier tubes, the positive signal of the differential signal is directly coupled to the gate terminals of NM2 and PM4 through a capacitor, and the negative signal of the differential signal is directly connected to NM2 The source terminal of PM4 is connected to the power supply. At the same time, an N-type transistor NM3 with a cascode structure is added to NM2. The source terminal of NM3 is connected to the drain terminals of NM2 and PM4, the gate terminal is connected to the bias voltage through a large resistor, and the drain terminal is connected to load resistors Z1 and Z3. The gate terminals of PM4 and NM2 are respectively connected to the bias voltage through a large resistance; the single-ended input terminal ① of the balanced unbalanced transformer 3 is connected to the signal source, and the balanced output terminal ③ is directly coupled to the source level of NM1 and the source level of NM6 and passed through a capacitor Coupled to the gates of NM2 and PM4, the balanced output terminal ④ is directly coupled to the source level of NM2 and the source level of NM5 and coupled to the gate terminals of NM6 and PM8 through capacitive coupling, the second terminal ② and the fifth terminal ⑤ are grounded; load impedance 4 is composed of impedances Z1, Z2, Z3 and Z4, and resistors are used as load impedances in the present invention. The two ends of Z1 are respectively connected to the power supply and the drain of NM3, and the two ends of Z2 are respectively connected to the drain of NM1 and the drain of NM3.

It can be seen from the accompanying drawings 5-7 that the structure of the present invention can achieve good matching within the gain 3dB bandwidth, and the noise figure can be as low as 3dB, and the advantages can be seen from the comparison diagram. And the power consumption is only 3.5mW when the power supply voltage is 1V.

Claims (2)

1. one kind adopts the difference low-power consumption low noise amplifier of active mutual conductance enhancing and noise cancellation technique, it is characterized in that, comprise amplifying stage (2), balance/unbalance transformer (3) and load impedance (4) that main grid amplifying stage (1) altogether, active mutual conductance strengthen; Input signal enters from the input port of balance/unbalance transformer (3), source and the main source direct-coupling of grid amplifying stage (1) altogether of the amplifying stage (2) that its difference output port had both strengthened with active mutual conductance, be also capacitively coupled to the grid end of the amplifying stage (2) that active mutual conductance strengthens; The amplifying stage (2) that active mutual conductance strengthens adopts the symmetrical structure of NMOS and PMOS, and NMOS structure has adopted cascode form; The drain terminal of the amplifying stage (2) that active mutual conductance strengthens is by being capacitively coupled to the main grid of grid amplifying stage (1) altogether; Load impedance (4) joins with the drain electrode of the cascode pipe of the amplifying stage (2) of main grid amplifying stage (1) altogether and active mutual conductance enhancing; The output of circuit is positioned at the main drain electrode of grid amplifying stage (1) altogether.

2. a kind of difference low-power consumption low noise amplifier that adopts active mutual conductance enhancing and noise cancellation technique according to claim 1, it is characterized in that, lead two identical N-type transistor NM1 of common grid amplifying stage (1) and NM5 as input amplifier tube, the grid end of NM1 and NM5 is received bias voltage by large resistance respectively, the two ends of capacitor C 1 connect respectively the grid of NM1, the drain electrode of NM2 and PM4 and the source class of NM3, the two ends of capacitor C 2 connect respectively the grid of input positive signal and PM4, the two ends of capacitor C 3 connect respectively the grid of input positive signal and NM2, the amplifying stage (2) that active mutual conductance strengthens adopts N-type transistor NM2 and P transistor npn npn PM4 as input amplifier tube, the positive signal of differential signal is capacitively coupled to the grid end of NM2 and PM4, the negative signal of differential signal is directly connected to the source of NM2, the source termination power of PM4, on NM2, add the N-type transistor NM3 of cascade (cascode) structure simultaneously, NM3 source connects the drain terminal of NM2 and PM4, grid end connects bias voltage by large resistance, drain terminal meets load resistance Z1 and Z3, the grid end of PM4 and NM2 connects bias voltage by large resistance respectively, the single-ended input (1.) of balance/unbalance transformer (3) is connected to signal source, balance output end (3.) is directly coupled to the source class of NM1 and the source class of NM6 and is capacitively coupled to NM2 and the grid of PM4, another balance output end (4.) is directly coupled to the source class of NM2 and the source class of NM5 and is capacitively coupled to NM6 and the grid end of PM8, the 2nd end (2.) and the 5th end (5.) ground connection, load impedance (4) is made up of impedance Z 1, Z2, Z3 and Z4, and the drain electrode of power supply and NM3 is received respectively at the two ends of Z1, and the two ends of Z2 connect respectively the drain electrode of NM1 and the drain electrode of NM3.