CN103248324A - High-linearity low-noise amplifier - Google Patents
High-linearity low-noise amplifier Download PDFInfo
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Abstract
The invention provides a high-linearity low-noise amplifier of the front end of an ultrahigh-frequency RFID (radio frequency identification) receiver. The amplifier detects two common levels from two differential output ends of a full-differential amplifier through a common-feedback circuit, bias current of the amplifier is adjusted validly and feedback voltage is outputted to a grid of a tail current source, and accordingly, overdrive voltage of the tail current source is increased, input current is increased and linearity is improved. Meanwhile, the problem of non-linear distortion caused by instability of the output common levels is solved. In addition, a coupling capacitor is crossed interstagely to increase power grain, and noise figure is reduced to improve noise performance. The high-linearity low-noise amplifier has the advantages of low noise figure, low power consumption, and high linearity, and solves the problem of carrier leak in ultrahigh-frequency RFID receivers and zero intermediate frequency receivers, and linearity of the low-noise amplifier is improved, so that weak available signals can be amplified linearly and distortionlessly in the process of receiving block signals.
Description
Technical field
The invention belongs to the radio frequency integrated circuit design field, be specifically related to a kind of high linearity low noise amplifier.
Background technology
In recent years, wireless communication technology obtains swift and violent development, is playing the part of more and more important role in social life.The development of radio communication is had higher requirement to the transceiver front ends circuit.
Low noise amplifier LNA(Low Noise Amplifier) as the receiver front end first order, the quality of its performance has directly influenced the performance of whole receiver system, and the total noise factor of system depends on the noiseproof feature of first order low noise amplifier.Except the overall noise of system, no matter be emission or reception data, antenna can continue to launch very big carrier signal, and carrier signal is leaked by circulator or directional coupler and entered receiver front end, energy can reach more than the 0dBm, is far longer than the energy that receives signal.Be same carrier frequency owing to receiving and send signal in most of communication system again, can't be at receiver front end by the carrier signal filtering of radio frequency band filter with leakage, make receiver front end produce and subtract quick and obstruction, had a strong impact on the dynamic range that receives link.
More than the summary, how under the situation that guarantees certain sensitivity, suppressed carrier leaks the influence that receiver is caused, and is the key that improves receiver performance.This has just proposed performance requirement to the receiver radio-frequency (RF) front-end circuit, and LNA no longer only pays close attention to noiseproof feature, needs to pay attention to the linearity more, can linearly amplifying faint useful signal when receiving big block signal.
At present, the carrier leak problem is particularly outstanding in radio-frequency (RF) identification (Radio Frequency Identification) technology in the communication system, and discover, be more suitable for future, what particularly use in the commercial offers chain is hyperfrequency frequency range system, therefore, stimulation frequency of the present invention is set at the hyperfrequency frequency range.
Figure 1 shows that a kind of typical differential low noise amplifier.NM1, NM3 and NM2, NM4 constitute the gain that cascodes provides low noise amplifier, reduced the Miller effect that the capacitance of drain of NM1, NM2 produces simultaneously, and the isolation between having improved input and having exported.
L1, L2, L3, L4 are used for realizing that coupling makes that input impedance is 50 ohm, wherein L1, L2 are as the source class negative feedback resistor, regulate the frequency that L3, L4 are used for controlling whole LNA work, and on NM1, NM2 respectively shunt capacitance C1, C2 can improve the grid source capacitor C gs of two metal-oxide-semiconductors, increased the nargin of control inductance.
Summary of the invention
The present invention is directed to the deficiencies in the prior art, in order to satisfy the radio circuit front end to the requirement of the linearity, propose a kind of high linearity low noise amplifier.Described amplifier has comprised fully-differential amplifier and common mode feedback circuit (Common-Feedback, CMFB) two modules, difference output end by fully-differential amplifier detects common mode electrical level, and by the grid of common mode feedback circuit CMFB negative feedback to tail current source, improve operating current, to increase the linearity; This amplifier circuit has positive and negative two-way input, output, the complete symmetric design of this two-way circuit.
The present invention adopts following technical scheme for solving the problems of the technologies described above:
A kind of high linearity low noise amplifier comprises fully-differential amplifier and common mode feedback circuit; The difference output end output common mode level of described fully-differential amplifier, and by the grid of described common mode feedback circuit negative feedback to tail current source; Described common mode feedback circuit, its positive pole is connected with the positive output end of the differential output signal of described fully-differential amplifier, and negative pole is connected with the negative output terminal of the differential output signal of described fully-differential amplifier.
Described fully-differential amplifier is made of jointly typical fully differential circuit and cross coupling capacitor; Described typical fully differential circuit comprises a NMOS pipe to the five NMOS pipe, the 7th PMOS pipe, the 8th PMOS pipe, first to the 4th inductance, first electric capacity, second electric capacity, the 3rd resistance, the 4th resistance; Described cross coupling capacitor has comprised the 3rd electric capacity, the 4th electric capacity, first resistance, second resistance;
The method of attachment of described typical fully differential circuit is as follows: the drain electrode of NMOS pipe links to each other with the 3rd NMOS pipe source electrode; The drain electrode of the 2nd NMOS pipe links to each other with the 4th NMOS pipe source electrode; The drain electrode of the 3rd NMOS pipe links to each other with the drain electrode of the 7th PMOS pipe; The drain electrode of the 4th NMOS pipe links to each other with the drain electrode of the 8th PMOS pipe; The 3rd NMOS tube grid, the 4th NMOS tube grid, the 7th PMOS pipe source electrode, the 8th PMOS pipe source electrode link to each other with power supply; The 7th gate pmos utmost point, the 8th gate pmos utmost point connect the 3rd bias voltage; Is connected first electric capacity between the one NMOS pipe source electrode and grid, a NMOS manages source electrode and links to each other with first inductance, one end; Be connected second electric capacity between the 2nd NMOS pipe source electrode and grid; The 2nd NMOS pipe source electrode links to each other with second inductance, one end; The first inductance other end, the second inductance other end link to each other with drain electrode as the 5th NMOS pipe of fully differential circuit tail current source; The 5th NMOS manages source ground, and grid connects second bias voltage; The one NMOS tube grid links to each other with the 3rd inductance one end, and another termination input signal of the 3rd inductance also links to each other another termination first bias voltage of the 3rd resistance with the 3rd resistance one end; The 2nd NMOS tube grid links to each other with the 4th inductance one end, and another termination input signal of the 4th inductance also links to each other another termination first bias voltage of the 4th resistance with the 4th resistance one end;
Described typical fully differential circuit is as follows with the method for attachment of cross coupling capacitor: an end of the 3rd electric capacity links to each other with the source electrode of the drain electrode of the 2nd NMOS pipe and the 4th NMOS pipe, and the other end links to each other with the grid of the 3rd NMOS pipe; One end of first resistance links to each other with the grid of the 3rd NMOS pipe, and the other end links to each other with power supply; One end of the 4th electric capacity links to each other with the source electrode of the drain electrode of a NMOS pipe and the 3rd NMOS pipe, and the other end links to each other with the grid of the 4th NMOS pipe; One end of second resistance links to each other with the grid of the 4th NMOS pipe, and the other end links to each other with power supply.
Described the 3rd electric capacity, the 4th electric capacity are the electric capacity that standard CMOS process is supported.
Described common mode feedback circuit comprises a PMOS pipe to the six PMOS pipe and the 6th NMOS pipe; Wherein, the 5th PMOS pipe source electrode, the 6th PMOS pipe source electrode link to each other with power supply; The 5th gate pmos utmost point, the 6th gate pmos utmost point link to each other with the 6th resistance one end, and the 6th resistance other end links to each other with bias voltage; The second gate pmos utmost point, the 3rd gate pmos utmost point link to each other with the 7th resistance one end, and the 7th resistance other end links to each other with reference voltage; The one PMOS pipe source electrode links to each other with the 2nd PMOS pipe source electrode, the drain electrode of the 5th PMOS pipe; The 3rd PMOS pipe source electrode links to each other with the 4th PMOS pipe source electrode, the drain electrode of the 6th PMOS pipe; The drain electrode of the one PMOS pipe links to each other with the drain electrode of the 4th PMOS pipe; The first gate pmos utmost point and the 4th gate pmos utmost point are respectively as the positive and negative input of common mode feedback circuit; Common-mode voltage is compared with reference voltage, and the voltage error of gained is the feedback voltage of common mode feedback circuit just, and this feedback voltage is by the grid output of the 6th NMOS pipe, and the grid of the 6th NMOS pipe links to each other with drain electrode.
The grid of tail current source the 5th NMOS pipe is given in the negative feedback of described common mode feedback circuit output voltage, and connects the 5th resistance between the 5th NMOS tube grid and second bias voltage.
The invention has the beneficial effects as follows: the present invention proposes a kind of high linearity low noise amplifier.Described amplifier detects common mode electrical level by common mode feedback circuit CMFB from two difference output ends of fully-differential amplifier, and the output feedback voltage is to the grid of tail current source, thereby increased the overdrive voltage of tail current source, and then improved operating current and reach the purpose that improves the linearity, solved again simultaneously because the nonlinear distortion that output common mode level instability causes; In addition, cross coupling capacitor is used for increasing gain, and reduces noise factor to improve noiseproof feature, and this structure has low-noise factor, low-power consumption, advantage of high linearity.The present invention improves the linearity of low noise amplifier with solving the carrier leak problem that exists in the current zero intermediate frequency reciver, can be enough when having big block signal, and linearity is amplified faint useful signal without distortion.
Description of drawings
Fig. 1 is a kind of typical differential low noise amplifier structure;
Fig. 2 is a kind of high linearity low noise amplifier architecture provided by the invention;
Fig. 3 is a kind of common mode feedback circuit structure that the present invention adopts;
Fig. 4 is the noise factor schematic diagram of typical differential low noise amplifier;
Fig. 5 is the noise factor schematic diagram of high linearity low noise amplifier of the present invention;
Fig. 6 is input third order intermodulation point (IIP3) schematic diagram of typical differential low noise amplifier;
Fig. 7 is input third order intermodulation point (IIP3) schematic diagram of high linearity low noise amplifier of the present invention.
Embodiment
Below in conjunction with accompanying drawing, further specify a kind of high linearity low noise amplifier of the present invention.
With reference to Fig. 2, a kind of high linearity low noise amplifier provided by the present invention is constituted by differential amplifier and negative-feedback circuit, and differential amplifier adopts typical fully differential circuit and cross coupling capacitor structure.This amplifier circuit has positive and negative two-way input, output, the complete symmetric design of this two-way circuit.RF
OpPositive output end for differential amplifier; RF
OnNegative output terminal for differential amplifier.
Described typical fully differential circuit comprises a NMOS pipe to the five NMOS pipe, the 7th PMOS pipe PM7, the 8th PMOS pipe PM8, first to the 4th inductance, first capacitor C 1, second capacitor C 2, the 3rd resistance R 3, the 4th resistance R 4; Described cross coupling capacitor has comprised the 3rd capacitor C 3, the 4th capacitor C 4, first resistance R 1, second resistance R 2;
The method of attachment of described typical fully differential circuit is as follows: NMOS pipe NM1 drain electrode links to each other with the 3rd NMOS pipe NM3 source electrode; The 2nd NMOS pipe NM2 drain electrode links to each other with the 4th NMOS pipe NM4 source electrode; The 3rd NMOS pipe NM3 drain electrode links to each other with the 7th PMOS pipe PM7 drain electrode; The 4th NMOS pipe NM4 drain electrode links to each other with the 8th PMOS pipe PM8 drain electrode; The 3rd NMOS pipe NM3 grid, the 4th NMOS pipe NM4 grid, the 7th PMOS pipe PM7 source electrode, the 8th PMOS pipe PM8 source electrode link to each other with power supply Vdd; The 7th PMOS pipe PM7 grid, the 8th PMOS pipe PM8 grid meet the 3rd bias voltage Vbias3; Being connected first capacitor C, 1, the one NMOS between the one NMOS pipe NM1 source electrode and grid manages the NM1 source electrode and links to each other with first inductance L, 1 one ends; Be connected second capacitor C 2 between the 2nd NMOS pipe NM2 source electrode and grid; The 2nd NMOS pipe NM2 source electrode links to each other with second inductance L, 2 one ends; First inductance L, 1 other end, second inductance L, 2 other ends link to each other with drain electrode as the 5th NMOS pipe NM5 of fully differential circuit tail current source; The 5th NMOS pipe NM5 source ground, grid meets the second bias voltage Vbias2; The one NMOS pipe NM1 grid links to each other with the 3rd inductance L 3 one ends, and the 3rd inductance L 3 another termination input signals also link to each other the 3rd resistance R 3 another terminations first bias voltage Vbias1 with the 3rd resistance R 3 one ends; The 2nd NMOS pipe NM2 grid links to each other with the 4th inductance L 4 one ends, and the 4th inductance L 4 another termination input signals also link to each other the 4th resistance R 4 another terminations first bias voltage Vbias1 with the 4th resistance R 4 one ends;
Described typical fully differential circuit is as follows with the method for attachment of cross coupling capacitor: an end of the 3rd capacitor C 3 links to each other with the drain electrode of the 2nd NMOS pipe NM2 and the source electrode of the 4th NMOS pipe NM4, and the other end links to each other with the grid of the 3rd NMOS pipe NM3; One end of first resistance R 1 links to each other with the grid of the 3rd NMOS pipe NM3, and the other end links to each other with power supply Vdd; One end of the 4th capacitor C 4 links to each other with the drain electrode of NMOS pipe NM1 and the source electrode of the 3rd NMOS pipe NM3, and the other end links to each other with the grid of the 4th NMOS pipe NM4; One end of second resistance R 2 links to each other with the grid of the 4th NMOS pipe NM4, and the other end links to each other with power supply Vdd.
With reference to Fig. 3, described common mode feedback circuit comprises a PMOS pipe to the six PMOS pipe and the 6th NMOS pipe, by four PMOS pipe common-mode voltages that detect the differential amplifier output parallel with one another; Wherein, the 5th PMOS pipe PM5 source electrode, the 6th PMOS pipe PM6 source electrode link to each other with power supply Vdd; The 5th PMOS pipe PM5 grid, the 6th PMOS pipe PM6 grid link to each other with the 6th resistance R 6 one ends, and the 6th resistance R 6 other ends link to each other with bias voltage Vbias; The 2nd PMOS pipe PM2 grid, the 3rd PMOS pipe PM3 grid link to each other with the 7th resistance R 7 one ends, and the 7th resistance R 7 other ends link to each other with reference voltage Vref; The one PMOS pipe PM1 source electrode links to each other with the 2nd PMOS pipe PM2 source electrode, the 5th PMOS pipe PM5 drain electrode; The 3rd PMOS pipe PM3 source electrode links to each other with the 4th PMOS pipe PM4 source electrode, the 6th PMOS pipe PM6 drain electrode; The one PMOS pipe PM1 drain electrode links to each other with the 4th PMOS pipe PM4 drain electrode; The one PMOS pipe PM1 grid and the 4th PMOS manage the PM4 grid respectively as the positive and negative input of common mode feedback circuit; Common-mode voltage is compared with reference voltage Vref, and the voltage error of gained is the feedback voltage of common mode feedback circuit just, and this feedback voltage is by the grid output of the 6th NMOS pipe NM6, and the grid of the 6th NMOS pipe NM6 links to each other with drain electrode.
Common mode feedback circuit, its positive pole are connected on the positive output end RF of signal
Op, just between the 3rd NMOS pipe NM3 and the 7th PMOS pipe PM7, its negative pole is connected on the negative output terminal RF of signal
On, just between the 4th NMOS pipe NM4 and the 8th PMOS pipe PM8; Its output is connected on the grid of the tail current source of difference channel, just the grid of the 5th NMOS pipe NM5;
With reference to Fig. 3, detect the output common mode electrical level by common mode feedback circuit CMFB, and relatively draw output feedback voltage V cmfb with circuit internal reference voltage Vref, be added in the grid of tail current source NM5, like this gate source voltage V of NM5
GSImproved, by formula:
I in the formula
SSBe the current value that tail current source provides, V
THBe the threshold voltage of tail current source NMOS, μ
nC
OxBe process constant, W/L is the breadth length ratio of metal-oxide-semiconductor.
As can be known: as gate source voltage V
GSImprove I
SSAlso along with raising, increased operating current, thereby improved the input linearity, the index of the linearity is input third order intermodulation point (IIP3), and IIP3 is determined jointly by the input linearity and the output linearity, and for the input linearity, common mode feedback circuit of the present invention can improve, and for output, often by guaranteeing that output signal does not enter the voltage restricted area and realizes.
Yet bigger input current often makes the output dc point on the low side, thereby forms the output voltage restriction, so we often adopt the PMOS pipe as load, the present invention adopts the 7th PMOS pipe PM7 and the 8th PMOS pipe PM8 as load, and pipe sizing is large scale.Use the PMOS pipe to exist the distinctive problem of difference channel as load: output common mode level instability.The present invention has introduced common mode feedback circuit, having increased input current improves the input linearity on the one hand, on the other hand in high-gain amplifier, the output common mode level is quite responsive to Devices Characteristics and mismatch, this common mode feedback circuit can detect the common mode electrical level of two outputs, and the deviation electric current of with good grounds ground resonance-amplifier.
In the cross coupling capacitor structure, signal after the 3rd capacitor C 3 and the 4th capacitor C 4 are amplified amplifier tube the one NMOS pipe NM1 and the 2nd NMOS pipe NM2 is coupled to the grid that the 3rd NMOS pipe NM3 and the 4th NMOS manage NM4 respectively and amplifies again, has increased Amplifier Gain.Simultaneously, this coupling capacitance has reduced the gate leakage capacitance C of amplifier tube the one NMOS pipe NM1 and the 2nd NMOS pipe NM2
GDInfluence to noiseproof feature.
Figure 4 shows that noise factor NF (NoiseFigure) schematic diagram of typical differential low noise amplifier.As can be seen, the noise factor of low noise amplifier is 2.86dB when frequency is 900MHZ; Figure 5 shows that the noise factor NF schematic diagram of high linearity low noise amplifier of the present invention.As can be seen, the noise factor of low noise amplifier is 2.62dB when frequency is 900MHZ.By comparison diagram 4 and Fig. 5 as can be known, high linearity low noise noise figure of amplifier of the present invention has illustrated that than the noise factor of typical differential low noise amplifier low 0.3dB nearly when frequency is 900MHz noiseproof feature of the present invention is better.
Figure 6 shows that input third order intermodulation point IIP3 (the Input 3rd order intercept point) schematic diagram of typical differential low noise amplifier.As can be seen, when frequency was 900MHz, the input third order intermodulation point IIP3 of low noise amplifier was-9.0dBm; Figure 7 shows that the input third order intermodulation point IIP3 schematic diagram of high linearity low noise amplifier of the present invention.As can be seen, when frequency was 900MHZ, the input third order intermodulation point IIP3 of low noise amplifier was-5.4dBm.By comparison diagram 6 and Fig. 7 as can be known, the input third order intermodulation point IIP3 of high linearity low noise amplifier of the present invention when working frequency points is 900MHz than about the high 3.6dB of typical differential low noise amplifier.Illustrated that the linearity of the present invention is relatively good.
In sum, the high linearity low noise amplifier that the present invention proposes has linearity height, advantage that noise factor is little, has broad application prospects in ultrahigh frequency RFID receiver front end circuit.
For those skilled in the art, can be easy to other advantage and distortion of association according to above implementation of class.Therefore, the present invention is not limited to above-mentioned instantiation, and it carries out detailed, exemplary explanation as just example to a kind of form of the present invention.In the scope that does not deviate from aim of the present invention, those of ordinary skills replace resulting technical scheme according to above-mentioned instantiation by various being equal to, and all should be included within claim scope of the present invention and the equivalency range thereof.
Claims (5)
1. a high linearity low noise amplifier is characterized in that, comprises fully-differential amplifier and common mode feedback circuit; The difference output end output common mode level of described fully-differential amplifier, and by the grid of described common mode feedback circuit negative feedback to the fully-differential amplifier tail current source; Described common mode feedback circuit, its positive pole is connected with the positive output end of the differential output signal of described fully-differential amplifier, and negative pole is connected with the negative output terminal of the differential output signal of described fully-differential amplifier.
2. a kind of high linearity low noise amplifier as claimed in claim 1 is characterized in that, described fully-differential amplifier is made of jointly typical fully differential circuit and cross coupling capacitor; Described typical fully differential circuit comprises first to the 5th NMOS pipe, the 7th PMOS pipe, the 8th PMOS pipe, first to the 4th inductance, first electric capacity, second electric capacity, the 3rd resistance, the 4th resistance; Described cross coupling capacitor has comprised the 3rd electric capacity, the 4th electric capacity, first resistance, second resistance;
The connection of described typical fully differential circuit is as follows: NMOS pipe (NM1) drain electrode links to each other with the 3rd NMOS pipe (NM3) source electrode; The 2nd NMOS pipe (NM2) drain electrode links to each other with the 4th NMOS pipe (NM4) source electrode; The 3rd NMOS pipe (NM3) drain electrode links to each other with the 7th PMOS pipe (PM7) drain electrode; The 4th NMOS pipe (NM4) drain electrode links to each other with the 8th PMOS pipe (PM8) drain electrode; The 3rd NMOS pipe (NM3) grid, the 4th NMOS pipe (NM4) grid, the 7th PMOS pipe (PM7) source electrode, the 8th PMOS pipe (PM8) source electrode link to each other with power supply (Vdd) respectively; The 7th PMOS pipe (PM7) grid, the 8th PMOS pipe (PM8) grid connect the 3rd bias voltage (Vbias3) respectively; Is connected first electric capacity (C1) between the one NMOS pipe (NM1) source electrode and grid, a NMOS manages (NM1) source electrode and links to each other with first inductance (L1) end; Be connected second electric capacity (C2) between the 2nd NMOS pipe (NM2) source electrode and grid; The 2nd NMOS pipe (NM2) source electrode links to each other with second inductance (L2) end; First inductance (L1) other end, second inductance (L2) other end link to each other with drain electrode as the 5th NMOS of fully differential circuit tail current source pipe (NM5) respectively; The 5th NMOS manages (NM5) source ground, and the 5th NMOS pipe (NM5) grid connects second bias voltage (Vbias2); The one NMOS pipe (NM1) grid links to each other with the 3rd inductance (L3) end, and another termination input signal of the 3rd inductance (L3) also links to each other another termination first bias voltage (Vbias1) of the 3rd resistance (R3) with the 3rd resistance (R3) end; The 2nd NMOS pipe (NM2) grid links to each other with the 4th inductance (L4) end, and another termination input signal of the 4th inductance (L4) also links to each other another termination first bias voltage (Vbias1) of the 4th resistance (R4) with the 4th resistance (R4) end;
Described typical fully differential circuit is as follows with the method for attachment of cross coupling capacitor: the 3rd electric capacity (C3) end links to each other with the 2nd NMOS pipe (NM2) drain electrode and the 4th NMOS pipe (NM4) source electrode respectively, and the 3rd electric capacity (C3) other end links to each other with the grid that the 3rd NMOS manages (NM3); One end of first resistance (R1) links to each other with the grid that the 3rd NMOS manages (NM3), and first resistance (R1) other end links to each other with power supply (Vdd); One end of the 4th electric capacity (C4) links to each other with the drain electrode of NMOS pipe (NM1) and the source electrode of the 3rd NMOS pipe (NM3) respectively, and the 4th electric capacity (C4) other end links to each other with the grid that the 4th NMOS manages (NM4); One end of second resistance (R2) links to each other with the grid that the 4th NMOS manages (NM4), and second resistance (R2) other end links to each other with power supply (Vdd).
3. a kind of high linearity low noise amplifier as claimed in claim 1 is characterized in that, described the 3rd electric capacity (C3), the 4th electric capacity (C4) are the electric capacity that standard CMOS process is supported.
4. a kind of high linearity low noise amplifier as claimed in claim 1 is characterized in that, described common mode feedback circuit comprises first to the 6th PMOS pipe and the 6th NMOS pipe; Wherein, the 5th PMOS pipe (PM5) source electrode, the 6th PMOS pipe (PM6) source electrode link to each other with power supply (Vdd) respectively; The 5th PMOS pipe (PM5) grid, the 6th PMOS pipe (PM6) grid link to each other with the 6th resistance (R6) end respectively, and the 6th resistance (R6) other end links to each other with bias voltage (Vbias); The 2nd PMOS pipe (PM2) grid, the 3rd PMOS pipe (PM3) grid link to each other with the 7th resistance (R7) end respectively, and the 7th resistance (R7) other end links to each other with reference voltage (Vref); The one PMOS pipe (PM1) source electrode links to each other with the 2nd PMOS pipe (PM2) source electrode, the 5th PMOS pipe (PM5) drain electrode respectively; The 3rd PMOS pipe (PM3) source electrode links to each other with the 4th PMOS pipe (PM4) source electrode, the 6th PMOS pipe (PM6) drain electrode respectively; The one PMOS pipe (PM1) drain electrode links to each other with the 4th PMOS pipe (PM4) drain electrode; The one PMOS pipe (PM1) grid and the 4th PMOS manage (PM4) grid respectively as the positive and negative input of common mode feedback circuit; Common-mode voltage is compared with reference voltage (Vref), and the voltage error of gained is the feedback voltage of common mode feedback circuit just, and this feedback voltage is by the output of the 6th NMOS pipe (NM6) grid, and the grid of the 6th NMOS pipe (NM6) links to each other with drain electrode.
5. as claim 1 or 2 or 3 or 4 described a kind of high linearity low noise amplifiers, it is characterized in that, the grid of fully-differential amplifier tail current source the 5th NMOS pipe (NM5) is given in the negative feedback of described common mode feedback circuit output voltage, and connects the 5th resistance (R5) between the 5th NMOS pipe (NM5) grid and second bias voltage (Vbias2).
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| US9166530B2 (en) | 2014-03-16 | 2015-10-20 | Advanced Semiconductor Engineering Inc. | Low noise amplifier and receiver |
| CN105577133A (en) * | 2014-08-29 | 2016-05-11 | 三星电子株式会社 | Low noise amplifier and method for carrier aggregation and non-carrier aggregation |
| CN105959008A (en) * | 2015-03-09 | 2016-09-21 | 爱思开海力士有限公司 | Preamplifier, and comparator and analog-to-digital converting apparatus including the same |
| CN106160782A (en) * | 2016-08-23 | 2016-11-23 | 池州睿成微电子有限公司 | A kind of MUX eliminating system for carrier leak |
| CN106230389A (en) * | 2016-09-27 | 2016-12-14 | 无锡中科微电子工业技术研究院有限责任公司 | high-gain low-noise amplifier |
| CN106385239A (en) * | 2016-09-09 | 2017-02-08 | 中国计量大学 | Gain-adjustable CMOS (Complementary Metal-Oxide-Semiconductor Transistor) broadband low-noise amplifier |
| CN107765751A (en) * | 2017-11-29 | 2018-03-06 | 成都锐成芯微科技股份有限公司 | Common mode feedback circuit and signal processing circuit |
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| CN109120243A (en) * | 2018-07-23 | 2019-01-01 | 中国电子科技集团公司第二十四研究所 | Clock driver circuit |
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| CN110708021A (en) * | 2019-09-30 | 2020-01-17 | 西安电子科技大学 | High-linearity differential double-feedback low-noise amplifier |
| CN110829984A (en) * | 2018-08-14 | 2020-02-21 | 武汉芯泰科技有限公司 | High-linearity power amplifier |
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