CN103248324A - High-linearity low-noise amplifier - Google Patents

Abstract

The invention provides a high-linearity low-noise amplifier at the front end of an ultra-high frequency RFID receiver. The amplifier detects two common-mode levels from the two differential output terminals of the fully differential amplifier through the common-mode feedback circuit, and adjusts the bias current output feedback voltage of the amplifier to the gate of the tail current source accordingly, thereby increasing the The overdrive voltage of the tail current source, thereby increasing the input current to achieve the purpose of improving linearity, and at the same time solving the nonlinear distortion caused by the instability of the output common-mode level; in addition, the inter-stage cross-coupling capacitor, It is used to increase power gain and reduce noise figure to improve noise performance. This structure has the advantages of low noise figure, low power consumption and high linearity. The invention is used to solve the carrier leakage problem existing in the zero-IF receiver of the current UHF RFID receiver, improve the linearity of the low-noise amplifier, and enable it to receive a large blocking signal without distortion Linearly amplifies weak useful signals.

Description

A High Linearity Low Noise Amplifier

technical field

The invention belongs to the field of radio frequency integrated circuit design, in particular to a high-linearity low-noise amplifier.

Background technique

In recent years, wireless communication technology has developed rapidly and plays an increasingly important role in social life. The development of wireless communication puts forward higher requirements on the front-end circuit of the transceiver.

Low Noise Amplifier LNA (Low Noise Amplifier) is the first stage of the receiver front end, its performance directly affects the performance of the entire receiver system, and the overall noise figure of the system depends on the noise performance of the first stage LNA. In addition to the overall noise of the system, whether it is transmitting or receiving data, the antenna will continue to transmit a large carrier signal. The carrier signal leaks into the front end of the receiver through a circulator or a directional coupler, and the energy can reach more than 0dBm, which is far greater than the received signal. energy of. And because most of the communication systems receive and transmit signals at the same carrier frequency, it is impossible to filter out the leaked carrier signal through a radio frequency band-pass filter at the front end of the receiver, resulting in desensitization and blocking at the front end of the receiver, which seriously affects the receiving link. dynamic range.

To sum up the above, how to suppress the impact of carrier leakage on the receiver while ensuring a certain sensitivity is the key to improving the performance of the receiver. This puts forward performance requirements for the receiver's RF front-end circuit. LNA no longer only focuses on noise performance, but more on linearity, so that it can linearly amplify weak useful signals while receiving large blocking signals.

At present, the problem of carrier leakage in communication systems is particularly prominent in radio frequency identification (RFID) technology, and research has found that it is more suitable for the future, especially in the commercial supply chain, the ultra-high frequency band system is used. Therefore, the simulation frequency of the present invention Set to UHF band.

Figure 1 shows a typical differential low noise amplifier. NM1, NM3, NM2, and NM4 form a cascode structure to provide the gain of the low noise amplifier, reduce the Miller effect produced by the drain capacitance of NM1, NM2, and improve the isolation between input and output.

L1, L2, L3, and L4 are used to achieve matching so that the input impedance is 50 ohms, among which L1, L2 are used as source-level negative feedback resistors, adjusting L3, L4 is used to control the working frequency of the entire low-noise amplifier, while NM1, NM2 Connecting capacitors C1 and C2 in parallel can increase the gate-source capacitance Cgs of the two MOS transistors and increase the margin for controlling the inductance.

Contents of the invention

Aiming at the deficiencies of the prior art, the invention proposes a high-linearity low-noise amplifier in order to meet the linearity requirement of the radio frequency circuit front end. The amplifier includes two modules: a fully differential amplifier and a common-feedback circuit (Common-Feedback, CMFB). The common-mode level is detected through the differential output of the fully differential amplifier, and the common-mode feedback circuit CMFB negatively feeds back the tail current The gate of the source increases the operating current to increase the linearity; the amplifier circuit has positive and negative two-way input and output, and the two-way circuit is completely symmetrical in design.

In order to solve the problems of the technologies described above, the present invention adopts the following technical solutions:

A high-linearity low-noise amplifier comprising a fully differential amplifier and a common-mode feedback circuit; the differential output of the fully differential amplifier outputs a common-mode level, and is negatively fed back to the gate of the tail current source by the common-mode feedback circuit pole; the positive pole of the common mode feedback circuit is connected to the positive output terminal of the differential output signal of the fully differential amplifier, and the negative pole is connected to the negative output terminal of the differential output signal of the fully differential amplifier.

The fully differential amplifier is composed of a typical fully differential circuit and a cross-coupling capacitor; the typical fully differential circuit includes a first NMOS transistor to a fifth NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, and a first to a fifth NMOS transistor. Four inductors, a first capacitor, a second capacitor, a third resistor, and a fourth resistor; the cross-coupling capacitor includes a third capacitor, a fourth capacitor, a first resistor, and a second resistor;

The connection method of the typical fully differential circuit is as follows: the drain of the first NMOS transistor is connected to the source of the third NMOS transistor; the drain of the second NMOS transistor is connected to the source of the fourth NMOS transistor; the drain of the third NMOS transistor is connected to the source of the fourth NMOS transistor. The drains of the seven PMOS transistors are connected; the drains of the fourth NMOS transistors are connected to the drains of the eighth PMOS transistors; the gates of the third NMOS transistors, the gates of the fourth NMOS transistors, the source electrodes of the seventh PMOS transistors, and the source electrodes of the eighth PMOS transistors Connected to the power supply; the gate of the seventh PMOS transistor and the gate of the eighth PMOS transistor are connected to the third bias voltage; the source and gate of the first NMOS transistor are connected to the first capacitor, and the source of the first NMOS transistor is connected to one end of the first inductor ; The second capacitor is connected between the source of the second NMOS tube and the grid; the source of the second NMOS tube is connected to one end of the second inductor; The drains of the five NMOS transistors are connected; the source of the fifth NMOS transistor is grounded, and the gate is connected to the second bias voltage; the gate of the first NMOS transistor is connected to one end of the third inductor, and the other end of the third inductor is connected to the input signal and connected to the third One end of the resistor is connected, the other end of the third resistor is connected to the first bias voltage; the gate of the second NMOS transistor is connected to one end of the fourth inductor, the other end of the fourth inductor is connected to the input signal and connected to one end of the fourth resistor, and the other end of the fourth resistor connected to the first bias voltage;

The connection method between the typical fully differential circuit and the cross-coupling capacitor is as follows: one end of the third capacitor is connected to the drain of the second NMOS transistor and the source of the fourth NMOS transistor, and the other end is connected to the gate of the third NMOS transistor ; One end of the first resistor is connected to the gate of the third NMOS transistor, and the other end is connected to the power supply; one end of the fourth capacitor is connected to the drain of the first NMOS transistor and the source of the third NMOS transistor, and the other end is connected to the fourth NMOS transistor. The gate of the NMOS transistor is connected; one end of the second resistor is connected to the gate of the fourth NMOS transistor, and the other end is connected to the power supply.

Both the third capacitor and the fourth capacitor are capacitors supported by a standard CMOS process.

The common mode feedback circuit includes the first PMOS transistor to the sixth PMOS transistor and the sixth NMOS transistor; wherein, the source of the fifth PMOS transistor and the source of the sixth PMOS transistor are connected to the power supply; the gate of the fifth PMOS transistor, the sixth NMOS transistor The gate of the PMOS transistor is connected to one end of the sixth resistor, and the other end of the sixth resistor is connected to the bias voltage; the grid of the second PMOS transistor and the gate of the third PMOS transistor are connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to the reference voltage connected; the source of the first PMOS transistor is connected to the source of the second PMOS transistor and the drain of the fifth PMOS transistor; the source of the third PMOS transistor is connected to the source of the fourth PMOS transistor and the drain of the sixth PMOS transistor; the first PMOS transistor The drain is connected to the drain of the fourth PMOS transistor; the gate of the first PMOS transistor and the gate of the fourth PMOS transistor are respectively used as the positive and negative input ends of the common-mode feedback circuit; the common-mode voltage is compared with the reference voltage, and the obtained voltage error That is, the feedback voltage of the common mode feedback circuit, the feedback voltage is output through the gate of the sixth NMOS transistor, and the gate of the sixth NMOS transistor is connected to the drain.

The output voltage of the common mode feedback circuit is negatively fed back to the gate of the fifth NMOS transistor of the tail current source, and a fifth resistor is connected between the gate of the fifth NMOS transistor and the second bias voltage.

The beneficial effects of the invention are: the invention provides a high-linearity low-noise amplifier. The amplifier detects the common-mode level from the two differential output terminals of the fully differential amplifier through the common-mode feedback circuit CMFB, and outputs the feedback voltage to the gate of the tail current source, thereby increasing the overdrive voltage of the tail current source, In turn, the working current is increased to achieve the purpose of improving linearity, and at the same time, it solves the nonlinear distortion caused by the instability of the output common-mode level; in addition, the cross-coupling capacitor is used to increase the gain and reduce the noise figure to improve Noise performance, the structure has the advantages of low noise figure, low power consumption, and high linearity. The invention is used to solve the carrier leakage problem existing in the current zero-IF receiver, improve the linearity of the low-noise amplifier, and enable it to linearly amplify weak useful signals without distortion while there are large blocking signals.

Description of drawings

Figure 1 is a typical differential low noise amplifier structure;

Fig. 2 is a kind of high linearity low noise amplifier structure provided by the present invention;

Fig. 3 is a kind of common mode feedback circuit structure that the present invention adopts;

Fig. 4 is a schematic diagram of the noise figure of a typical differential low noise amplifier;

Fig. 5 is a schematic diagram of the noise figure of the high linearity low noise amplifier of the present invention;

Fig. 6 is a schematic diagram of the input third-order intercept point (IIP3) of a typical differential low noise amplifier;

FIG. 7 is a schematic diagram of the input third-order intercept point (IIP3) of the high linearity low noise amplifier of the present invention.

Detailed ways

A high-linearity low-noise amplifier of the present invention will be further described below in conjunction with the accompanying drawings.

Referring to FIG. 2 , a high-linearity low-noise amplifier provided by the present invention is composed of a differential amplifier and a negative feedback circuit, and the differential amplifier adopts a typical fully differential circuit and cross-coupling capacitor structure. The amplifier circuit has positive and negative two-way input and output, and the two-way circuits are completely symmetrical in design. RF _op is the positive output terminal of the differential amplifier; RF _on is the negative output terminal of the differential amplifier.

The typical fully differential circuit includes the first NMOS transistor to the fifth NMOS transistor, the seventh PMOS transistor PM7, the eighth PMOS transistor PM8, the first to the fourth inductors, the first capacitor C1, the second capacitor C2, and the third resistor R3, a fourth resistor R4; the cross-coupling capacitor includes a third capacitor C3, a fourth capacitor C4, a first resistor R1, and a second resistor R2;

The connection method of the typical fully differential circuit is as follows: the drain of the first NMOS transistor NM1 is connected to the source of the third NMOS transistor NM3; the drain of the second NMOS transistor NM2 is connected to the source of the fourth NMOS transistor NM4; The drain of NM3 is connected to the drain of the seventh PMOS transistor PM7; the drain of the fourth NMOS transistor NM4 is connected to the drain of the eighth PMOS transistor PM8; the gate of the third NMOS transistor NM3, the gate of the fourth NMOS transistor NM4, and the seventh PMOS transistor The source of PM7 and the source of the eighth PMOS transistor PM8 are connected to the power supply Vdd; the gate of the seventh PMOS transistor PM7 and the gate of the eighth PMOS transistor PM8 are connected to the third bias voltage Vbias3; between the source and the gate of the first NMOS transistor NM1 Connect the first capacitor C1, the source of the first NMOS transistor NM1 is connected to one end of the first inductor L1; the source and gate of the second NMOS transistor NM2 are connected to the second capacitor C2; the source of the second NMOS transistor NM2 is connected to the second inductor L2 One end is connected; the other end of the first inductance L1 and the other end of the second inductance L2 are connected to the drain of the fifth NMOS transistor NM5 as the tail current source of the fully differential circuit; the source of the fifth NMOS transistor NM5 is grounded, and the gate is connected to the second bias Set the voltage Vbias2; the gate of the first NMOS transistor NM1 is connected to one end of the third inductor L3, the other end of the third inductor L3 is connected to the input signal and connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the first bias voltage Vbias1 ; The gate of the second NMOS transistor NM2 is connected to one end of the fourth inductor L4, the other end of the fourth inductor L4 is connected to the input signal and connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the first bias voltage Vbias1;

The connection method between the typical fully differential circuit and the cross-coupling capacitor is as follows: one end of the third capacitor C3 is connected to the drain of the second NMOS transistor NM2 and the source of the fourth NMOS transistor NM4, and the other end is connected to the third NMOS transistor NM3 One end of the first resistor R1 is connected to the gate of the third NMOS transistor NM3, and the other end is connected to the power supply Vdd; one end of the fourth capacitor C4 is connected to the drain of the first NMOS transistor NM1 and the third NMOS transistor NM3 One end of the second resistor R2 is connected to the gate of the fourth NMOS transistor NM4, and the other end is connected to the power supply Vdd.

Referring to Fig. 3, the common-mode feedback circuit includes the first PMOS transistor to the sixth PMOS transistor and the sixth NMOS transistor, and four PMOS transistors are connected in parallel to detect the common-mode voltage at the output terminal of the differential amplifier; wherein, the fifth PMOS transistor PM5 The source and the source of the sixth PMOS transistor PM6 are connected to the power supply Vdd; the gate of the fifth PMOS transistor PM5 and the gate of the sixth PMOS transistor PM6 are connected to one end of the sixth resistor R6, and the other end of the sixth resistor R6 is connected to the bias voltage Vbias The grid of the second PMOS transistor PM2 and the grid of the third PMOS transistor PM3 are connected to one end of the seventh resistor R7, and the other end of the seventh resistor R7 is connected to the reference voltage Vref; the source of the first PMOS transistor PM1 is connected to the source of the second PMOS transistor PM2 pole and the drain of the fifth PMOS transistor PM5; the source of the third PMOS transistor PM3 is connected to the source of the fourth PMOS transistor PM4 and the drain of the sixth PMOS transistor PM6; the drain of the first PMOS transistor PM1 is connected to the drain of the fourth PMOS transistor PM4 The poles are connected; the gate of the first PMOS transistor PM1 and the gate of the fourth PMOS transistor PM4 are respectively used as the positive and negative input terminals of the common-mode feedback circuit; the common-mode voltage is compared with the reference voltage Vref, and the obtained voltage error is the common-mode feedback The feedback voltage of the circuit, the feedback voltage is output through the gate of the sixth NMOS transistor NM6, and the gate of the sixth NMOS transistor NM6 is connected to the drain.

In the common mode feedback circuit, its anode is connected to the positive output terminal RF _op of the signal, which is between the third NMOS transistor NM3 and the seventh PMOS transistor PM7, and its cathode is connected to the negative output terminal RF _on of the signal, which is the fourth NMOS transistor Between the tube NM4 and the eighth PMOS tube PM8; its output terminal is connected to the grid of the tail current source of the differential circuit, that is, the grid of the fifth NMOS tube NM5;

Referring to Figure 3, the common-mode level of the output terminal is detected by the common-mode feedback circuit CMFB, and compared with the internal reference voltage Vref of the circuit, the output feedback voltage Vcmfb is obtained, which is added to the gate of the tail current source NM5, so that the gate-source voltage of NM5 V _GS is raised by the formula:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; SS</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ox</span>}}\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; GS</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}$

In the formula, I _SS is the current value provided by the tail current source, V _TH is the threshold voltage of the tail current source NMOS, μ _n C _ox is the process constant, and W/L is the width-to-length ratio of the MOS tube.

It can be seen that when the gate-source voltage V _GS increases, I _SS also increases, increasing the operating current, thereby improving the input linearity. The index of linearity is the input third-order intercept point (IIP3), and IIP3 is determined by the input linearity It is determined jointly with the output linearity. For the input linearity, the common-mode feedback circuit of the present invention can improve, and for the output, it is often realized by ensuring that the output signal does not enter the voltage-limited area.

However, a large input current often makes the output DC point low, thereby forming an output voltage limit, so we often use PMOS tubes as loads. The present invention uses the seventh PMOS tube PM7 and the eighth PMOS tube PM8 as loads, and the size of the tubes is large size. Using PMOS transistors as loads has a unique problem with differential circuits: the output common-mode level is unstable. The present invention introduces a common-mode feedback circuit. On the one hand, it increases the input current to improve the input linearity. On the other hand, in a high-gain amplifier, the output common-mode level is quite sensitive to the characteristics and mismatch of the device. The common-mode feedback The circuit can detect the common-mode level of the two output terminals, and adjust the bias current of the amplifier accordingly.

In the cross-coupling capacitor structure, the third capacitor C3 and the fourth capacitor C4 respectively couple the amplified signals of the first NMOS transistor NM1 and the second NMOS transistor NM2 to the gates of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 Amplify again, increasing the gain of the amplifier. At the same time, the coupling capacitance reduces the influence of the gate-drain capacitance C _GD of the first NMOS transistor NM1 and the second NMOS transistor NM2 of the amplifier transistors on the noise performance.

Figure 4 shows a schematic diagram of the noise figure NF (NoiseFigure) of a typical differential low noise amplifier. It can be seen that the noise figure of the low noise amplifier is 2.86dB when the frequency is 900MHZ; FIG. 5 is a schematic diagram of the noise figure NF of the high linearity low noise amplifier of the present invention. It can be seen that the noise figure of the low noise amplifier is 2.62dB when the frequency is 900MHZ. By comparing Fig. 4 and Fig. 5, it can be seen that the noise figure of the high linearity low noise amplifier of the present invention is lower than the noise figure of the typical differential low noise amplifier when the frequency is 900MHz, which is nearly 0.3dB lower, which shows that the noise performance of the present invention is better than that of the typical differential low noise amplifier. good.

Figure 6 shows a schematic diagram of the input third-order intercept point IIP3 (Input 3rdorder intercept point) of a typical differential low-noise amplifier. It can be seen that when the frequency is 900MHz, the input third-order interim point IIP3 of the low-noise amplifier is -9.0dBm; FIG. 7 is a schematic diagram of the input third-order interim point IIP3 of the high-linearity low-noise amplifier of the present invention. It can be seen that when the frequency is 900MHZ, the input third-order intercept point IIP3 of the low noise amplifier is -5.4dBm. By comparing Fig. 6 and Fig. 7, it can be known that the input third-order intermodulation point IIP3 of the high-linearity low-noise amplifier of the present invention is about 3.6dB higher than that of a typical differential low-noise amplifier when the operating frequency is 900MHz. It shows that the linearity of the present invention is relatively good.

In summary, the high-linearity low-noise amplifier proposed by the present invention has the advantages of high linearity and small noise figure, and has broad application prospects in front-end circuits of UHF RFID receivers.

For those skilled in the art, other advantages and variants can be easily ascertained based on the above implementations. Therefore, the present invention is not limited to the above-mentioned specific examples, which are merely used as examples to describe in detail and exemplary one form of the present invention. Within the scope of not departing from the gist of the present invention, technical solutions obtained by those skilled in the art through various equivalent replacements based on the above specific examples shall be included in the scope of the claims of the present invention and their equivalent scope.

Claims (5)

1. A high-linearity low-noise amplifier, characterized in that, comprises a full differential amplifier and a common-mode feedback circuit; the differential output terminal output common-mode level of the full differential amplifier, and is negatively fed back by the common-mode feedback circuit Give the gate of the fully differential amplifier tail current source; the common mode feedback circuit, its positive pole is connected with the positive output terminal of the differential output signal of the fully differential amplifier, and the negative pole is connected with the negative output of the differential output signal of the fully differential amplifier end connection. 2. A kind of high linearity low noise amplifier as claimed in claim 1, is characterized in that, described fully differential amplifier is jointly formed by typical fully differential circuit and cross-coupling capacitance; Described typical fully differential circuit comprises first to the fifth NMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the first to the fourth inductors, the first capacitor, the second capacitor, the third resistor, and the fourth resistor; the cross-coupling capacitor includes the third capacitor, The fourth capacitor, the first resistor, and the second resistor; The connection of the typical fully differential circuit is as follows: the drain of the first NMOS transistor (NM1) is connected to the source of the third NMOS transistor (NM3); the drain of the second NMOS transistor (NM2) is connected to the source of the fourth NMOS transistor (NM4) The drain of the third NMOS transistor (NM3) is connected to the drain of the seventh PMOS transistor (PM7); the drain of the fourth NMOS transistor (NM4) is connected to the drain of the eighth PMOS transistor (PM8); the third NMOS transistor ( NM3) gate, the fourth NMOS transistor (NM4) gate, the seventh PMOS transistor (PM7) source, the eighth PMOS transistor (PM8) source are respectively connected to the power supply (Vdd); the seventh PMOS transistor (PM7) gate pole and the gate of the eighth PMOS transistor (PM8) are respectively connected to the third bias voltage (Vbias3); the source and gate of the first NMOS transistor (NM1) are connected to the first capacitor (C1), and the first NMOS transistor (NM1) The source is connected to one end of the first inductor (L1); the second capacitor (C2) is connected between the source and the gate of the second NMOS transistor (NM2); the source of the second NMOS transistor (NM2) is connected to one end of the second inductor (L2) connected; the other end of the first inductor (L1) and the other end of the second inductor (L2) are respectively connected to the drain of the fifth NMOS transistor (NM5) as the tail current source of the fully differential circuit; the source of the fifth NMOS transistor (NM5) Grounded, the gate of the fifth NMOS transistor (NM5) is connected to the second bias voltage (Vbias2); the gate of the first NMOS transistor (NM1) is connected to one end of the third inductor (L3), and the other end of the third inductor (L3) is connected to the input The signal is connected to one end of the third resistor (R3), and the other end of the third resistor (R3) is connected to the first bias voltage (Vbias1); the gate of the second NMOS transistor (NM2) is connected to one end of the fourth inductor (L4), and the other end of the third resistor (R3) is connected to the first bias voltage (Vbias1). The other end of the four inductors (L4) is connected to the input signal and connected to one end of the fourth resistor (R4), and the other end of the fourth resistor (R4) is connected to the first bias voltage (Vbias1); The connection method between the typical fully differential circuit and the cross-coupling capacitor is as follows: one end of the third capacitor (C3) is respectively connected to the drain of the second NMOS transistor (NM2) and the source of the fourth NMOS transistor (NM4), and the third capacitor ( C3) The other end is connected to the gate of the third NMOS transistor (NM3); one end of the first resistor (R1) is connected to the gate of the third NMOS transistor (NM3), and the other end of the first resistor (R1) is connected to the power supply (Vdd ) connected; one end of the fourth capacitor (C4) is respectively connected to the drain of the first NMOS transistor (NM1) and the source of the third NMOS transistor (NM3), and the other end of the fourth capacitor (C4) is connected to the fourth NMOS transistor ( The gate of NM4) is connected; one end of the second resistor (R2) is connected with the gate of the fourth NMOS transistor (NM4), and the other end of the second resistor (R2) is connected with the power supply (Vdd). 3. The high-linearity low-noise amplifier according to claim 1, characterized in that, the third capacitor (C3) and the fourth capacitor (C4) are all capacitors supported by standard CMOS technology. 4. A kind of high-linearity low-noise amplifier as claimed in claim 1, is characterized in that, described common-mode feedback circuit comprises first to sixth PMOS transistor and sixth NMOS transistor; Wherein, the fifth PMOS transistor (PM5 ) source and the source of the sixth PMOS transistor (PM6) are respectively connected to the power supply (Vdd); the gate of the fifth PMOS transistor (PM5) and the gate of the sixth PMOS transistor (PM6) are respectively connected to one end of the sixth resistor (R6) , the other end of the sixth resistor (R6) is connected to the bias voltage (Vbias); the gate of the second PMOS transistor (PM2) and the gate of the third PMOS transistor (PM3) are respectively connected to one end of the seventh resistor (R7). The other end of the resistor (R7) is connected to the reference voltage (Vref); the source of the first PMOS transistor (PM1) is connected to the source of the second PMOS transistor (PM2) and the drain of the fifth PMOS transistor (PM5); the third PMOS transistor The source of (PM3) is connected to the source of the fourth PMOS transistor (PM4) and the drain of the sixth PMOS transistor (PM6); the drain of the first PMOS transistor (PM1) is connected to the drain of the fourth PMOS transistor (PM4); The gate of one PMOS transistor (PM1) and the gate of the fourth PMOS transistor (PM4) are respectively used as the positive and negative input terminals of the common mode feedback circuit; the common mode voltage is compared with the reference voltage (Vref), and the obtained voltage error is the common mode feedback circuit. The feedback voltage of the mode feedback circuit is output through the gate of the sixth NMOS transistor (NM6), and the gate of the sixth NMOS transistor (NM6) is connected to the drain. 5. A kind of high-linearity low-noise amplifier as claimed in claim 1 or 2 or 3 or 4, it is characterized in that, the output voltage of the common mode feedback circuit is negatively fed back to the fifth NMOS transistor of the tail current source of the fully differential amplifier ( NM5), and connect the fifth resistor (R5) between the fifth NMOS transistor (NM5) gate and the second bias voltage (Vbias2).

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