CN104134661B - A kind of high voltage integrated circuit and manufacture method thereof - Google Patents
A kind of high voltage integrated circuit and manufacture method thereof Download PDFInfo
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- CN104134661B CN104134661B CN201310159369.2A CN201310159369A CN104134661B CN 104134661 B CN104134661 B CN 104134661B CN 201310159369 A CN201310159369 A CN 201310159369A CN 104134661 B CN104134661 B CN 104134661B
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Abstract
The present invention provides a kind of high voltage integrated circuit using parasitic JFET isolation structure and manufacture method thereof.This high voltage integrated circuit includes low-voltage control circuit, high-voltage control circuit, level shift circuit, wherein the device of level shift circuit is transverse diffusion metal oxide semiconductor device (LDMOS), wherein this high voltage integrated circuit use parasitic junction field effect transistor to realize the isolation to LDMOS, the device of the present invention is when high-pressure work, Electric Field Distribution is more uniformly distributed, it can be avoided that the high electric field of local, so that it is guaranteed that the breakdown voltage of high basin does not reduces because of isolation structure, it is possible to improve the reliability of device.
Description
[technical field]
The present invention is about manufacture of semiconductor field, especially with regard to a kind of high pressure collection using parasitic JFET isolation structure
Become circuit and manufacture method thereof.
[background technology]
High voltage integrated circuit (HVIC), typically such as half-bridge drive circuit, includes low-voltage control circuit, high pressure in chip
Control circuit, low-voltage control circuit needs to output signal to high-voltage control circuit, high voltage control by level shift circuit simultaneously
Circuit needs by high voltage junction terminal (HVJT) around surrounding can bear high pressure.It is typically implemented the device of level shift function
Being the LDMOS of high pressure, the grid of the high-voltage LDMOS of level shift is controlled by low-voltage control circuit, and drain terminal and high voltage control
Circuit couples realizes level shift.The pressure of device is affected for avoiding drain terminal to pass through HVJT with high-voltage control circuit line, logical
Often can use self-isolation (self-shielding) mode, this mode needs the drain terminal high-voltage LDMOS and high voltage control electricity
Road is designed together, and in order to avoid high pressure line is through HVJT, need to solve high-voltage LDMOS and high-voltage control circuit every
From so that the function of its level shift normally works.
Fig. 1 is the schematic layout pattern of the HVIC of a kind of traditional employing self-isolation (self-shielding).Such as Fig. 1, show
Some high voltage integrated circuits include low-voltage control circuit 001, high-voltage control circuit 002, and low-voltage control circuit 001 and high pressure
Level shift circuit 003 between control circuit 002, wherein this level shift circuit is high-voltage LDMOS device, its grid 031
Being connected with low-voltage control circuit 001, drain electrode 032 is connected with high-voltage control circuit 002 by line 004, wherein high voltage control electricity
The drain electrode of road 002 and LDMOS device is by N-drift region 005(namely uses RESURF technology to bear the high voltage junction terminal of high pressure
(HVJT, high voltage junction termination)) around being surrounded, the drain electrode of such LDMOS device and grid
Also separated by N-drift region between pole.In order to high-voltage LDMOS device is kept apart with other parts, use 006, a p-type ring
LDMOS device is isolated.
Structure shown in Fig. 1 achieves self-isolation (self-shielding), i.e. line 004 without pass through high voltage junction eventually
End just can realize being connected to high lateral circuit, and uses 006 high-voltage LDMOS device 3 of p-type ring to keep apart.But p-type shading ring
The existence of 006 also can affect pressure, and Fig. 2 is the enlarged drawing that in Fig. 1, dotted line is enclosed the p-shaped ring 006 shown.Dotted line in Fig. 2 represents
Potential lines, by Fig. 2 it will be seen that owing to the N-region 005 of both sides, 005a are cut off by p-type shading ring 006, thus cause electricity
Gesture line bends, and produces comparatively dense district in local and produces high field intensity.This may cause pressure reduction or integrity problem.
[summary of the invention]
It is an object of the invention to provide a kind of high voltage integrated circuit, its use parasitic junction field-effect transistor as every
From structure.
Another object of the present invention is to provide a kind of uses parasitic junction field-effect transistor as the height of isolation structure
The manufacture method of pressure integrated circuit.
For reaching object defined above, one high voltage integrated circuit of the present invention, it includes low-voltage control circuit, high voltage control electricity
Road, level shift circuit, wherein the device of level shift circuit is transverse diffusion metal oxide semiconductor device (LDMOS),
The grid of LDMOS is connected with low-voltage control circuit, and the drain terminal of LDMOS is connected with high-voltage control circuit, at high-voltage control circuit
Periphery be formed by high-voltage control circuit around defendance high voltage junction terminal, be formed outside LDMOS a circle by LDMOS and other
The isolation structure of device isolation, described isolation structure forms the parasitic junction field effect transistor being in the normally off state.
Further, described high voltage integrated circuit is formed in P type substrate, and described technotron is by cincture
Discrete p-type ring of LDMOS is formed, and the most discrete p-type ring and P type substrate form the grid of technotron, non-
The interconnective high voltage junction terminal area of continuous print p-type ring both sides forms the raceway groove of technotron.
Further, wherein the pinch-off voltage of technotron is less than the drain terminal of high-voltage LDMOS under circuit working state
Current potential.
For reaching aforementioned another object, a kind of method manufacturing high voltage integrated circuit of the present invention, comprising:
P-type silicon substrate is provided；
Carry out thin oxidation, photoetching, implanted dopant phosphorus, remove photoresist, annealing steps formed high voltage integrated circuit level shift electricity
N-buried regions below the drain terminal of road LDMOS device；
By photoetching, implanted dopant antimony or arsenic, remove photoresist, the N+ in Gao Pen district that annealing steps forms high voltage integrated circuit buries
Layer, high-voltage control circuit designs on high basin N+ buried regions, and this N+ buried regions makes high-voltage control circuit isolate with substrate；
Carry out photoetching, implanted dopant boron, the level shift circuit LDMOS device of the annealing steps that removes photoresist formation high voltage integrated circuit
The P buried regions of part；
Then growing P-type epitaxial layer；
P-shaped epitaxial layer is formed silicon nitride layer；
Remove partial nitridation silicon layer, inject phosphorus in the position removing silicon nitride layer and form high pressure N trap 107, high pressure N trap and front
The N-buried regions of the drain terminal formed before the extension stated is collectively forming the drift region of level shift devices LDMOS, this drift region (i.e. high pressure
Knot terminal HVJT) the most also guarantee that high-voltage control circuit can bear high pressure around high-voltage control circuit；
Further inject into phosphorus at high pressure N well region and form low pressure N trap；
The silicon chip removing silicon nitride layer is formed layer of oxide layer；
Remove remaining silicon nitride layer, inject boron in the position removing remaining nitride silicon layer, form p-well, concurrently form bag
Enclose the discontinuous ring-shaped P trap of the level shift circuit LDMOS device of high voltage integrated circuit；
Remove the oxide layer of silicon chip surface, then grow thin oxygen and silicon nitride, carry out photoetching, corroding silicon nitride, remove photoresist, so
Rear formation field oxide, removal is sheltered the silicon nitride of oxidation and is obtained active area window；
Growth gate oxide and polysilicon gate, carry out being lithographically formed the level shift circuit LDMOS device of high voltage integrated circuit
The grid of part；
Inject and form N+ district, form source electrode and the drain electrode of the level shift circuit LDMOS device of high voltage integrated circuit；
Inject and form P+ district, for drawing the substrate terminal of level shift circuit LDMOS device i.e. the exit of p-well.
Then somatomedin layer carry out photoetching, etch media layer forms fairlead, then carries out the sputtering of metal level, then
Metal level carries out chemical wet etching remove photoresist and form the metal lead wire of level shift circuit LDMOS device of high voltage integrated circuit.
Further, aforementioned discontinuous ring-shaped P trap forms the grid of parasitic junction field effect transistor, phase between ring-shaped P trap
The region connected forms the raceway groove of technotron.
Further, the pinch-off voltage of aforementioned technotron is less than the drain terminal of high-voltage LDMOS under circuit working state
Current potential.
Compared with prior art, present configuration uses the parasitic fields effect transistor isolation that discontinuous p-type ring is formed
The level shift circuit of high tension apparatus, and this parasitic fields effect transistor is the normally off state, and obtained device is at high-pressure work
Time, Electric Field Distribution is more uniformly distributed, it is to avoid the high electric field of local, so that it is guaranteed that the breakdown voltage of high basin does not reduces because of isolation structure
With improve reliability.
[accompanying drawing explanation]
Fig. 1 is the structural plan schematic diagram of existing high voltage integrated circuit.
Fig. 2 is the Potential Distributing schematic diagram of existing high voltage integrated circuit.
Fig. 3 a is the structural plan schematic diagram of the high voltage integrated circuit of the present invention.
Fig. 3 b is the sectional view in the line A-A direction along Fig. 3 a.
Fig. 3 c is the sectional view in the line B-B direction along Fig. 3 a.
Fig. 4 is the Potential Distributing schematic diagram of the high voltage integrated circuit of the present invention.
Fig. 5 is the equivalent circuit diagram that the LDMOS device of the high voltage integrated circuit of the present invention is isolated from it structure.
Fig. 6 a to Fig. 6 m-2 is the knot that the LDMOS device of the high voltage integrated circuit of the present invention is isolated from it structure manufacturing process
Structure schematic diagram.
[detailed description of the invention]
" embodiment " or " embodiment " referred to herein refers to may be included at least one implementation of the present invention
Special characteristic, structure or characteristic.Different in this manual local " in one embodiment " occurred not refer both to same
Individual embodiment, is not single or the most mutually exclusive with other embodiments embodiment.
As it was previously stated, in the isolation method of the level shift circuit of existing high tension apparatus, due to the existence of p-type ring, lead
Cause to produce comparatively dense district in local and produce high field intensity.This may cause pressure reduction or integrity problem.
As shown in Figure 3 a, the high voltage integrated circuit of the present invention, it includes low-voltage control circuit 1, high-voltage control circuit equally
Level shift circuit 3 between 2, and low-voltage control circuit 1 and high-voltage control circuit 2, wherein this level shift circuit 3 is high
Pressure LDMOS device, the grid 31 of this high-voltage LDMOS device is connected with low-voltage control circuit 1, the drain electrode of this high-voltage LDMOS device
32 are connected with high-voltage control circuit 2 by line 4, and wherein the drain electrode 32 of high-voltage control circuit 2 and LDMOS device is drifted about by N-
District 5, around being surrounded, is also separated by N-drift region 5 between drain electrode 32 and the grid 31 of such LDMOS device.Wherein this N-drift
Moving district 5 is high voltage junction terminal (HVJT, the high voltage junction using RESURF technology to bear high pressure
termination)。
As shown in fig. 3a, different from the isolation structure of prior art, the present invention by LDMOS device and other structure every
The isolation structure left uses discrete p-type ring 6, and such LDMOS device does not has completely separated, and surrounds high pressure
The N-drift region of control circuit does not has the most completely separated yet, drift region 5a between the drain electrode and grid of LDMOS and its
The N-drift region 5 of its part is only isolated by discrete p-type ring 6, and the Reng Youn-drift region, gap of discrete p-type ring 6 is even
Connect.
As shown in Fig. 3 b and Fig. 3 c, the isolation of discrete p-type ring 6 of the present invention is connected with P type substrate and is considered as parasitism N
The grid of channel junction field-effect pipe (NJFET), interconnective N-drift region, p-type shading ring both sides 5 and 5a is considered as posting
The raceway groove of raw N-channel technotron.
Owing to the N-drift region 5 and 5a in Fig. 3 a is interconnective, this can change Electric Field Distribution during high pressure, such as figure
Shown in 4, when its display uses the isolation structure of the present invention, the potential profile at shading ring that in Fig. 3 a, dotted line is enclosed, in figure
Dotted line i.e. potential lines, its Electric Field Distribution is uniform as seen from Figure 4, eliminates high field area.
Due to the fact that and have employed discrete p-type ring, causing N-drift region 6 and 6a in Fig. 3 a is to connect, Qi Zhongfei
Continuous print p-type ring forms a parasitic NJFET with the N-drift region of its both sides, in order to realize the isolation to LDMOS, this
NJFET can not turn on, so needing appropriate design technique and domain, makes this parasitic NJFET be designed to the normally off state.Such as figure
Shown in 5, the LDMOS of its display present invention and the equivalent circuit diagram of parasitic junction field effect transistor NJFET of discontinuous p-type ring, as
Shown in Fig. 5, side circuit is used for the drain terminal of high-voltage LDMOS of level shift by a resistance and the power end of high side
(Vb in Fig. 5) is connected, so its drain terminal current potential is positive potential all the time, then have only to correctly design guarantee in Fig. 5 parasitic
The pinch-off voltage of NJFET is less than the drain terminal current potential of the high-voltage LDMOS under circuit working state, then this parasitic NJFET can be in
The normally off state, thus play the effect of isolation.
Refer to shown in Fig. 6 a to Fig. 6 l-2, the LDMOS device of its display present invention and the manufacturing process of isolation structure thereof.
What wherein the identical figure number of Fig. 6 g-1 to Fig. 6 l-2 figure was shown respectively is line A-A and the sectional view of line B-B along Fig. 3 a.
As shown in Figure 6 a, the present invention is generally selected the P-type silicon substrate of low concentration, as shown in 100 in Fig. 6 a.First carry out
Thin oxygen, the 1st photoetching, implanted dopant phosphorus, remove photoresist, N-region 101a and 101b that annealing steps is formed in Fig. 6 a, this region
It is positioned at drain terminal and the lower section of high side control circuit of HVJT, it is common that thin and deeper N-buried regions.
As shown in Figure 6 b, carry out the 2nd photoetching, implanted dopant antimony or arsenic, remove photoresist, annealing steps formed high voltage integrated circuit
The N+ buried regions in Gao Pen district, i.e. N+ buried regions 103 in Fig. 6 a, N+ buried regions 103 is positioned at the lower section of high side control circuit.High voltage control
Circuit design is on high basin N+ buried regions, and this N+ buried regions makes high-voltage control circuit isolate with substrate.
As fig. 6 c, then carry out the 3rd photoetching, implanted dopant boron, remove photoresist, P that annealing steps is formed in Fig. 6 c buries
Layer 102a and 102b, wherein below the p-well of the source that P buried regions 102a is positioned at high-voltage LDMOS or HVJT, P buried regions 102b is positioned at and posts
5a in raw NJFET(Fig. 3 a) lower section.
As shown in fig 6d, then growing P-type epitaxial layer 104, now original N-region 101a, 101b and N+ buried regions formed
103 and P buried regions 102a, 102b can extend into p-type epitaxial layer 104, and therefore the upper surface of original silicon chip surface changes and is represented by dashed line,
Represent the position of original silicon chip upper surface.
As shown in fig 6e, delay outside growing P-type, use one layer of thin oxygen layer 105 of thermal oxide length.
As shown in Figure 6 f, at one layer of silicon nitride layer 106 of surface regeneration length of thin oxygen layer 105.
Refer to, shown in Fig. 6 g-1 and Fig. 6 g-2, carry out the 4th photoetching, etch nitride silicon layer 106, wherein remove silicon nitride
Layer 106 window be used for defining high pressure N trap, stay the place of silicon nitride layer for defining p-well, as the 106a in figure, 106b,
The position of 106c.Wherein Fig. 6 g-1 is the sectional view of line A-A position along Fig. 3 a, and Fig. 6 g-2 is line B-B position along Fig. 3 a
Sectional view, because there is p-type ring line A-A position in Fig. 3 a, i.e. needs to inject the position of p-well, so ratio Fig. 6 g-in Fig. 6 g-1
Leaving silicon nitride layer 106b 2 more.Then inject phosphorus in the position removing silicon nitride layer 106 and form high pressure N trap 107.High pressure N trap
107 and aforesaid extension before N-buried regions 101a, 101b of drain terminal of being formed be collectively forming the drift of level shift devices LDMOS
District, around high-voltage control circuit, this drift region (i.e. high voltage junction terminal HVJT) the most also guarantees that high-voltage control circuit can bear height
Pressure.
As shown in Fig. 6 h-1 and Fig. 6 h-2, the position forming high pressure N trap in Fig. 6 g-1 and Fig. 6 g-2 carries out the 5th light again
Carve, inject phosphorus and coordinate low pressure N trap 108a and 108b.
As shown in Fig. 6 i-1 and Fig. 6 i-2, silicon chip aoxidizes through a trap afterwards, not having shown in Fig. 6 h-1 and Fig. 6 h-2
The region having silicon nitride layer 106 to cover obtains the oxide layer 109 of one layer of about 5000A.
As shown in Fig. 6 j-1 and Fig. 6 j-2, then remove the silicon nitride layer 106a in Fig. 6 i-1 and Fig. 6 i-2,106b,
106c, silicon chip does the most general note, injects boron and forms the doping of p-well, forms p-well 110a in figure, 110b, 110c.Then carry out
High temperature pushes away trap and forms p-well 110a110b in Fig. 6 j-1 and Fig. 6 j-2 and 110c, and it is to carry out whole silicon chip that high temperature pushes away trap
High temperature pushes away trap, and it is deeper that the high pressure N trap 107 being therefore originally defined and low pressure N trap 108a and 108b also become.
P-well 110a formed in Fig. 6 j-1 and Fig. 6 j-2 is used as the source of high-voltage LDMOS and channel region or conduct
The source (low-pressure end) of HVJT, the discontinuous p-type ring in the p-well 110b i.e. Fig. 3 a formed in Fig. 6 j-1 and Fig. 6 j-2, permissible
Regarding the grid of parasitic NJFET as, the channel region of parasitic NJFET is then the 110b ' in Fig. 6 j-2, in Fig. 6 j-1 and Fig. 6 j-2
The P buried regions 102b of 110b with 110b ' lower section is connected with substrate P, it is possible to regard a part for the grid of parasitic NJFET as.
As shown in Fig. 6 k-1 and Fig. 6 k-2, then oxide layer 109 erosion removal of original silicon chip surface.Then according to mark
Accurate LOCOS technique, grows thin oxygen and silicon nitride, carries out the 6th photoetching, corroding silicon nitride, remove photoresist, then form field oxide
111, removal is sheltered the silicon nitride of oxidation and is obtained active area window.
As shown in Fig. 6 l-1 and Fig. 6 l-2, regrowth gate oxide and polysilicon gate, carry out the 7th this photoetching, etches polycrystalline
Silicon, removes photoresist and forms the grid of high-voltage LDMOS, such as the grid 112 in figure Fig. 6 l-1 and Fig. 6 l-2.Carry out the 8th photoetching the most again,
Injection is removed photoresist and is formed Fig. 6 l-1 and 113a, 113b, 113c, and P+ district of Fig. 6 l-2 Zhong N+ district 114, and wherein N+ district 113a is high
Pressure LDMOS source extraction electrode, N+ district 113b is the drain terminal extraction electrode of high-voltage LDMOS.P+ district 114, is used for drawing level shift
The substrate terminal of circuit LDMOS device i.e. the exit of p-well.
As shown in Fig. 6 m-1 and Fig. 6 m-2, then somatomedin layer 115, and carry out the 9th photoetching, etch media layer 115
And fairlead 116 in the formation Fig. 6 m-1 and Fig. 6 m-2 that removes photoresist, then carry out the chemical wet etching of the sputtering followed by metal level of metal level
Remove photoresist formation metal lead wire 117a, 117b, 117c, and wherein metal lead wire 117a draws for the source drawing high-voltage LDMOS simultaneously
Going out p-well, metal lead wire 117b is for the drain terminal extraction electrode of high-voltage LDMOS, and metal lead wire 117c is for high side circuit part electricity
Vb in source i.e. Fig. 5.
So far, whole LDMOS device and isolation structure manufacture thereof complete.
The parasitic fields effect transistor that present configuration uses discontinuous p-type ring to be formed is isolated the level of high tension apparatus and is moved
Position circuit, and this parasitic fields effect transistor is the normally off state, and obtained device is when high-pressure work, and Electric Field Distribution is the most equal
It is even, it is to avoid the high electric field of local, so that it is guaranteed that the breakdown voltage of high basin does not reduces because of isolation structure and improves reliability.
Described above the most fully discloses the detailed description of the invention of the present invention.It is pointed out that and be familiar with this field
Any change that the detailed description of the invention of the present invention is done by technical staff is all without departing from the scope of claims of the present invention.
Correspondingly, the scope of the claim of the present invention is also not limited only to previous embodiment.
Claims (6)
1. a high voltage integrated circuit, it includes low-voltage control circuit, high-voltage control circuit, level shift circuit, wherein level
The device of shift circuit is transverse diffusion metal oxide semiconductor device LDMOS, and the grid of LDMOS is with low-voltage control circuit even
Connecing, the drain terminal of LDMOS is connected with high-voltage control circuit, is formed high-voltage control circuit cincture in the periphery of high-voltage control circuit
The high voltage junction terminal of defendance, it is characterised in that: outside LDMOS, it is formed with discontinuous by LDMOS and other device isolation of a circle
Isolation structure, formed based on described discrete isolation structure and be in the parasitic junction field effect transistor of the normally off state.
2. high voltage integrated circuit as claimed in claim 1, it is characterised in that: described high voltage integrated circuit is formed at p-type lining
, described parasitic junction field effect transistor is formed by the discrete p-type ring around LDMOS, the most discrete p-type ring and P at the end
Type substrate forms the grid of parasitic junction field effect transistor, the interconnective high voltage junction terminal area of discrete p-type ring both sides
Form the raceway groove of parasitic junction field effect transistor.
3. high voltage integrated circuit as claimed in claim 1, it is characterised in that: the pinch off of wherein said parasitic junction field effect transistor
Voltage is less than the drain terminal current potential of LDMOS under circuit working state.
4. the method manufacturing high voltage integrated circuit, comprising:
P-type silicon substrate is provided；
Carry out aoxidizing, photoetching, implanted dopant phosphorus, remove photoresist, annealing steps forms the level shift circuit LDMOS of high voltage integrated circuit
The N-buried regions of device drain terminal；
By photoetching, implanted dopant antimony or arsenic, remove photoresist, annealing steps forms the N+ buried regions in Gao Pen district of high voltage integrated circuit, high
Pressure design on control circuit is on the N+ buried regions of Gao Penqu, and this N+ buried regions makes high-voltage control circuit isolate with substrate；
Carry out the level shift circuit LDMOS device of photoetching, implanted dopant boron, the annealing steps that removes photoresist formation high voltage integrated circuit
P buried regions；
Then growing P-type epitaxial layer；
P-shaped epitaxial layer is formed silicon nitride layer；
Remove partial nitridation silicon layer, remove silicon nitride layer position inject phosphorus formed high pressure N trap, high pressure N trap and aforesaid outside
Before prolonging, the N-buried regions of the drain terminal of formation is collectively forming the drift region of level shift devices LDMOS, and this drift region is the most also around high
Pressure control circuit guarantees that high-voltage control circuit can bear high pressure；
Further inject into phosphorus at high pressure N well region and form low pressure N trap；
The silicon chip removing silicon nitride layer is formed layer of oxide layer；
Remove remaining silicon nitride layer, inject boron in the position removing remaining nitride silicon layer, form p-well, concurrently form encirclement height
The discontinuous ring-shaped P trap of the level shift circuit LDMOS device of pressure integrated circuit；
Remove the oxide layer of silicon chip surface, then grow thin oxygen and silicon nitride, carry out photoetching, corroding silicon nitride, remove photoresist, then shape
Become field oxide, removal to shelter the silicon nitride of oxidation and obtain active area window；
Growth gate oxide and polysilicon gate, carries out being lithographically formed the level shift circuit LDMOS device of high voltage integrated circuit
Grid；
Inject and form N+ district, form source electrode and the drain electrode of the level shift circuit LDMOS device of high voltage integrated circuit；
Inject and form P+ district, for drawing the substrate terminal of level shift circuit LDMOS device i.e. the exit of p-well；
Then somatomedin layer carry out photoetching, etch media layer forms fairlead, then carries out the sputtering of metal level, then to gold
Belong to layer to carry out chemical wet etching and remove photoresist and form the metal lead wire of level shift circuit LDMOS device of high voltage integrated circuit.
5. method as claimed in claim 4, it is characterised in that: aforementioned discontinuous ring-shaped P trap forms parasitic junction field effect
The grid of pipe, between ring-shaped P trap, interconnective region forms the raceway groove of parasitic junction field effect transistor.
6. method as claimed in claim 5, it is characterised in that: the pinch-off voltage of described parasitic junction field effect transistor is less than circuit
The drain terminal current potential of high-voltage LDMOS under duty.
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| CN109427771B (en) * | 2017-09-01 | 2020-10-30 | 无锡华润上华科技有限公司 | Integrated circuit chip, manufacturing method thereof and gate drive circuit |
| CN109817718A (en) * | 2019-01-08 | 2019-05-28 | 上海华虹宏力半导体制造有限公司 | The high-voltage isolating ring device of gate drive circuit |
| CN117374072A (en) * | 2022-06-30 | 2024-01-09 | 无锡华润上华科技有限公司 | Semiconductor device and method for manufacturing the same |
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| CN102244092A (en) * | 2011-06-20 | 2011-11-16 | 电子科技大学 | Junction termination structure of transverse high-pressure power semiconductor device |
| CN102306656A (en) * | 2011-08-23 | 2012-01-04 | 东南大学 | Isolation structure of high voltage driver circuit |
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| KR100374627B1 (en) * | 2000-08-04 | 2003-03-04 | 페어차일드코리아반도체 주식회사 | High voltage semiconductor device having a high breakdown voltage isolation region |
| KR100363101B1 (en) * | 2001-04-16 | 2002-12-05 | 페어차일드코리아반도체 주식회사 | High voltage semiconductor device having a high breakdown voltage isolation region |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102244092A (en) * | 2011-06-20 | 2011-11-16 | 电子科技大学 | Junction termination structure of transverse high-pressure power semiconductor device |
| CN102306656A (en) * | 2011-08-23 | 2012-01-04 | 东南大学 | Isolation structure of high voltage driver circuit |
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Effective date of registration: 20171031 Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Patentee after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China Patentee before: Wuxi CSMC Semiconductor Co., Ltd. |