ATE374399T1 - Integrierter schaltkreis und verfahren zum erstellen von transaktionen - Google Patents
Integrierter schaltkreis und verfahren zum erstellen von transaktionenInfo
- Publication number
- ATE374399T1 ATE374399T1 AT03748424T AT03748424T ATE374399T1 AT E374399 T1 ATE374399 T1 AT E374399T1 AT 03748424 T AT03748424 T AT 03748424T AT 03748424 T AT03748424 T AT 03748424T AT E374399 T1 ATE374399 T1 AT E374399T1
- Authority
- AT
- Austria
- Prior art keywords
- module
- address
- integrated circuit
- addressed
- slave
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/32—Flow control; Congestion control by discarding or delaying data units, e.g. packets or frames
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9063—Intermediate storage in different physical parts of a node or terminal
- H04L49/9068—Intermediate storage in different physical parts of a node or terminal in the network interface card
- H04L49/9073—Early interruption upon arrival of a fraction of a packet
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Mathematical Physics (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Communication Control (AREA)
- Multi Processors (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Bus Control (AREA)
- Semiconductor Integrated Circuits (AREA)
- Microcomputers (AREA)
- Computer And Data Communications (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02079196 | 2002-10-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE374399T1 true ATE374399T1 (de) | 2007-10-15 |
Family
ID=32088020
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT03740945T ATE373922T1 (de) | 2002-10-08 | 2003-07-04 | Integrierter schaltkreis und verfahren zum erstellen von transaktionen |
AT03748424T ATE374399T1 (de) | 2002-10-08 | 2003-10-07 | Integrierter schaltkreis und verfahren zum erstellen von transaktionen |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT03740945T ATE373922T1 (de) | 2002-10-08 | 2003-07-04 | Integrierter schaltkreis und verfahren zum erstellen von transaktionen |
Country Status (10)
Country | Link |
---|---|
US (3) | US7769893B2 (de) |
EP (3) | EP1552411A2 (de) |
JP (3) | JP2006502642A (de) |
KR (1) | KR101016987B1 (de) |
CN (5) | CN100342370C (de) |
AT (2) | ATE373922T1 (de) |
AU (3) | AU2003299454A1 (de) |
DE (2) | DE60316458T2 (de) |
TW (1) | TWI307840B (de) |
WO (3) | WO2004034173A2 (de) |
Families Citing this family (82)
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JP2007500894A (ja) * | 2003-07-30 | 2007-01-18 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 動的通信サービス選択を備えた集積回路 |
JP4598051B2 (ja) * | 2004-03-03 | 2010-12-15 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | データ処理ユニットがネットワークを介し通信するデータ処理回路 |
US20070234006A1 (en) * | 2004-04-26 | 2007-10-04 | Koninklijke Philips Electronics, N.V. | Integrated Circuit and Metod for Issuing Transactions |
EP1751667B1 (de) * | 2004-05-18 | 2008-05-21 | Koninklijke Philips Electronics N.V. | Integrierte schaltung und verfahren zur pufferung zur optimierung der burst-länge in netzwerken auf chips |
EP1605727A1 (de) * | 2004-06-09 | 2005-12-14 | Koninklijke Philips Electronics N.V. | Integrierte Schaltungsanordnung und Verfahren zur Zuordnung von Zeitlagen |
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2003
- 2003-07-04 KR KR1020057005986A patent/KR101016987B1/ko active IP Right Grant
- 2003-07-04 WO PCT/IB2003/003035 patent/WO2004034173A2/en active Application Filing
- 2003-07-04 AT AT03740945T patent/ATE373922T1/de not_active IP Right Cessation
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