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NL7609320A - Halfgeleiderinrichting. - Google Patents

Halfgeleiderinrichting.

Info

Publication number
NL7609320A
NL7609320A NL7609320A NL7609320A NL7609320A NL 7609320 A NL7609320 A NL 7609320A NL 7609320 A NL7609320 A NL 7609320A NL 7609320 A NL7609320 A NL 7609320A NL 7609320 A NL7609320 A NL 7609320A
Authority
NL
Netherlands
Prior art keywords
semi
guide device
guide
Prior art date
Application number
NL7609320A
Other languages
English (en)
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of NL7609320A publication Critical patent/NL7609320A/nl

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312Organic layers, e.g. photoresist
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
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    • H01L2224/0554External layer
    • H01L2224/0555Shape
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48599Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624Aluminium (Al) as principal constituent
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
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    • H01L2924/01006Carbon [C]
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    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
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    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • H01L2924/12036PN diode
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
NL7609320A 1975-08-22 1976-08-20 Halfgeleiderinrichting. NL7609320A (nl)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50101245A JPS5851425B2 (ja) 1975-08-22 1975-08-22 ハンドウタイソウチ

Publications (1)

Publication Number Publication Date
NL7609320A true NL7609320A (nl) 1977-02-24

Family

ID=14295510

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7609320A NL7609320A (nl) 1975-08-22 1976-08-20 Halfgeleiderinrichting.

Country Status (4)

Country Link
US (1) US4060828A (nl)
JP (1) JPS5851425B2 (nl)
DE (1) DE2637667C2 (nl)
NL (1) NL7609320A (nl)

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JPS5833705B2 (ja) * 1975-08-27 1983-07-21 株式会社日立製作所 タソウハイセンオ ユウスルハンドウタイソウチ
JPS5421165A (en) * 1977-07-18 1979-02-17 Nec Corp Semiconductor device
JPS5459080A (en) * 1977-10-19 1979-05-12 Nec Corp Semiconductor device
JPS54139415A (en) * 1978-04-21 1979-10-29 Hitachi Ltd Semiconductor channel switch
US4433004A (en) * 1979-07-11 1984-02-21 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device and a method for manufacturing the same
JPS56150830A (en) * 1980-04-25 1981-11-21 Hitachi Ltd Semiconductor device
JPS5925387B2 (ja) * 1980-06-10 1984-06-16 株式会社東芝 半導体装置
JPS5670646U (nl) * 1980-10-03 1981-06-11
JPS57211248A (en) * 1981-06-22 1982-12-25 Hitachi Ltd Semiconductor integrated circuit device
FR2510307A1 (fr) * 1981-07-24 1983-01-28 Hitachi Ltd Dispositif a semi-conducteurs et procede de fabrication d'un tel dispositif
JPS59191353A (ja) * 1983-04-15 1984-10-30 Hitachi Ltd 多層配線構造を有する電子装置
JPS6178151A (ja) * 1984-09-25 1986-04-21 Nec Corp 半導体装置
US4672739A (en) * 1985-04-11 1987-06-16 International Business Machines Corporation Method for use in brazing an interconnect pin to a metallization pattern situated on a brittle dielectric substrate
US4755631A (en) * 1985-04-11 1988-07-05 International Business Machines Corporation Apparatus for providing an electrical connection to a metallic pad situated on a brittle dielectric substrate
IT1215268B (it) * 1985-04-26 1990-01-31 Ates Componenti Elettron Apparecchio e metodo per il confezionamento perfezionato di dispositivi semiconduttori.
JPH06101532B2 (ja) * 1986-10-29 1994-12-12 三菱電機株式会社 半導体集積回路装置
US4759431A (en) * 1987-04-15 1988-07-26 Samsonite Corporation Travel bag with combination pull handle and auxiliary bag strap
JPH01128615U (nl) * 1988-02-26 1989-09-01
JPH01131313U (nl) * 1988-02-29 1989-09-06
JPH01225137A (ja) * 1988-03-04 1989-09-08 Toshiba Corp 半導体集積回路装置
JPH01280368A (ja) * 1988-05-06 1989-11-10 Sharp Corp 化合物半導体発光素子
JPH02105418A (ja) * 1988-10-14 1990-04-18 Mitsubishi Electric Corp 樹脂封止型半導体装置
US5293073A (en) * 1989-06-27 1994-03-08 Kabushiki Kaisha Toshiba Electrode structure of a semiconductor device which uses a copper wire as a bonding wire
JPH03233972A (ja) * 1990-02-08 1991-10-17 Matsushita Electron Corp 半導体装置用電極およびその製造方法
US5384488A (en) * 1992-06-15 1995-01-24 Texas Instruments Incorporated Configuration and method for positioning semiconductor device bond pads using additional process layers
US20020053734A1 (en) 1993-11-16 2002-05-09 Formfactor, Inc. Probe card assembly and kit, and methods of making same
US5495667A (en) * 1994-11-07 1996-03-05 Micron Technology, Inc. Method for forming contact pins for semiconductor dice and interconnects
EP0734059B1 (en) * 1995-03-24 2005-11-09 Shinko Electric Industries Co., Ltd. Chip sized semiconductor device and a process for making it
KR0145128B1 (ko) * 1995-04-24 1998-08-17 김광호 열방열 핀을 구비한 내부 리드 본딩 장치 및 이를 이용한 내부 리드 본딩 방법
US5994152A (en) * 1996-02-21 1999-11-30 Formfactor, Inc. Fabricating interconnects and tips using sacrificial substrates
US8033838B2 (en) 1996-02-21 2011-10-11 Formfactor, Inc. Microelectronic contact structure
US5903058A (en) * 1996-07-17 1999-05-11 Micron Technology, Inc. Conductive bumps on die for flip chip application
TW332336B (en) * 1997-09-15 1998-05-21 Winbond Electruction Company Anti-peeling bonding pad structure
US6495442B1 (en) * 2000-10-18 2002-12-17 Magic Corporation Post passivation interconnection schemes on top of the IC chips
US6965165B2 (en) * 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US6284079B1 (en) * 1999-03-03 2001-09-04 International Business Machines Corporation Method and structure to reduce low force pin pull failures in ceramic substrates
US6306749B1 (en) * 1999-06-08 2001-10-23 Winbond Electronics Corp Bond pad with pad edge strengthening structure
KR100313706B1 (ko) 1999-09-29 2001-11-26 윤종용 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법
US6555757B2 (en) * 2000-04-10 2003-04-29 Ngk Spark Plug Co., Ltd. Pin solder jointed to a resin substrate, made having a predetermined hardness and dimensions
US7566964B2 (en) * 2003-04-10 2009-07-28 Agere Systems Inc. Aluminum pad power bus and signal routing for integrated circuit devices utilizing copper technology interconnect structures
US20050137540A1 (en) * 2003-12-23 2005-06-23 Kimberly-Clark Worldwide, Inc. Bacteria removing wipe
US7242102B2 (en) * 2004-07-08 2007-07-10 Spansion Llc Bond pad structure for copper metallization having increased reliability and method for fabricating same
US11158595B2 (en) * 2017-07-07 2021-10-26 Texas Instruments Incorporated Embedded die package multichip module
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US3558992A (en) * 1968-06-17 1971-01-26 Rca Corp Integrated circuit having bonding pads over unused active area components
NL161617C (nl) * 1968-06-17 1980-02-15 Nippon Electric Co Halfgeleiderinrichting met vlak oppervlak en werkwijze voor het vervaardigen daarvan.
US3629669A (en) * 1968-11-25 1971-12-21 Gen Motors Corp Passivated wire-bonded semiconductor device
NL159822B (nl) * 1969-01-02 1979-03-15 Philips Nv Halfgeleiderinrichting.
US3751292A (en) * 1971-08-20 1973-08-07 Motorola Inc Multilayer metallization system
JPS4834686A (nl) * 1971-09-09 1973-05-21
US3809625A (en) * 1972-08-15 1974-05-07 Gen Motors Corp Method of making contact bumps on flip-chips
JPS5748854B2 (nl) * 1973-03-09 1982-10-19

Also Published As

Publication number Publication date
JPS5226187A (en) 1977-02-26
DE2637667A1 (de) 1977-02-24
US4060828A (en) 1977-11-29
JPS5851425B2 (ja) 1983-11-16
DE2637667C2 (de) 1984-05-24

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