NL6517226A - - Google Patents
Info
- Publication number
- NL6517226A NL6517226A NL6517226A NL6517226A NL6517226A NL 6517226 A NL6517226 A NL 6517226A NL 6517226 A NL6517226 A NL 6517226A NL 6517226 A NL6517226 A NL 6517226A NL 6517226 A NL6517226 A NL 6517226A
- Authority
- NL
- Netherlands
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/051—Etching
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/085—Isolated-integrated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/102—Mask alignment
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/977—Thinning or removal of substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Pressure Sensors (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB58/65A GB1066911A (en) | 1965-01-01 | 1965-01-01 | Semiconductor devices |
Publications (1)
Publication Number | Publication Date |
---|---|
NL6517226A true NL6517226A (de) | 1966-07-04 |
Family
ID=9697659
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NL6517226A NL6517226A (de) | 1965-01-01 | 1965-12-31 |
Country Status (4)
Country | Link |
---|---|
US (1) | US3428499A (de) |
DE (1) | DE1514073B2 (de) |
GB (1) | GB1066911A (de) |
NL (1) | NL6517226A (de) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1421766A (en) * | 1972-03-21 | 1976-01-21 | Ici Ltd | Salicylaldoximes and their use in metal extraction processes |
GB1520925A (en) * | 1975-10-06 | 1978-08-09 | Mullard Ltd | Semiconductor device manufacture |
US4321747A (en) * | 1978-05-30 | 1982-03-30 | Tokyo Shibaura Denki Kabushiki Kaisha | Method of manufacturing a solid-state image sensing device |
EP0547677A3 (en) * | 1991-12-17 | 1996-10-16 | Philips Nv | Use of vapor-phase etching in fabrication of semiconductor-on-insulator structure |
US5294808A (en) * | 1992-10-23 | 1994-03-15 | Cornell Research Foundation, Inc. | Pseudomorphic and dislocation free heteroepitaxial structures |
US6033489A (en) * | 1998-05-29 | 2000-03-07 | Fairchild Semiconductor Corp. | Semiconductor substrate and method of making same |
US6927073B2 (en) * | 2002-05-16 | 2005-08-09 | Nova Research, Inc. | Methods of fabricating magnetoresistive memory devices |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL268294A (de) * | 1960-10-10 | |||
DE1258983B (de) * | 1961-12-05 | 1968-01-18 | Telefunken Patent | Verfahren zum Herstellen einer Halbleiteranordnung mit epitaktischer Schicht und mindestens einem pn-UEbergang |
US3320485A (en) * | 1964-03-30 | 1967-05-16 | Trw Inc | Dielectric isolation for monolithic circuit |
US3312879A (en) * | 1964-07-29 | 1967-04-04 | North American Aviation Inc | Semiconductor structure including opposite conductivity segments |
DE1250514B (de) * | 1965-06-28 | 1900-01-01 |
-
1965
- 1965-01-01 GB GB58/65A patent/GB1066911A/en not_active Expired
- 1965-10-11 US US494350A patent/US3428499A/en not_active Expired - Lifetime
- 1965-12-11 DE DE19651514073 patent/DE1514073B2/de active Pending
- 1965-12-31 NL NL6517226A patent/NL6517226A/xx unknown
Also Published As
Publication number | Publication date |
---|---|
DE1514073B2 (de) | 1971-01-21 |
US3428499A (en) | 1969-02-18 |
DE1514073A1 (de) | 1969-06-12 |
GB1066911A (en) | 1967-04-26 |