Kalaiyarasi et al., 2019 - Google Patents
An efficient implementation of least mean square adaptive FIR filter based on distributed arithmeticKalaiyarasi et al., 2019
View PDF- Document ID
- 3001005492816449403
- Author
- Kalaiyarasi D
- Reddy T
- Publication year
- Publication venue
- Far East J. Electron. Commun.
External Links
Snippet
A novel pipelined architecture implementation of least mean square (LMS) adaptive FIR filter based on distributed arithmetic (DA) algorithm is presented. In conventional DA, partial product of filter coefficients is precomputed and stored in look up tables (LUTs) and it is …
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
- G06F7/5332—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by skipping over strings of zeroes or ones, e.g. using the Booth Algorithm
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/5443—Sum of products
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
- G06F17/141—Discrete Fourier transforms
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
- G06F17/147—Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/11—Complex mathematical operations for solving equations, e.g. nonlinear equations, general mathematical optimization problems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/386—Special constructional features
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0223—Computation saving measures; Accelerating measures
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Park et al. | Low-power, high-throughput, and low-area adaptive FIR filter based on distributed arithmetic | |
Meher et al. | Low adaptation-delay LMS adaptive filter part-II: An optimized architecture | |
Saritha et al. | Pipelined Distributive Arithmetic-based FIR Filter Using Carry Save and Ripple Carry Adder | |
Prashanth et al. | Design and implementation of DA FIR filter for bio-inspired computing architecture | |
Vinitha et al. | Area and energy-efficient approximate distributive arithmetic architecture for LMS adaptive FIR filter | |
Yazhini et al. | Fir filter implementation using modified distributed arithmetic architecture | |
Khan et al. | Low complexity and critical path based VLSI architecture for LMS adaptive filter using distributed arithmetic | |
Kalaiyarasi et al. | An efficient implementation of least mean square adaptive FIR filter based on distributed arithmetic | |
Al-Yateem et al. | Digital Filter based Adder Module Realization High-Speed Switching Functions | |
Reddy et al. | ASIC implementation of distributed arithmetic in adaptive FIR filter | |
Singh et al. | Implementation of high speed FIR filter using serial and parallel distributed arithmetic algorithm | |
Kumar et al. | Low area VLSI implementation of CSLA for FIR filter design | |
Yergaliyev et al. | A Systematic Review on Distributed Arithmetic-Based Hardware Implementation of Adaptive Digital Filters | |
Khan et al. | A new high performance VLSI architecture for LMS adaptive filter using distributed arithmetic | |
Shanthi et al. | Memory based hardware efficient implementation of FIR Filters | |
Tiwari et al. | High throughput adaptive block FIR filter using distributed arithmetic | |
Naik et al. | An efficient reconfigurable FIR digital filter using modified distribute arithmetic technique | |
Khan et al. | VLSI realization of low complexity pipelined LMS filter using distributed arithmetic | |
Student | FPGA implementation of efficient VLSI architecture of DLMS adaptive filter algorithm | |
Sreesh et al. | Performance analysis of fixed point FIR filter architectures | |
Mehendale et al. | DA-based circuits for inner-product computation | |
Prabakaran et al. | High throughput parallelized realization of adaptive FIR filter based on distributive arithmetic using offset binary coding | |
Meher | Low-latency hardware-efficient memory-based design for large-order FIR digital filters | |
Nagabushanam et al. | An Optimized VLSI Implementation of the Least Mean Square (LMS) Adaptive Filter Architecture on the Basis of Distributed Arithmetic Approach | |
kumar Bhadavath et al. | An Efficient Approximation Look Up Table Based Distributed Arithmetic (DA) VLSI Architecture for Finite Impulse Response |