Nothing Special   »   [go: up one dir, main page]

Saritha et al., 2021 - Google Patents

Pipelined Distributive Arithmetic-based FIR Filter Using Carry Save and Ripple Carry Adder

Saritha et al., 2021

Document ID
4313387810834368365
Author
Saritha M
Radhika C
Reddy M
Lavanya M
Karthik A
Vijay V
Vallabhuni R
Publication year
Publication venue
2021 2nd International Conference on Communication, Computing and Industry 4.0 (C2I4)

External Links

Snippet

FIR filter bank play a vital role in any signal processing systems. The FIR filter is used to implement any frequency response digitally. Usually, the FIR filters contain multipliers, adders and many delays. As we know, the number of MAC operations (multiply and …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • G06F7/533Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5332Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by skipping over strings of zeroes or ones, e.g. using the Booth Algorithm
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • G06F7/53Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443Sum of products
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/505Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H21/00Adaptive networks
    • H03H21/0012Digital adaptive filters
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00Networks using digital techniques
    • H03H17/02Frequency selective networks
    • H03H17/0223Computation saving measures; Accelerating measures

Similar Documents

Publication Publication Date Title
Saritha et al. Pipelined Distributive Arithmetic-based FIR Filter Using Carry Save and Ripple Carry Adder
Meher et al. Critical-path analysis and low-complexity implementation of the LMS adaptive algorithm
Meher et al. A high-speed FIR adaptive filter architecture using a modified delayed LMS algorithm
Naga Jyothi et al. Asic implementation of low power, area efficient adaptive fir filter using pipelined da
Mula et al. Algorithm and VLSI architecture design of proportionate-type LMS adaptive filters for sparse system identification
Al-Yateem et al. Digital Filter based Adder Module Realization High-Speed Switching Functions
Meher On efficient retiming of fixed-point circuits
Lan et al. FPGA implementation of an adaptive noise canceller
Reddy et al. ASIC implementation of distributed arithmetic in adaptive FIR filter
Immareddy et al. Adaptive FIR filter design with approximate adder and hybridized multiplier for efficient noise eradication in sensor nodes
Tiwari et al. High throughput adaptive block FIR filter using distributed arithmetic
Amira et al. An FPGA implementation of Walsh-Hadamard transforms for signal processing
Student FPGA implementation of efficient VLSI architecture of DLMS adaptive filter algorithm
Kannan A Design of Low Power and Area efficient FIR Filter using Modified Carry save Accumulator Method
Vijetha et al. Low power low area VLSI implementation of adaptive FIR filter using DA for decision feed back equalizer
Kulkarni et al. Energy-efficient architecture for high-performance FIR adaptive filter using hybridizing CSDTCSE-CRABRA based distributed arithmetic design: Noise removal application in IoT-based WSN
Prabakaran et al. High throughput parallelized realization of adaptive FIR filter based on distributive arithmetic using offset binary coding
Mankar et al. Design and Verification of low power DA-Adaptive digital FIR filter
Kundu et al. Low power design of memoryless adaptive filter using distributed arithmetic unit
Kalaiyarasi et al. An efficient implementation of least mean square adaptive FIR filter based on distributed arithmetic
Padmapriya Design of an optimized twin mode reconfigurable adaptive FIR filter architecture for speech signal processing
Vidal et al. A VLSI parallel architecture of a piecewise linear neural network for nonlinear channel equalization
Prasad et al. Time-Shared LUT-Less Pipelined LMS Adaptive Filter
Usha et al. An efficient adaptive FIR filter based on distributed arithmetic
Chodoker et al. Multiple Constant Multiplication Technique for Configurable Finite Impulse Response Filter Design