Nothing Special   »   [go: up one dir, main page]

Rajasekar et al., 2019 - Google Patents

Implementation of Low Power Null Conventional Logic Function for Configuration Logic Block

Rajasekar et al., 2019

Document ID
2579809395763291041
Author
Rajasekar P
Subash Kumar C
Publication year
Publication venue
Wireless Personal Communications

External Links

Snippet

Todays, transistor level design plays major impact in the power consumption of the VLSI based design. The various logic design models are used to reduce the power consumption that includes synchronous and asynchronous design model. The operation of synchronous …
Continue reading at link.springer.com (other versions)

Classifications

    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/356121—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit with synchronous operation
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00323—Delay compensation
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70—Fault tolerant, i.e. transient fault suppression

Similar Documents

Publication Publication Date Title
Parsan et al. CMOS implementation of static threshold gates with hysteresis: A new approach
Zhao et al. Low-power clocked-pseudo-NMOS flip-flop for level conversion in dual supply systems
Toprak et al. Low-power current mode logic for improved DPA-resistance in embedded systems
Bisdounis et al. A comparative study of CMOS circuit design styles for low-power high-speed VLSI circuits
Bhutada et al. Complex clock gating with integrated clock gating logic cell
Stojanovic et al. A unified approach in the analysis of latches and flip-flops for low-power systems
Rajasekar et al. Implementation of Low Power Null Conventional Logic Function for Configuration Logic Block
Azimi et al. Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source
Sakib et al. Implementation of finfet based static ncl threshold gates: An analysis of design choice
Bajpai et al. LECTOR incorporated differential cascode voltage swing logic (L-DCVSL)
Al Zahrani et al. Glitch-free design for multi-threshold CMOS NCL circuits
Owda et al. High performance and low power dynamic circuit design
Lee et al. Low power null convention logic circuit design based on DCVSL
Singh et al. Static-switching pulse domino: A switching-aware design technique for wide fan-in dynamic multiplexers
Sakthivel et al. Energy efficient low area error tolerant adder with higher accuracy
Vakil et al. Comparitive analysis of null convention logic and synchronous CMOS ripple carry adders
US6329846B1 (en) Cross-coupled dual rail dynamic logic circuit
Sudhakar et al. Multi objective analysis of NCL threshold gates with return to zero protocols
CN116686218A (en) Gao Xiaomu Lec element implementation for high bit width asynchronous applications
Hassoune et al. Dynamic differential self-timed logic families for robust and low-power security ICs
Parsan et al. Cmos implementation of threshold gates with hysteresis
Metku et al. Novel area-efficient null convention logic based on cmos and gate diffusion input (Gdi) hybrid
Singar et al. A Glitch‐Free Novel DET‐FF in 22 nm CMOS for Low‐Power Application
Moyal et al. Synthesis of dual mode logic
Kumre Power and delay analysis of one bit adders