Wang et al., 2011 - Google Patents
Area and power-efficient innovative congestion-aware Network-on-Chip architectureWang et al., 2011
- Document ID
- 15526355986076362394
- Author
- Wang C
- Hu W
- Lee S
- Bagherzadeh N
- Publication year
- Publication venue
- Journal of Systems Architecture
External Links
Snippet
This paper proposes a novel Network-on-Chip architecture that not only enhances network transmission performance while maintaining a feasible implementation cost, but also provides a power-efficient solution for interconnection network scenarios. Diagonally-linked …
- 238000000034 method 0 abstract description 27
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
- G06F15/17368—Indirect interconnection networks non hierarchical topologies
- G06F15/17387—Three dimensional, e.g. hypercubes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/06—Deflection routing, e.g. hot-potato routing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/12—Shortest path evaluation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/70—Fault tolerant, i.e. transient fault suppression
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Wang et al. | Area and power-efficient innovative congestion-aware Network-on-Chip architecture | |
Trik et al. | A hybrid selection strategy based on traffic analysis for improving performance in networks on chip | |
Lotfi-Kamran et al. | EDXY–A low cost congestion-aware routing algorithm for network-on-chips | |
Ascia et al. | Implementation and analysis of a new selection strategy for adaptive routing in networks-on-chip | |
Fu et al. | An abacus turn model for time/space-efficient reconfigurable routing | |
Wang et al. | Design and evaluation of a high throughput qos-aware and congestion-aware router architecture for network-on-chip | |
Tran et al. | RoShaQ: High-performance on-chip router with shared queues | |
Wang et al. | Scalable load balancing congestion-aware Network-on-Chip router architecture | |
Hu et al. | DMesh: a diagonally-linked mesh network-on-chip architecture | |
Wang et al. | Congestion-aware network-on-chip router architecture | |
Rahmati et al. | Power-efficient deterministic and adaptive routing in torus networks-on-chip | |
Yu-hang et al. | Xtorus: An extended torus topology for on-chip massive data communication | |
Effiong et al. | Distributed and dynamic shared-buffer router for high-performance interconnect | |
Taheri et al. | ON–OFF: a reactive routing algorithm for dynamic thermal management in 3D NoCs | |
Agyeman et al. | An efficient 2d router architecture for extending the performance of inhomogeneous 3d noc-based multi-core architectures | |
Wang et al. | Area and power-efficient innovative network-on-chip architecurte | |
Charif et al. | A dynamic sufficient condition of deadlock-freedom for high-performance fault-tolerant routing in networks-on-chips | |
Daneshtalab et al. | A systematic reordering mechanism for on-chip networks using efficient congestion-aware method | |
Gaffour et al. | A new congestion-aware routing algorithm in network-on-chip: 2D and 3D comparison | |
Yaghini et al. | On the design of hybrid routing mechanism for mesh-based network-on-chip | |
Singh et al. | Energy efficient and congestion-aware router design for future NoCs | |
Rezaei et al. | Fault-tolerant 3-D network-on-chip design using dynamic link sharing | |
Ma et al. | Holistic routing algorithm design to support workload consolidation in NoCs | |
Zhu et al. | BiLink: A high performance NoC router architecture using bi-directional link with double data rate | |
Jiao et al. | Performance analysis and optimization for homogenous multi-core system based on 3D Torus Network on Chip |