Eshaghian-Wilner et al., 2004 - Google Patents
The systolic reconfigurable meshEshaghian-Wilner et al., 2004
View PDF- Document ID
- 14529400496883318863
- Author
- Eshaghian-Wilner M
- Miller R
- Publication year
- Publication venue
- Parallel Processing Letters
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Snippet
In this paper, we introduce the Systolic Reconfigurable Mesh (SRM), which combines aspects of the reconfigurable mesh with that of systolic arrays. Every processor controls a local switch that can be reconfigured during every clock cycle in order to control the physical …
- 230000003068 static 0 description 20
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- G06F15/8007—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
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- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
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- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
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