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Wankar et al., 2009 - Google Patents

Reconfigurable Architectures and Algorithms: A Research Survey.

Wankar et al., 2009

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Document ID
12356477367185275893
Author
Wankar R
Akerkar R
Publication year
Publication venue
Int. J. Comput. Sci. Appl.

External Links

Snippet

Ever since the introduction of the Dynamically Reconfigurable Buses, the architecture gained a lot of popularity amongst the researchers and scientists for its high performance computing with general purpose processor used. It is a powerful model of computation in …
Continue reading at www.researchgate.net (PDF) (other versions)

Classifications

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    • G06F15/80—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
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    • G06F9/3895—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
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