Nothing Special   »   [go: up one dir, main page]

Leung, 1993 - Google Patents

On-line fault identification in multistage interconnection networks

Leung, 1993

Document ID
12003536607947535028
Author
Leung Y
Publication year
Publication venue
Parallel computing

External Links

Snippet

If a multistage interconnection network (MIN) has faulty switching elements, the data may be blocked or may go along an incorrect path. In this paper, we propose an on-line fault identification method for automatically locating the faulty switch modules (ie the faulty IC …
Continue reading at www.sciencedirect.com (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/163Interprocessor communication
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems
    • H04L12/56Packet switching systems
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/02Details
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. local area networks [LAN], wide area networks [WAN]
    • H04L12/42Loop networks
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer

Similar Documents

Publication Publication Date Title
Kumar et al. Augmented shuffle-exchange multistage interconnection networks
US4409656A (en) Serial data bus communication system
US6233702B1 (en) Self-checked, lock step processor pairs
US8018837B2 (en) Self-healing chip-to-chip interface
EP0430569B1 (en) Fault tolerant interconnection networks
JPH05298134A (en) Method and mechanism for processing of processing error in computer system
US8112658B2 (en) Row fault detection system
Kumar et al. Failure dependent performance analysis of a fault-tolerant multistage interconnection network
Azad et al. From online fault detection to fault management in Network-on-Chips: A ground-up approach
DeHon et al. METRO: A router architecture for high-performance, short-haul routing networks
US20040078732A1 (en) SMP computer system having a distributed error reporting structure
US3465132A (en) Circuits for handling intentionally mutated information with verification of the intentional mutation
Azad et al. Holistic approach for fault-tolerant network-on-chip based many-core systems
Leung On-line fault identification in multistage interconnection networks
Somani Sequential fault occurrence and reconfiguration in system level diagnosis
Bhowmik et al. A time-optimized scheme towards analysis of channel-shorts in on-chip networks
DeHon Robust, high-speed network design for large-scale multiprocessing
Rambo et al. Failure analysis of a network-on-chip for real-time mixed-critical systems
Olajide et al. An approach to improve the availability of a traffic light system
Lee et al. Some directed graph theorems for testing the dynamic full access property of multistage interconnection networks
Tamir Fault tolerance for VLSI multicomputers
Nambinina et al. Adaptive Time-Triggered Network-on-Chip Architecture: Enhancing Safety
DeHon et al. Transit Note# 96 METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks
CN115526768A (en) Two-dimensional convolutional neural network architecture based on video stream processing and provided with fault-tolerant mechanism
Heil et al. Fault-tolerant self-organized mechanism for networked reconfigurable MPSoC