Prakash et al., 2022 - Google Patents
Simultaneous optimization of the area, wirelength and TSVs in a 3D IC designPrakash et al., 2022
View PDF- Document ID
- 1107855394682900280
- Author
- Prakash A
- Lal R
- Publication year
- Publication venue
- Sādhanā
External Links
Snippet
The technology of a three-dimensional integrated circuit (3D-IC) is an emerging approach for improving performance. In comparison to a standard 2-D IC design, which arranges all of the devices on a single planar layer, a 3D-IC stacking of many tiers enables more devices to …
- 241000724291 Tobacco streak virus 0 title abstract description 11
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5072—Floorplanning, e.g. partitioning, placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5077—Routing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Hsu et al. | TSV-aware analytical placement for 3-D IC designs based on a novel weighted-average wirelength model | |
Hsu et al. | TSV-aware analytical placement for 3D IC designs | |
US8689164B2 (en) | Method of analytical placement with weighted-average wirelength model | |
Li et al. | Fast fixed-outline 3-D IC floorplanning with TSV co-placement | |
Li et al. | Integrating dynamic thermal via planning with 3D floorplanning algorithm | |
Sait et al. | Design partitioning and layer assignment for 3D integrated circuits using tabu search and simulated annealing | |
Lin et al. | Thermal-aware floorplanning and TSV-planning for mixed-type modules in a fixed-outline 3-D IC | |
Pangracious et al. | Three-dimensional integration: A more than Moore technology | |
Sivakumar et al. | Optimization of thermal aware multilevel routing for 3D IC | |
Wen et al. | Via-based redistribution layer routing for InFO packages with irregular pad structures | |
Vinay Kumar et al. | Optimal floor planning in VLSI using improved adaptive particle swarm optimization | |
Prakash et al. | Simultaneous optimization of the area, wirelength and TSVs in a 3D IC design | |
Ahmed et al. | TSV-and delay-aware 3D-IC floorplanning | |
US10133841B1 (en) | Methods, systems, and computer program product for implementing three-dimensional integrated circuit designs | |
Cuesta et al. | 3D thermal-aware floorplanner using a MILP approximation | |
Lin et al. | Routability-driven TSV-aware floorplanning methodology for fixed-outline 3-D ICs | |
Tabrizi et al. | A fast force-directed simulated annealing for 3D IC partitioning | |
Hentschke et al. | 3D-vias aware quadratic placement for 3D VLSI circuits | |
Zhu et al. | Floorplanning for 3D-IC with Through-Silicon via co-design using simulated annealing | |
Fu et al. | Coplace: Coherent placement engine with layout-aware partitioning for 3d ics | |
Ravichandran et al. | Physical layout automation for system-on-packages | |
Li et al. | Design methodology of fault-tolerant custom 3D network-on-chip | |
Chen et al. | Lagrangian relaxation based inter-layer signal via assignment for 3-D ICs | |
Huang et al. | On Legalization of Die Bonding Bumps and Pads for 3D ICs | |
Yang et al. | Physical co-design for micro-fluidically cooled 3D ICs |