Nothing Special   »   [go: up one dir, main page]

Zhu et al., 2018 - Google Patents

Floorplanning for 3D-IC with Through-Silicon via co-design using simulated annealing

Zhu et al., 2018

Document ID
460718277719045381
Author
Zhu H
Zhang M
He Y
Huang Y
Publication year
Publication venue
2018 IEEE International Symposium on Electromagnetic Compatibility and 2018 IEEE Asia-Pacific Symposium on Electromagnetic Compatibility (EMC/APEMC)

External Links

Snippet

In this paper, we will propose a method for floorplanning in three dimensional integrated circuits (3D-IC), considering the impact of Through-Silicon-Via (TSV). In 3D-IC, multiple device layers are vertically stacked and interconnected by excessive amount of TSVs which …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072—Floorplanning, e.g. partitioning, placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5077—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78—Power analysis and optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/12—Design for manufacturability
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure

Similar Documents

Publication Publication Date Title
Hsu et al. TSV-aware analytical placement for 3-D IC designs based on a novel weighted-average wirelength model
Hsu et al. TSV-aware analytical placement for 3D IC designs
Cong et al. Thermal-aware 3D IC placement via transformation
Tsai et al. Through-silicon via planning in 3-D floorplanning
Li et al. Fast fixed-outline 3-D IC floorplanning with TSV co-placement
Lim Design for high performance, low power, and reliable 3D integrated circuits
Ku et al. Compact-2D: A physical design methodology to build two-tier gate-level 3-D ICs
Hsu et al. Stacking signal TSV for thermal dissipation in global routing for 3-D IC
US10831972B2 (en) Capacity model for global routing
Kim et al. Block-level 3D IC design with through-silicon-via planning
Lee et al. Co-optimization and analysis of signal, power, and thermal interconnects in 3-D ICs
Zhu et al. Floorplanning for 3D-IC with Through-Silicon via co-design using simulated annealing
Satomi et al. Thermal placement on PCB of components including 3D ICs
US8863062B2 (en) Methods and apparatus for floorplanning and routing co-design
Lin et al. Thermal-aware floorplanning and TSV-planning for mixed-type modules in a fixed-outline 3-D IC
Zhao et al. Thermal and wirelength optimization with TSV assignment for 3-D-IC
CN102682163B (en) Grid optimization method for through silicon via (TSV) positions in automatic layout of three-dimensional (3D) integrated circuit
Lin et al. Routability-driven TSV-aware floorplanning methodology for fixed-outline 3-D ICs
Chen et al. Clock-tree synthesis with methodology of reuse in 3D-IC
US6625792B1 (en) Semiconductor design system, semiconductor integrated circuit, semiconductor design method and storage medium storing semiconductor design program
Pathak et al. Performance and thermal-aware Steiner routing for 3-D stacked ICs
CN103886148A (en) Automatic layout method for positions of heat through holes in 3D integrated circuit
Zhao et al. TSV assignment of thermal and wirelength optimization for 3D-IC routing
Prakash et al. Simultaneous optimization of the area, wirelength and TSVs in a 3D IC design
Jagtap et al. A methodology for early exploration of TSV placement topologies in 3D stacked ICs