Nothing Special   »   [go: up one dir, main page]

Nagalaxmi et al., 2022 - Google Patents

Design and performance analysis of low latency routing algorithm based NoC for MPSoC

Nagalaxmi et al., 2022

View PDF
Document ID
10747007073978468553
Author
Nagalaxmi T
Rao E
Chandrasekhar P
Publication year
Publication venue
International Journal of Communication Networks and Information Security

External Links

Snippet

Abstract The Network on Chip is appropriate where System-on-Chip technology is scalable and adaptable. The Network on Chip is a new communication architecture with a number of benefits, including scalability, flexibility, and reusability, for applications built on …
Continue reading at core.ac.uk (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5077—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding through a switch fabric
    • H04L49/253—Connections establishment or release between ports
    • H04L49/254—Centralized controller, i.e. arbitration or scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding through a switch fabric
    • H04L49/256—Routing or path finding in ATM switching fabrics
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/06—Deflection routing, e.g. hot-potato routing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Switching fabric construction
    • H04L49/109—Switching fabric construction integrated on microchip, e.g. switch-on-chip

Similar Documents

Publication Publication Date Title
de Mello et al. Evaluation of routing algorithms on mesh based nocs
Jiang et al. A low-latency and low-power hybrid scheme for on-chip networks
Fadakar Noghondar et al. A low-cost and latency bypass channel-based on-chip network
Balakrishnan et al. Design and implementation of congestion aware router for network-on-chip
Wang et al. Area and power-efficient innovative congestion-aware Network-on-Chip architecture
Agyeman et al. An efficient 2d router architecture for extending the performance of inhomogeneous 3d noc-based multi-core architectures
Nagalaxmi et al. Design and performance analysis of low latency routing algorithm based NoC for MPSoC
Zhou et al. A router architecture with dual input and dual output channels for Networks-on-Chip
González et al. IPDeN: Real-Time deflection-based NoC with in-order flits delivery
Avramenko et al. QoSinNoC: analysis of QoS-aware NoC architectures for mixed-criticality applications
Parane et al. FPGA based NoC simulation acceleration framework supporting adaptive routing
Rezaei et al. Fault-tolerant 3-D network-on-chip design using dynamic link sharing
Seifi et al. A clustered NoC in group communication
Dridi et al. Modeling and validation of a mixed-criticality NoC router using the IF language
Gogula et al. Design of a VLSI Router for the Faster Data Transmission Using Buffer
Parane et al. YaNoC: Yet another network-on-chip simulation acceleration engine supporting congestion-aware adaptive routing using FPGAs
Zulkefli et al. A efficacy of different buffer size on latency of network on chip (NoC)
Gugulothu et al. Design and Implementation of various topologies for Networks on Chip and its performance evolution
Nunes et al. IPNoSys III: SDN Paradigm in a non-conventional NoC-based Processor
Bamberg et al. Interconnect architectures for 3d technologies
Panem et al. Performance analysis of 16× 16, 32× 32, 64× 64 2-D mesh topologies for network on chip
Fell RECONNECT: A flexible Router Architecture for Network-on-Chips
Sharma et al. Performance of router design for Network-on-Chip implementation
Prakash Managing HBM's Bandwidth in Multi-Die FPGAs Using Overlay NoCs
Sun et al. Design and implementation of the wormhole virtual channel NoC router