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Kim et al., 2020 - Google Patents

Architecture, chip, and package codesign flow for interposer-based 2.5-D chiplet integration enabling heterogeneous IP reuse

Kim et al., 2020

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Document ID
9775319211865872564
Author
Kim J
Murali G
Park H
Qin E
Kwon H
Chekuri V
Rahman N
Dasari N
Singh A
Lee M
Torun H
Roy K
Swaminathan M
Mukhopadhyay S
Krishna T
Lim S
Publication year
Publication venue
IEEE Transactions on Very Large Scale Integration (VLSI) Systems

External Links

Snippet

A new trend in system-on-chip (SoC) design is chiplet-based IP reuse using 2.5-D integration. Complete electronic systems can be created through the integration of chiplets on an interposer, rather than through a monolithic flow. This approach expands access to a …
Continue reading at www.academia.edu (PDF) (other versions)

Classifications

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