Nothing Special   »   [go: up one dir, main page]

Stratix - Google Patents

2. Stratix II GX Architecture

Stratix

View PDF
Document ID
9107604556559258424
Author
Stratix T

External Links

Snippet

Transceivers Stratix® II GX devices incorporate dedicated embedded circuitry on the right side of the device, which contains up to 20 high-speed 6.375-Gbps serial transceiver channels. Each Stratix II GX transceiver block contains four full-duplex channels and …
Continue reading at www.intel.com (PDF) (other versions)

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/04—Distributors combined with modulators or demodulators
    • H04J3/047—Distributors with transistors or integrated circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Application specific switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. local area networks [LAN], wide area networks [WAN]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation

Similar Documents

Publication Publication Date Title
US8184651B2 (en) PLD architecture optimized for 10G Ethernet physical layer solution
US7098685B1 (en) Scalable serializer-deserializer architecture and programmable interface
US7538578B2 (en) Multiple data rates in programmable logic device serial interface
US6650141B2 (en) High speed interface for a programmable interconnect circuit
US10009198B2 (en) Configurable multi-lane scrambler for flexible protocol support
EP1248372B1 (en) Programmable logic device with high speed serial interface circuitry
CN111193525B (en) Multipath clock and data recovery
US7557605B2 (en) Heterogeneous configurable integrated circuit
US8732375B1 (en) Multi-protocol configurable transceiver with independent channel-based PCS in an integrated circuit
US20090063889A1 (en) Aligning data on parallel transmission lines
JP2007060645A (en) Lane-to-lane skew reduction in multi-channel, high-speed, transceiver circuitry
US7706417B1 (en) Method of and circuit for generating a plurality of data streams
US6888376B1 (en) Multiple data rates in programmable logic device serial interface
US7474612B1 (en) Multi-function bypass port and port bypass circuit
US7180972B1 (en) Clock signal circuitry for multi-protocol high-speed serial interface circuitry
US6867616B1 (en) Programmable logic device serial interface having dual-use phase-locked loop circuitry
Stratix 2. Stratix II GX Architecture
US7365568B1 (en) Method and circuit for reducing programmable logic pin counts for large scale logic
Handbook Section I. Stratix II GX Device Data Sheet
Block et al. into four channels.
US10250347B1 (en) Routing-efficient time division multiplexing (TDM) data path circuitry
Lujan et al. Comparative analysis between the Stratix II (Altera) and Virtex 4 (Xilinx) for implementing a LVDS bus receiver
Zhang et al. Design of a high speed XAUI based on dynamic reconfigurable transceiver IP core
Yoon et al. A 103.125-Gb/s reverse gearbox IC in 40-nm CMOS for supporting legacy 10-and 40-GbE links
Made Section V. IP & Design Considerations