Nothing Special   »   [go: up one dir, main page]

Zhao et al., 2011 - Google Patents

Low-power clock tree design for pre-bond testing of 3-D stacked ICs

Zhao et al., 2011

View PDF
Document ID
6955823759476995079
Author
Zhao X
Lewis D
Lee H
Lim S
Publication year
Publication venue
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

External Links

Snippet

Pre-bond testing of 3-D stacked integrated circuits (ICs) involves testing each individual die before bonding. The overall yield of 3-D ICs improves with pre-bond testability because manufacturers can avoid stacking defective dies with good ones. However, pre-bond …
Continue reading at www.researchgate.net (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5077Routing
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5036Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072Floorplanning, e.g. partitioning, placement
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/505Logic synthesis, e.g. technology mapping, optimisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70Fault tolerant, i.e. transient fault suppression
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10Distribution of clock signals, e.g. skew

Similar Documents

Publication Publication Date Title
Zhao et al. Low-power clock tree design for pre-bond testing of 3-D stacked ICs
Restle et al. A clock distribution network for microprocessors
Zhao et al. Pre-bond testable low-power clock tree design for 3D stacked ICs
CN107066681B (en) Integrated circuit and computer-implemented method of manufacturing an integrated circuit
Zhao et al. Low-power and reliable clock network design for through-silicon via (TSV) based 3D ICs
Kim et al. Clock tree synthesis for TSV-based 3D IC designs
Nam et al. Modern circuit placement: best practices and results
CN103294842A (en) Semiconductor device design method, system and computer-readable medium
Kim et al. Chiplet/interposer co-design for power delivery network optimization in heterogeneous 2.5-D ICs
Lin et al. Pulsed-latch utilization for clock-tree power optimization
US9064081B1 (en) Generating database for cells routable in pin layer
Kim et al. Clock tree synthesis with pre-bond testability for 3D stacked IC designs
Choi et al. Probe3. 0: A systematic framework for design-technology pathfinding with improved design enablement
Vishnu et al. Clock tree synthesis techniques for optimal power and timing convergence in soc partitions
Zhu et al. Design automation and test solutions for monolithic 3D ICs
Jung et al. Design methodologies for low-power 3-D ICs with advanced tier partitioning
Healy et al. A novel TSV topology for many-tier 3D power-delivery networks
Kim et al. Resource allocation and design techniques of prebond testable 3-D clock tree
Kabir et al. Holistic Chiplet–Package Co-Optimization for Agile Custom 2.5-D Design
Liu et al. Whitespace-aware TSV arrangement in 3-D clock tree synthesis
Healy et al. Power-supply-network design in 3D integrated systems
Li et al. Partitioning-based approach to fast on-chip decoupling capacitor budgeting and minimization
Mamikonyan et al. IR drop estimation and optimization on DRAM memory using machine learning algorithms
Oh et al. Thermal-aware 3D symmetrical buffered clock tree synthesis
Cheng et al. TSV minimization for circuit—partitioned 3D SoC test wrapper design