Reyserhove et al., 2018 - Google Patents
Margin elimination through timing error detection in a near-threshold enabled 32-bit microcontroller in 40-nm CMOSReyserhove et al., 2018
- Document ID
- 6937928893815904492
- Author
- Reyserhove H
- Dehaene W
- Publication year
- Publication venue
- IEEE Journal of Solid-State Circuits
External Links
Snippet
This paper presents a near-threshold operating voltage timing error detecting 32-bit microcontroller system. The lightweight in situ error detection and correction technique uses a soft-edge flip-flop combined with in-latch transition detection and a set-dominant error …
- 238000001514 detection method 0 title abstract description 72
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/24—Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
- G06F1/3234—Action, measure or step performed to reduce power consumption
- G06F1/3237—Power saving by disabling clock generation or distribution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/70—Fault tolerant, i.e. transient fault suppression
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318594—Timing aspects
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00323—Delay compensation
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Reyserhove et al. | Margin elimination through timing error detection in a near-threshold enabled 32-bit microcontroller in 40-nm CMOS | |
Kwon et al. | Razor-lite: A light-weight register for error detection by observing virtual supply rails | |
Bowman et al. | Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance | |
Bowman et al. | A 45 nm resilient microprocessor core for dynamic variation tolerance | |
Das et al. | RazorII: In situ error detection and correction for PVT and SER tolerance | |
Choudhury et al. | TIMBER: Time borrowing and error relaying for online timing error resilience | |
KR102327567B1 (en) | A timing violation resilient asynchronous template | |
Mitra et al. | Logic soft errors in sub-65nm technologies design and CAD challenges | |
Choudhury et al. | Time-borrowing circuit designs and hardware prototyping for timing error resilience | |
GB2481100A (en) | Detecting marginal timing operation in a logic pipeline | |
Alghareb et al. | Designing and evaluating redundancy-based soft-error masking on a continuum of energy versus robustness | |
Valadimas et al. | The time dilation technique for timing error tolerance | |
Berry et al. | IBM z14: Processor characterization and power management for high-reliability mainframe systems | |
Sai et al. | Multi-path aging sensor for cost-efficient delay fault prediction | |
Tarawneh et al. | Eliminating synchronization latency using sequenced latching | |
Lin et al. | A low-cost radiation hardened flip-flop | |
Das et al. | Frequency-independent warning detection sequential for dynamic voltage and frequency scaling in ASICs | |
Valadimas et al. | Cost and power efficient timing error tolerance in flip-flop based microprocessor cores | |
Aketi et al. | SERAD: Soft error resilient asynchronous design using a bundled data protocol | |
Kasim et al. | Methodology for detecting glitch on clock, reset and CDC path | |
Kumar et al. | A low power soft error suppression technique for dynamic logic | |
Bowman et al. | Resilient microprocessor design for improving performance and energy efficiency | |
Balef et al. | Timing speculation with optimal in situ monitoring placement and within-cycle error prevention | |
Yang et al. | A low-power timing-error-tolerant circuit by controlling a clock | |
US20080069277A1 (en) | Method and apparatus for modeling signal delays in a metastability protection circuit |