Nothing Special   »   [go: up one dir, main page]

Durgagopal et al., 2022 - Google Patents

Power Optimized Low Pass Digital FIR Filter Using Five Modular Redundancy and Parallel Adding Methods

Durgagopal et al., 2022

Document ID
4072398921255152985
Author
Durgagopal R
Rao D
Publication year
Publication venue
2022 International Conference on Intelligent Controller and Computing for Smart Power (ICICCSP)

External Links

Snippet

The development of fault-tolerant filtering is crucial to the dependability of any communication network or digital signal processors system. FIR filtering with simultaneous error correcting algorithms have been developed, which increase the system's redundancy …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0223—Computation saving measures; Accelerating measures
    • H03H17/0225—Measures concerning the multipliers
    • H03H17/0226—Measures concerning the multipliers comprising look-up tables
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters
    • H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
    • H03H17/0635—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/04—Recursive filters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/388—Skewing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H21/00—Adaptive networks
    • H03H21/0012—Digital adaptive filters
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H2218/00—Indexing scheme relating to details of digital filters
    • H03H2218/10—Multiplier and or accumulator units
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H15/00—Transversal filters

Similar Documents

Publication Publication Date Title
Lyakhov et al. High-performance digital filtering on truncated multiply-accumulate units in the residue number system
Aparna et al. Design and implementation of a high performance multiplier using HDL
Vinay et al. Power efficient FIR filter architecture using distributed arithmetic algorithm
Zhang et al. Low-power reconfigurable FIR filter design based on common operation sharing
Durgagopal et al. Power Optimized Low Pass Digital FIR Filter Using Five Modular Redundancy and Parallel Adding Methods
Mahesh et al. Low area design architecture of xor-mux full adder based discrete wavelet transform
Erdogan et al. High throughput FIR filter design for low power SoC applications
Strandberg et al. Efficient realizations of squaring circuit and reciprocal used in adaptive sample rate notch filters
Arslan et al. Low power implementation of high throughput FIR filters
Thingom et al. FPGA implementation of FIR filter using RADIX-2 r
Liu et al. A pipelined sign-error LMS adaptive filter architecture with low computational complexity
Narasimha et al. Implementation of LOW Area and Power Efficient Architectures of Digital FIR filters
Kannan A Design of Low Power and Area efficient FIR Filter using Modified Carry save Accumulator Method
Maheshwari et al. Design of Efficient Booth Multiplier based Polyphase FIR Filters
Kumar et al. Array Multiplier and CIA based FIR Filter for DSP applications
Saini et al. Area Optimization of FIR Filter and its Implementation on FPGA
Parvatham et al. A novel architecture for an efficient implementation of image compression using 2D-DWT
Ali Cascaded ripple carry adder based SRCSA for efficient FIR filter
Malviya et al. Design of IIR filter using Wallace tree multiplier
Suriya et al. Low power analysis of MAC using modified booth algorithm
Radhakrishnan et al. Design of Low Power and High Speed MAC based FIR Filter using Hybrid Adder and Modified Booth Multiplier
Gnanasekaran et al. Low delay-high compact FIR filter using reduced wallace multiplier
Jayan et al. Implementation of folded FIR filter based on pipelined multiplier array
Dhivya et al. A high speed area efficient FIR filter using floating point dadda algorithm
Shankhwar et al. Configurable Fir Filter Using Different Multiplier Technique