#

systemverilog

Here are 7 public repositories matching this topic...

openhwgroup / core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

verification systemverilog uvm risc-v

Updated Nov 19, 2024
Assembly

vproc / vicuna

RISC-V Zve32x Vector Coprocessor

systemverilog coprocessor risc-v vector-processor

Updated Dec 2, 2023
Assembly

hoangsonww / Digital-Design-Labs

🖥️ A collection of SystemVerilog modules and Assembly programs. This repo includes examples of decoders, encoders, binary adders, and interactive games such as Guessing Game implemented in hardware description and assembly languages, illustrating practical applications in digital systems and microprocessor interfacing.

counter microcontroller encoder assembly decoder verilog finite-state-machine systemverilog guessing-game alu pic16f84a system-design arithmetic-logic-unit carry-look-ahead-adder microcontroller-programming carry-select-adder 3to8decoder

Updated Nov 17, 2024
Assembly

jracevedob / RISC-ARA

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

systemverilog hardware-acceleration instruction-set-architecture risc-v 5g massive-mimo 6g

Updated Nov 16, 2023
Assembly

AminiAria / CPE233Labs

systemverilog assembly-language-programming

Updated Jun 21, 2019
Assembly

expjel / CSE-141L-Project

Processor design project featuring 9-bit ISA 🤖

processor-architecture assembly systemverilog

Updated Mar 16, 2022
Assembly

iremsvn / computer-organization-labs

assembly systemverilog mips-architecture

Updated Mar 31, 2021
Assembly

Improve this page

Add a description, image, and links to the systemverilog topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the systemverilog topic, visit your repo's landing page and select "manage topics."